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Prof. Fayez F. M. El-Sousy
Prof. Fayez F. M. ElProf. Fayez F. M. El--SousySousy
Department of Electrical EngineeringDepartment of Electrical Engineering
College of EngineeringCollege of Engineering
SalmanSalman bin bin AbdulazizAbdulaziz UniversityUniversity
AlAl--KharjKharj, Saudi Arabia, Saudi Arabia
Hardware Specifications,Hardware Specifications,
Memory Interface and Basic Memory Interface and Basic
I/O InterfaceI/O Interface
Microprocessor 8086/8088Microprocessor 8086/8088
Prof. Fayez F. M. El-Sousy
Objectives of Objectives of Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� Upon completion of this chapter, you will be able to:Upon completion of this chapter, you will be able to:
�� Describe function of each 8086 & 8088 pin.Describe function of each 8086 & 8088 pin.
�� Understand the microprocessor's DC characteristics and Understand the microprocessor's DC characteristics and
indicate its fanindicate its fan--out to common logic families.out to common logic families.
�� Use the clock generator chip (8284A) to provide the clock Use the clock generator chip (8284A) to provide the clock
for the microprocessor.for the microprocessor.
�� Connect buffers and latches to the buses.Connect buffers and latches to the buses.
�� Interpret the timing diagrams.Interpret the timing diagrams.
�� Describe wait states and connect the circuitry required to Describe wait states and connect the circuitry required to
cause various numbers of waits.cause various numbers of waits.
�� Explain the difference between minimum and maximum Explain the difference between minimum and maximum
mode operation.mode operation.
Prof. Fayez F. M. El-Sousy
�� IntroductionIntroduction
�� In this chapter, the pin functions of both the In this chapter, the pin functions of both the
80868086 and and 80888088 microprocessors are detailed and microprocessors are detailed and
information is provided on the following information is provided on the following
hardware topics: hardware topics: clock generationclock generation, , bus bus
bufferingbuffering, , bus latchingbus latching, , timingtiming, , wait stateswait states, and , and
minimum mode operationminimum mode operation versusversus maximum maximum
mode operationmode operation..
�� These simple microprocessors are explained as These simple microprocessors are explained as
an introduction to the an introduction to the Intel microprocessorIntel microprocessor
family.family.
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
Prof. Fayez F. M. El-Sousy
��Data bus Data bus
�� Internally both are Internally both are 16 bit data bus16 bit data bus
��Externally Externally
��80880888 has has 8 bit8 bit bus AD0 to AD7bus AD0 to AD7
��80880866 has has 16 bit16 bit bus AD0 to AD15bus AD0 to AD15
�� ALE: address latch enable is needed ALE: address latch enable is needed
��Address bus : 20 pinsAddress bus : 20 pins
��Needs a latch to latch the addressNeeds a latch to latch the address
��Most widely used latch is 74LS373 Most widely used latch is 74LS373
��Data bus width is the only major difference.Data bus width is the only major difference.
��Thus 808Thus 80866 transfers transfers 1616--bit databit data more efficientlymore efficiently
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
Prof. Fayez F. M. El-Sousy
��Data bus 808Data bus 80866
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328086
Data BusData Bus
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Data bus 808Data bus 80888
GND
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
A15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
SS0
MN/MX
RD
WR
IO/M
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328088
Data BusData Bus
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Microprocessor Microprocessor 80880866
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328086
BHE:BHE: Bus High EnableBus High Enable
Used with ‘86 to
distinguish between high
and low byte
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Microprocessor Microprocessor 80880866
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328086
NMI:NMI: Nonmaskable interruptNonmaskable interrupt
Edge triggered input signal
from low to high
Input to µp.
Cause µp to jump into
interrupt vector after
finishing current instruction
Can not be masked by
software
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Microprocessor Microprocessor 80880866
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328086
INTR:INTR: Interrupt RequestInterrupt Request
Active high level-
triggered input
Monitored by µp at the
last clock cycle after each
instruction.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Microprocessor Microprocessor 80880866
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328086
CLK: ClockCLK: Clock
µµµµµµµµp require a very accurate p require a very accurate
clock for synchronizingclock for synchronizing
Intel has designed 8284 clock Intel has designed 8284 clock
generatorgenerator
CLKCLK is an input and is an input and
connected to 8284 clock connected to 8284 clock
generatorgenerator
Any irregularity cause the Any irregularity cause the
CPUCPU toto
malfunction malfunction
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Microprocessor Microprocessor 80880866
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328086
RESET: ResetRESET: Reset
••Terminate present activity of Terminate present activity of µµµµµµµµpp
••Input to Input to µµµµµµµµp p
••Active highActive high
••Signal comes from 8284 Clock generatorSignal comes from 8284 Clock generator
••After reset After reset µµµµµµµµp will contains the following Data:p will contains the following Data:
EMPTYEMPTYQUEUEQUEUE
CLEARCLEARFLAGFLAG
0000H0000HIPIP
0000H0000HESES
0000H0000HSSSS
0000H0000HDSDS
FFFFHFFFFHCSCS
ContentsContentsCPUCPU
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Microprocessor Microprocessor 80880866
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328086
READYREADY:
•Input signal
•Used to insert a wait state for
slower memories and IO.
•It inserts a wait state when it is
low
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Microprocessor Microprocessor 80880866
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328086
TESTTEST
•Input signal FROM 8087
Coprocessor
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Microprocessor Microprocessor 80880866
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328086
Pin specifying the operation Pin specifying the operation
ModeMode
•• LowLow � Maximum Mode
•• HighHigh � Minimum Mode
The function of pins 24 through 31 ofThe function of pins 24 through 31 of
8088 8088 andand 80868086 varies depending upon varies depending upon
whether the whether the µµµµµµµµpp is in max or min modeis in max or min mode
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Microprocessor Microprocessor 8088086: Min. Mode Versus Max. Mode6: Min. Mode Versus Max. Mode
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
328086
Min Mode
Logic 1
Max Mode
Logic 0
GT0/ RQ
GT1/ RQLOCKS2S1S0QS0
QS1
The function of pins The function of pins 2424 through through 3131 ofof 8088 8088 andand 80868086 varies varies
depending upon whether the depending upon whether the µµµµµµµµpp is in max or min modeis in max or min mode
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��Microprocessor Microprocessor 80880866: Min. : Min. ModeMode VersusVersus Max. Max. ModeMode
�� In Min Mode:In Min Mode:
��Pins Pins 24 24 –– 3131 are used as memory and are used as memory and I/OI/O control control signalssignals
��The control signal are generated internally by The control signal are generated internally by 80880888, 808, 80866
��Thus Min Mode is More cost efficient Thus Min Mode is More cost efficient
��Pins Pins 24 24 –– 3131 of of 80880888, , 80880866 are functioning similarly are functioning similarly to to 80880855
��Thus Thus 80880855 peripheral can be used with this mode.peripheral can be used with this mode.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� In Min Mode:In Min Mode:
��Pins Pins 24 24 –– 31 31 function are shown in the following function are shown in the following table:table:
HOLDHOLD3131
HLDAHLDA3030
WRWR2929
M/M/IOIO (8086) or IO/(8086) or IO/MM (8088)(8088) 2828
DT/DT/RR2727
DENDEN2626
ALEALE2525
INTAINTA2424
FunctionFunctionPinPin
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� In Min Mode:In Min Mode:
�� (24) (24) INTAINTA INTINTerrupterrupt AAcknowledgecknowledge
��Active low output signalActive low output signal
�� Inform interrupt controller that an interrupt has Inform interrupt controller that an interrupt has
occurred occurred
��And the vector number is available on the lower 8 And the vector number is available on the lower 8
lines of the data bus.lines of the data bus.
�� (25) (25) ALEALE –– AAddress ddress LLatch atch EEnablenable ––
��Active high output signalActive high output signal
�� Indicate that a valid address is available on the Indicate that a valid address is available on the
external address busexternal address bus
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��In Min Mode:In Min Mode:
�� (26) (26) DENDEN –– DData ata EEnablenable ––
��Active low output signalActive low output signal
��Enable 74LS245, which allows isolation of the Enable 74LS245, which allows isolation of the
CPU from system BusCPU from system Bus
�� (27) (27) DT/DT/RR –– DDataata TTransmitransmit RReceiveeceive ––
��Active low output signalActive low output signal
��Used to control the Data Direction of data flow Used to control the Data Direction of data flow
through 74LS245 through 74LS245 tranceivertranceiver
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��In Min Mode:In Min Mode:
�� (26) (26) DENDEN –– DData ata EEnablenable ––
��Active low output signalActive low output signal
��Enable 74LS245, which allows isolation of the Enable 74LS245, which allows isolation of the
CPU from system BusCPU from system Bus
�� (28)(28) IO/IO/MM (808(80888)) oror IOIO/M/M (808(80866))
��Memory or Input/outputMemory or Input/output
��Indicate whether address bus is accessing Indicate whether address bus is accessing
memory or input / output devicememory or input / output device
��See the difference between 808See the difference between 80888 and and 80880866
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��In Min Mode:In Min Mode:
�� (29) (29) WRWR WrWriteite
��Active low output signalActive low output signal
��Indicating that Data on the bus is being written Indicating that Data on the bus is being written
to memory or I/O deviceto memory or I/O device
�� (30) HLDA (30) HLDA –– HolHoldd AAcknowledgecknowledge ––
��Active high Active high o/po/p signal used after HOLD.signal used after HOLD.
��Indicate that CPU allows to the DMA to Use Indicate that CPU allows to the DMA to Use
buses.buses.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��In Min Mode:In Min Mode:
�� (31) (31) HOLDHOLD –– HoldHold ––
��Active high input from DMA controllerActive high input from DMA controller
��Indicates that device requesting to control the Indicates that device requesting to control the
local buseslocal buses
��SSOSSO –– Status LineStatus Line ––
��For 88 only, an output signal that can be used For 88 only, an output signal that can be used
along with the IO/M and DT/R to decode the along with the IO/M and DT/R to decode the
status of the current bus cycle.status of the current bus cycle.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��In Min Mode:In Min Mode:
��SSOSSO –– Status LineStatus Line ––
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��In Min Mode:In Min Mode:
��For the 808For the 80888/808/80866 in min mode some control signal in min mode some control signal must be generated using logic gate.must be generated using logic gate.
��In max mode these signal are provided by the 8288In max mode these signal are provided by the 8288
��88/86 in min mode provides 3 signals88/86 in min mode provides 3 signals
��RD, WRRD, WR, , andand IO/MIO/M oror M/IOM/IO
��Using these 3 signal 4 important signal must be Using these 3 signal 4 important signal must be generated.generated.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��In Min Mode:In Min Mode:
��These signals are shown in the following table:These signals are shown in the following table:
Never Never
Happened Happened
XX0000
IOWIOW110011
IORIOR111100
MEMWMEMW000011
MEMRMEMR001100
SignalSignalIO/IO/MMWRWRRDRD
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��In Max Mode:In Max Mode:
��Some control signal are generated externally by Some control signal are generated externally by
the the 82888288 bus controllerbus controller
��Some Some pinspins are used for new features available are used for new features available
only for only for Max ModeMax Mode
��Mostly used when Mostly used when CPUCPU is used with Math is used with Math
CoprocessorCoprocessor
��IBM PC/XT and compatible use IBM PC/XT and compatible use 80880888, 808, 80866 with with
80880877 coprocessorcoprocessor
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� In Max Mode:In Max Mode:
�� (24 and 25) (24 and 25) QS0QS0 and and QS1QS1 –– Queue StatusQueue Status ––
�� Give information to the system about the Queue inside Give information to the system about the Queue inside µµµµµµµµp p
at any given timeat any given time
�� In IBM PC these pins are connected to 808In IBM PC these pins are connected to 80877 to synchronize to synchronize
it with 808it with 80888
�� The following table describe their functionThe following table describe their function
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� In Max Mode:In Max Mode:
�� (26, 27 and 28)(26, 27 and 28) SoSo , , S1S1 andand S2S2 Status signalStatus signal
�� Connected to 8288 which will use them to produce all Connected to 8288 which will use them to produce all
control signal such as those shown in tablecontrol signal such as those shown in table
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� In Max Mode:In Max Mode:
�� (29 ) (29 ) LOCKLOCK PinPin
�� Active low Active low o/po/p signalsignal
�� Used to prevent other processor or devices from gaining Used to prevent other processor or devices from gaining
control on the busescontrol on the buses
�� Activated by LOCK prefix in the instruction of the Activated by LOCK prefix in the instruction of the
assembly programassembly program
�� (30 , 31 ) (30 , 31 ) RQRQ / / GT0GT0 and and RQRQ / / GT1GT1 request Grantrequest Grant
�� Bidirectional LinesBidirectional Lines
�� Allow other processors to gain control on the busAllow other processors to gain control on the bus
�� In IBM PC, RQ / GT0 is connected to high making it In IBM PC, RQ / GT0 is connected to high making it
disabled and RQ / GT1 Is connected to 8087disabled and RQ / GT1 Is connected to 8087
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� CLOCK GENERATOR (8284A)CLOCK GENERATOR (8284A)::
�� AnAn 1818--pin chip. Not only provide the clock and pin chip. Not only provide the clock and
synchronization for the microprocessor, but also provides the synchronization for the microprocessor, but also provides the
READY signal for the insertion of WAIT states into the CPU READY signal for the insertion of WAIT states into the CPU
bus cycle.bus cycle.
�� Input PinsInput Pins
�� RESRES (Reset In): from power supplier(Reset In): from power supplier
�� X1X1 and and X2X2 (Crystal In): the crystal frequency must be 3 (Crystal In): the crystal frequency must be 3
times the desired frequency for the microprocessortimes the desired frequency for the microprocessor..
��For IBM PC, 14.31818 MHz (max 24 MHz)For IBM PC, 14.31818 MHz (max 24 MHz)
�� RDY1RDY1 and and AEN1AEN1: provide a Ready signal to the : provide a Ready signal to the µµµµµµµµP, which P, which
will insert a will insert a WAITWAIT state to the CPU read/write cycle. state to the CPU read/write cycle.
�� RDY2RDY2 and and AEN2AEN2: For multiprocessor systems: For multiprocessor systems..
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� CLOCK GENERATOR (8284A)CLOCK GENERATOR (8284A)::
�� Output SignalsOutput Signals
�� RESETRESET: reset signal to the 8086/88: reset signal to the 8086/88
�� OSCOSC (oscillator): provide to the expansion slot(oscillator): provide to the expansion slot. .
�� CLKCLK (clock): 1/3 of the OSC or EFI input, with a duty (clock): 1/3 of the OSC or EFI input, with a duty
cycle of 33%cycle of 33%..
��In IBM PC, OSC = 14.31818 MHz, so CLK = In IBM PC, OSC = 14.31818 MHz, so CLK =
4.772776 MHz4.772776 MHz
�� PCLKPCLK: one: one--half of CLK (1/6 of crystal) with duty cycle half of CLK (1/6 of crystal) with duty cycle
of 50% and is TTL compatible. Provide to 8253 Timer to of 50% and is TTL compatible. Provide to 8253 Timer to
generate speaker tonesgenerate speaker tones
�� READYREADY: connect to READY input of CPU to insert : connect to READY input of CPU to insert
WAIT stateWAIT state
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��CLOCK GENERATOR (8284A)CLOCK GENERATOR (8284A)::
��The The 82848284 chips serves three purposes:chips serves three purposes:
��Generates the main clock (Generates the main clock (CLKCLK) for the ) for the
processor (fc/3 with 33% duty cycle) and the processor (fc/3 with 33% duty cycle) and the
clock for the peripheral devices (fc/5).clock for the peripheral devices (fc/5).
��Provides the Provides the ResetReset pulse according to the state of pulse according to the state of
the RC circuit connected at the the RC circuit connected at the RESRES input.input.
��Provides the Provides the ReadyReady signal to insert wait states signal to insert wait states
whenever the processor is accessing slow whenever the processor is accessing slow
memory or peripheral memory or peripheral I/OI/O ports. ports.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��CLOCK GENERATOR (8284A)CLOCK GENERATOR (8284A)::
��This section describes the This section describes the 8484A8484A clock generator clock generator
and theand the RESETRESET signalsignal.
��also introduces the also introduces the READYREADY signal for 8086/8088signal for 8086/8088
��With no clock generator, many circuits would be With no clock generator, many circuits would be
required to generate the clock (required to generate the clock (CLKCLK).).
��8284A8284A provides the following basic functions:provides the following basic functions:
��clock generation; clock generation; RESETRESET & & READYREADY synchsynch
��TTLTTL--levellevel peripheral clock signalperipheral clock signal
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
CSYNCCSYNC ((cclock lock
syncsynchronization)hronization)
�� This This activeactive--highhigh signal signal
�� It is used to allow several It is used to allow several
8284 chips to be connected 8284 chips to be connected
together and synchronized.together and synchronized.
�� The IBM PC only uses one The IBM PC only uses one
8284; therefore, this pin is 8284; therefore, this pin is
connected to connected to lowlow..
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
PCLKPCLK ((pperipheral eripheral clclocockk))
�� This frequency is oneThis frequency is one--half half
of of CLKCLK (or o(or onene--sixthsixth of the of the
crystal) with a duty cycle of crystal) with a duty cycle of
50% and is TTL 50% and is TTL
compatible.compatible.
�� In the IBM PC this In the IBM PC this
2.386383 MHz2.386383 MHz is provided is provided
to the to the 82538253 timer to be used timer to be used
to generate speaker tones, to generate speaker tones,
and other functionsand other functions.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
RDY1RDY1 and and AEN1AEN1
�� RDY1RDY1 is active high and is active high and AEN1AEN1
(address enable) is active low. (address enable) is active low.
�� They are used together to provide a They are used together to provide a
ready signal to the microprocessor, ready signal to the microprocessor,
�� which will insert a which will insert a WAITWAIT state to the state to the
CPU read/write cycle. CPU read/write cycle.
�� In the IBM PC, RDY1 is connected In the IBM PC, RDY1 is connected
to to DMAWAITDMAWAIT and and AEN1AEN1 is is
connected to connected to RDY/WAITRDY/WAIT. .
�� They allow the wait state to be They allow the wait state to be
inserted either by the CPU or by inserted either by the CPU or by
DMA.DMA.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
READYREADY
�� This signal is connected to This signal is connected to
READYREADY of the CPU. of the CPU.
�� In the IBM PC it is used to In the IBM PC it is used to
signal the signal the 80888088 to indicate to indicate
if the CPU needs to insert if the CPU needs to insert
a wait state due to the a wait state due to the
slowness of the devices slowness of the devices
that the CPU is trying to that the CPU is trying to
contact.contact.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
RDY2RDY2 and and AEN2AEN2
�� These function exactly like These function exactly like RDY1RDY1 and and AEN1AEN1. .
�� These extra These extra RDYRDY and and AENAEN signals are signals are provided to allow for a provided to allow for a multiprocessing system. multiprocessing system.
�� It allows other generalIt allows other general--purpose CPUs purpose CPUs such as the such as the 8088/80868088/8086 to gain control to gain control over the buses. over the buses.
�� In the IBM PC, In the IBM PC, RDY2RDY2 is connected to is connected to lowlow, , AEN2AEN2 is connected to is connected to highhigh, which , which permanently disables this function permanently disables this function since there is only one since there is only one 8088/80868088/8086microprocessor in the system. microprocessor in the system.
�� In cases of multiprocessor systems, In cases of multiprocessor systems, these signals are used to coordinate these signals are used to coordinate access over the buses by different access over the buses by different CPUs CPUs
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
CLK (clock)CLK (clock)
�� This is an output clock frequency This is an output clock frequency equal to equal to oneone--third third of the of the crystal crystal oscillatoroscillator, or , or EFIEFI input frequency, input frequency,
�� with a duty cycle of with a duty cycle of 33%.33%. This is This is connected to the clock input of the connected to the clock input of the 8088/868088/86 and all other devices that and all other devices that must be synchronized with the CPU. must be synchronized with the CPU.
�� In the IBM PC it is connected to pin In the IBM PC it is connected to pin 1919 of the of the 80888088 microprocessor and microprocessor and other circuitry under the CLK88 other circuitry under the CLK88 label.label.
�� This frequency, This frequency, 4.772776 MHz4.772776 MHz((14.31818 divided by 314.31818 divided by 3), is the ), is the processor frequency on which all of processor frequency on which all of the timing calculations of the the timing calculations of the memory and I/Omemory and I/O cycle are based.cycle are based.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
RESETRESET
�� This is an activeThis is an active--high signal high signal
that provides a that provides a RESETRESET signal signal
to the to the 8088/868088/86 microprocessor. microprocessor.
�� It is activated by the It is activated by the RESRES
input signal discussed earlier.input signal discussed earlier.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
RES (reset in)RES (reset in)
�� This is an input activeThis is an input active--low signal to low signal to
generate generate RESETRESET. .
�� In the IBM PC, it is connected to the In the IBM PC, it is connected to the
powerpower--good signal from the power good signal from the power
supply. supply.
�� When the power switch in the IBM PC is When the power switch in the IBM PC is
turned on, assuming that the power turned on, assuming that the power
supply is good,supply is good,
�� a low signal is provided to this pin a low signal is provided to this pin
�� and the and the 82848284 in turn will activate the in turn will activate the
RESETRESET pin,pin,
�� forcing the forcing the 8088/868088/86 to reset; then the to reset; then the
microprocessor takes over. This is called microprocessor takes over. This is called
a cold boota cold boot.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
OSC (oscillator)OSC (oscillator)
�� This provides a clock This provides a clock
frequency equal to the crystal frequency equal to the crystal
oscillator and it is TTL oscillator and it is TTL
compatible. compatible.
�� Since the IBM crystal Since the IBM crystal
oscillator is oscillator is 14.31818 MHz14.31818 MHz, ,
OSCOSC will provide this will provide this
frequency to the expansion frequency to the expansion
slot of the IBM PC.slot of the IBM PC.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
F/C (frequency/clock select)F/C (frequency/clock select)
�� This pin provides an option This pin provides an option for the way the clock is for the way the clock is generated. generated.
�� If connected to low, the clock If connected to low, the clock is generated by the is generated by the 82848284 with with the help of a crystal oscillator. the help of a crystal oscillator.
�� If it is connected to high, it If it is connected to high, it expects to receive clocks at the expects to receive clocks at the EFIEFI pin. pin.
�� Since the IBM PC uses a Since the IBM PC uses a crystal, this pin is connected to crystal, this pin is connected to low. low.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
EFI (EFI (external frequency inexternal frequency in))
�� External frequency is External frequency is
connected to this pin if connected to this pin if F/CF/C
has been connected to high. has been connected to high.
�� In the IBM PC this is not In the IBM PC this is not
connected since a crystal is connected since a crystal is
used instead of an external used instead of an external
frequency generator. frequency generator.
�� In some cases (such as the In some cases (such as the
Turbo PC), this pin is used to Turbo PC), this pin is used to
provide clock frequency in provide clock frequency in
place of place of XIXI and and X2X2..
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
ASYNCASYNC
�� This is called ready This is called ready
synchronization select. synchronization select.
�� An active low is used for An active low is used for
devices that are not able to devices that are not able to
adhere to the very strict adhere to the very strict RDYRDY
setup time requirement. setup time requirement.
�� In the IBM PC this is In the IBM PC this is
connected to low, making the connected to low, making the
timing design of the system timing design of the system
easier with slower logic gates.easier with slower logic gates.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
��The pinThe pin--out of the out of the 8284A8284A clock generatorclock generator
X1 and X2 (crystal in)X1 and X2 (crystal in)
�� XIXI and and X2X2 are the pins to which are the pins to which a crystal is attached.a crystal is attached.
�� The crystal frequency must be The crystal frequency must be 3 times the desired frequency 3 times the desired frequency
for the microprocessor. for the microprocessor.
�� The maximum crystal for the The maximum crystal for the 8284A is 24 MHz and 30 MHz 8284A is 24 MHz and 30 MHz for the 8284Afor the 8284A--1. 1.
�� The IBM PC is connected to a The IBM PC is connected to a crystal of 14.31818 MHz. For crystal of 14.31818 MHz. For some turbo compatibles, it is 24 some turbo compatibles, it is 24 MHz.MHz.
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� The internal block diagram of the The internal block diagram of the 8284A8284A clock generatorclock generator
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� Operation of the Clock SectionOperation of the Clock Section of the of the 8284A8284A clock clock
generatorgenerator
�� Crystal oscillator has two inputs: XCrystal oscillator has two inputs: X11 and Xand X22..
�� if a crystal is attached to Xif a crystal is attached to X11 and Xand X
22, the oscillator , the oscillator
generates a squaregenerates a square--wave signal at the same wave signal at the same
frequency as the crystalfrequency as the crystal
�� The squareThe square--wave is fed to an AND gate & an inverting wave is fed to an AND gate & an inverting
buffer to provide an buffer to provide an OSCOSC output.output.
�� The The OSCOSC signal is sometimes used as an signal is sometimes used as an EFIEFI input to other input to other
8284A8284A circuits in a system.circuits in a system.
�� The following Figure shows how an The following Figure shows how an 8284A8284A is connected to is connected to
the the 8086/80888086/8088. .
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� The clock generator (The clock generator (8284A8284A) and the 8086 and 8088 microprocessors illustrating the ) and the 8086 and 8088 microprocessors illustrating the
connection for the clock and reset signals. A 15 MHz crystal proconnection for the clock and reset signals. A 15 MHz crystal provides the 5 MHz clock vides the 5 MHz clock
for the microprocessorfor the microprocessor
Prof. Fayez F. M. El-Sousy
Hardware SpecificationsHardware Specifications
Microprocessor 8086/8088Microprocessor 8086/8088
�� Operation of the Operation of the ResetReset SectionSection of the of the 8284A8284A clock clock
generatorgenerator
�� The reset section of The reset section of 8284A8284A consists of a consists of a Schmitt trigger Schmitt trigger
bufferbuffer and a and a DD--type fliptype flip--flopflop..
�� the Dthe D--type fliptype flip--flop ensures timing requirementsflop ensures timing requirements
of 8086/8088 RESET input are metof 8086/8088 RESET input are met
�� This circuit applies the This circuit applies the RESETRESET signal on the signal on the negative edgenegative edge
((11--toto--0 transition0 transition) of each clock.) of each clock.
�� 80880866/808/80888 microprocessors sample microprocessors sample RESETRESET at the at the positive positive
edgeedge ((00--toto--1 transition1 transition) clocks.) clocks.
�� thus, this circuit meets 808thus, this circuit meets 80866/808/80888 timing timing
requirementsrequirements
Prof. Fayez F. M. El-Sousy
Memory InterfaceMemory Interface
Microprocessor 8086/8088Microprocessor 8086/8088
�� Two basic types:Two basic types:
�� ROM: ReadROM: Read--only memoryonly memory
�� RAM: ReadRAM: Read--Write memoryWrite memory
�� Four commonly used memories:Four commonly used memories:
�� ROMROM
�� Flash (EEPROM)Flash (EEPROM)
�� Static RAM (SRAM)Static RAM (SRAM)
�� Dynamic RAM (DRAM)Dynamic RAM (DRAM)
Prof. Fayez F. M. El-Sousy
Memory InterfaceMemory Interface
Microprocessor 8086/8088Microprocessor 8086/8088
��The data pins are typically biThe data pins are typically bi--directional in readdirectional in read--write memories. write memories.
�� The number of data pins is related to the size The number of data pins is related to the size of the memory location. For example, an 8of the memory location. For example, an 8--bit bit wide (bytewide (byte--wide) memory device has 8 data wide) memory device has 8 data pins. pins.
��Each memory device has at least one chip select Each memory device has at least one chip select (CS) or chip enable (CE) or select (S) pin that (CS) or chip enable (CE) or select (S) pin that enables the memory device. enables the memory device.
�� This enables read and/or write operations. This enables read and/or write operations.
�� If more than one are present, then all must be If more than one are present, then all must be 0 in order to perform a read or write. 0 in order to perform a read or write.
Prof. Fayez F. M. El-Sousy
Memory InterfaceMemory Interface
Microprocessor 8086/8088Microprocessor 8086/8088
��SRAMsSRAMs
�� SRAMsSRAMs used for caches have access times as used for caches have access times as low as 10ns.low as 10ns.
��DRAMsDRAMs
�� SRAMsSRAMs are limited in size (up to about are limited in size (up to about 128Kb). 128Kb).
�� DRAMsDRAMs are available in much larger sizes, are available in much larger sizes, e.g., 64M X 1. e.g., 64M X 1.
�� DRAMsDRAMs MUST be refreshed every 2 to 4 ms.MUST be refreshed every 2 to 4 ms.
�� Since they store their value on an integrated Since they store their value on an integrated capacitor that loses charge over time. capacitor that loses charge over time.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��Address DecodingAddress Decoding
�� In orderIn order to attach a memory deviceto attach a memory device to the to the
microprocessor,microprocessor, it is necessary to decode the it is necessary to decode the
address sent from the microprocessor.address sent from the microprocessor.
��Decoding makes theDecoding makes the memory function at a unique memory function at a unique
section or partition of the memory map.section or partition of the memory map.
��Without an address decoder, only one memory Without an address decoder, only one memory
device can be connected to a microprocessor, which device can be connected to a microprocessor, which
would make it virtually useless. would make it virtually useless.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��Address DecodingAddress Decoding
�� The processor can usually address a memory space that is The processor can usually address a memory space that is
much larger than the memory space covered by an much larger than the memory space covered by an
individual memory chip. individual memory chip.
�� In order to splice a memory device into the address space of In order to splice a memory device into the address space of
the processor, decoding is necessary. the processor, decoding is necessary.
�� For example, the For example, the 8088 issues 208088 issues 20--bitbit addresses for a total of addresses for a total of
1MB1MB of memory address space.of memory address space.
�� The The BIOSBIOS on a on a 2716 EPROM2716 EPROM has only has only 2KB2KB of memory and of memory and
11 address pins.11 address pins.
�� A decoder can be used to decode the A decoder can be used to decode the additional 9 address additional 9 address
pinspins and allow the and allow the EPROMEPROM to be placed in any to be placed in any 2KB2KB section section
of the of the 1MB1MB address space. address space.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��Address DecodingAddress Decoding-- Why Decode Memory? Why Decode Memory?
��TheThe 8088 has 208088 has 20 address connections and address connections and the the 27162716
EPROM has 11EPROM has 11 connections.connections.
��The The 80888088 sends out a sends out a 2020--bit memory addressbit memory address
whenever it reads or writes data. whenever it reads or writes data.
�� because the 2716 has only 11 address pins,because the 2716 has only 11 address pins,
there is a mismatch that must be correctedthere is a mismatch that must be corrected
��The decoder corrects the mismatch by decoding The decoder corrects the mismatch by decoding
address pins that do not connect to the memory address pins that do not connect to the memory
component. component.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��Simple NAND Gate Decoder Simple NAND Gate Decoder
��When the When the 2K 2K ×××××××× 8 EPROM8 EPROM is used, address is used, address
connections connections AA1010––AA00 of 8088of 8088 are connected to are connected to
address inputs address inputs AA1010––AA00 of the EPROMof the EPROM. .
�� the remaining nine address pins (Athe remaining nine address pins (A1919––AA1111))
are connected to a NAND gate decoderare connected to a NAND gate decoder
��The decoder selects the The decoder selects the EPROMEPROM from one of the from one of the
2K2K--byte sections of the byte sections of the 1M1M--byte memorybyte memory system in system in
the the 80888088 microprocessor.microprocessor.
�� In this circuit a In this circuit a NANDNAND gate decodes the memory gate decodes the memory
address, as seen in the following Figure.address, as seen in the following Figure.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��A simple NAND gate decoder that selects a 2716 A simple NAND gate decoder that selects a 2716
EPROM for memory location FF800HEPROM for memory location FF800H––FFFFFH FFFFFH
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��Simple NAND Gate Decoder for memory location Simple NAND Gate Decoder for memory location
FF800HFF800H––FFFFFH FFFFFH
��To determine the address range that a device is To determine the address range that a device is
mapped into:mapped into:
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
1111 1111 11111111 1000 0000 1000 0000 00000000 = F0000H= F0000H
1111 1111 11111111 11111111 11111111 11111111 = F1FFFH= F1FFFH
A11A11A19A19 A10A10 A0A0
Memory Locations:
FF800H-FFFFFH
Common part makes the
9 selector bits
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
�� Simple NAND Gate Decoder Simple NAND Gate Decoder
�� If the If the 2020--bit binary addressbit binary address, decoded by the , decoded by the NANDNAND
gate, is written so that the gate, is written so that the leftmost 9 bitsleftmost 9 bits are are 1s1s and and
the the rightmost 11 bitsrightmost 11 bits are are dondon’’t cares (X),t cares (X), the actual the actual
address range of the address range of the EPROMEPROM can be determined. can be determined.
�� a a dondon’’t caret care is a logic 1 or a logic 0, whicheveris a logic 1 or a logic 0, whichever
is appropriateis appropriate
��Because of the excessive cost of the Because of the excessive cost of the NANDNAND gate gate
decoderdecoder and inverters often required, this option and inverters often required, this option
requires an alternate be found.requires an alternate be found.
��NANDNAND gate decoders are not often used. Rather the gate decoders are not often used. Rather the 33--
toto--8 Line Decoder8 Line Decoder (74LS138) is more common.(74LS138) is more common.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��The 3The 3--toto--8 Line Decoder (74LS138)8 Line Decoder (74LS138)
��The 74LS138 The 74LS138 33--toto--8 line decoder8 line decoder and function table.and function table.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
A circuit that uses eight 2764 A circuit that uses eight 2764 EPROMsEPROMs for a 64K for a 64K ×××××××× 8 section of memory in an 8088 8 section of memory in an 8088
microprocessormicroprocessor--based system. The addresses selected in this circuit are F0000Hbased system. The addresses selected in this circuit are F0000H––FFFFFH.FFFFFH.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
A circuit that uses eight 2764 A circuit that uses eight 2764 EPROMsEPROMs for a 64K for a 64K ×××××××× 8 section of memory in an 8088 8 section of memory in an 8088
microprocessormicroprocessor--based system. The addresses selected in this circuit are F0000Hbased system. The addresses selected in this circuit are F0000H––FFFFFH.FFFFFH.
Module 0Module 0
1111 000X XXXX 1111 000X XXXX XXXXXXXX XXXXXXXX
1111 0000 1111 0000 00000000 00000000 00000000 = F0000H= F0000H
toto
1111 0001 1111 1111 0001 1111 11111111 11111111 = F1FFFH= F1FFFH
Module 7Module 7
1111 111X XXXX 1111 111X XXXX XXXXXXXX XXXXXXXX
1111 1110 0000 1111 1110 0000 00000000 00000000 = FE000H= FE000H
toto
1111 1111 11111111 1111 1111 11111111 11111111 = FFFFFH= FFFFFH
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
�� In this circuit, a In this circuit, a threethree--inputinput NANDNAND gate is connected to gate is connected to
address bits address bits AA1919––AA1717. .
�� When all three address inputs are high, the output of this When all three address inputs are high, the output of this
NANDNAND gate goes low and enables input gate goes low and enables input G2BG2B of the of the 74LS13874LS138. .
�� Input Input G1G1 is connected directly to is connected directly to AA1616. .
�� In order to enable this decoder, the first four address In order to enable this decoder, the first four address
connections (connections (AA1919––AA1616) must all be ) must all be highhigh..
�� Address inputs C, B, and A connect to microprocessor address Address inputs C, B, and A connect to microprocessor address
pins pins AA1515––AA1313. .
�� These These three address inputsthree address inputs determine which output pin goes determine which output pin goes
low and which low and which EPROMEPROM is selected whenever is selected whenever 80888088 outputs a outputs a
memory address within this range to the memory system.memory address within this range to the memory system.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��The 3The 3--toto--8 Line Decoder (74LS138)8 Line Decoder (74LS138)
��Example:Example:
A19A19………………………………………………………………. A0 . A0
1111 1111 XXXX XXXX XXXXXXXX XXXXXXXX XXXXXXXX
oror
1111 0000 1111 0000 00000000 00000000 00000000 = F0000H= F0000H
toto
1111 1111 11111111 11111111 11111111 11111111 = FFFFFH= FFFFFH
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��The 3The 3--toto--8 Line Decoder (74LS138)8 Line Decoder (74LS138)
��Example:Example:
CBACBA
1111 1111 000X XXXX 000X XXXX XXXXXXXX XXXXXXXX
oror
1111 0000 1111 0000 00000000 00000000 00000000 = F0000H= F0000H
toto
1111 0001 1111 1111 0001 1111 11111111 11111111 = F1FFFH= F1FFFH
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��The 3The 3--toto--8 Line Decoder (74LS138)8 Line Decoder (74LS138)
��Example:Example:
CBACBA
1111 1111 001X XXXX 001X XXXX XXXXXXXX XXXXXXXX
oror
1111 0010 0000 1111 0010 0000 00000000 00000000 = F2000H= F2000H
toto
1111 0011 1111 1111 0011 1111 11111111 11111111 = F3FFFH= F3FFFH
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��The The 22--toto--4 Binary Decoders4 Binary Decoders
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��The The 22--toto--4 Binary Decoders4 Binary Decoders
�� The binary inputs The binary inputs AA and and BB determine which output line determine which output line
from from D0D0 to to D3D3 is "is "HIGHHIGH" at logic level " at logic level "1""1" while the while the
remaining outputs are held "remaining outputs are held "LOWLOW" at logic " at logic "0""0" so only so only
one output can be active (one output can be active (HIGHHIGH) at any one time.) at any one time.
�� Therefore, whichever output line is "Therefore, whichever output line is "HIGHHIGH" identifies the " identifies the
binary code present at the input, in other words it binary code present at the input, in other words it "de"de--
codes"codes" the binary input and these types of binary decoders the binary input and these types of binary decoders
are commonly used as Address Decoders in are commonly used as Address Decoders in
microprocessor memory applications.microprocessor memory applications.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– Address DecodingAddress Decoding
Microprocessor 8086/8088Microprocessor 8086/8088
��The Dual The Dual 22--toto--4 Line Decoder (74LS139)4 Line Decoder (74LS139)
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– I/O InterfaceI/O Interface
Microprocessor 8086/8088Microprocessor 8086/8088
�� Programmable Peripheral Interface (PPI) 8255Programmable Peripheral Interface (PPI) 8255
��The The 82C5582C55 is a popular interfacing component, that is a popular interfacing component, that can interface any TTLcan interface any TTL--compatible compatible I/OI/O device to the device to the microprocessor. microprocessor.
�� It is used to interface to the keyboard and a parallel It is used to interface to the keyboard and a parallel printer port in PCs (usually as part of an integrated printer port in PCs (usually as part of an integrated chipset). chipset).
��Requires insertion of wait states if used with a Requires insertion of wait states if used with a microprocessor using higher that an microprocessor using higher that an 8 MHz8 MHz clock. clock.
�� PPI has PPI has 24 pins24 pins for for I/OI/O that are programmable in that are programmable in groups of 12 pins and has three distinct modes of groups of 12 pins and has three distinct modes of operation. operation.
�� In the In the PCPC, an , an 82C5582C55 or its equivalent is decoded at or its equivalent is decoded at I/O I/O ports 60Hports 60H--63H.63H.
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– I/O InterfaceI/O Interface
Microprocessor 8086/8088Microprocessor 8086/8088
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– I/O InterfaceI/O Interface
Microprocessor 8086/8088Microprocessor 8086/8088
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– I/O InterfaceI/O Interface
Microprocessor 8086/8088Microprocessor 8086/8088
��Programmable Peripheral Interface (PPI) 8255Programmable Peripheral Interface (PPI) 8255
��The The 82558255 Programmable Peripheral Interface (Programmable Peripheral Interface (PPIPPI) ) is a 40is a 40--pin DIP IC that provides 3 programmable pin DIP IC that provides 3 programmable I/OI/O ports, ports, A, B, and CA, B, and C..
��How are is it programmable?How are is it programmable?
�� Configure each port as input or outputConfigure each port as input or output
�� Different modes of operationDifferent modes of operation
��You must initialize the You must initialize the PPIPPI via software commandsvia software commands
�� Send a control byte to the deviceSend a control byte to the device’’s control s control
register portregister port
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– I/O InterfaceI/O Interface
Microprocessor 8086/8088Microprocessor 8086/8088
�� Programmable Peripheral Interface (PPI) 8255Programmable Peripheral Interface (PPI) 8255
�� PA0 PA0 –– PA7: Port A / All / input/output/bidirectionalPA7: Port A / All / input/output/bidirectional
�� PB0 PB0 –– PB7: Port B / All / input/outputPB7: Port B / All / input/output
�� PC0 PC0 –– PC7: Port C / All / input/outputPC7: Port C / All / input/output
�� Can be split into two parts:Can be split into two parts:
�� Upper (PC7 Upper (PC7 –– PC4) and Lower (PC3 PC4) and Lower (PC3 –– PC0).PC0).
�� Each can be used for input or output.Each can be used for input or output.
�� Any of PC0 Any of PC0 –– PC7 can be programmed.PC7 can be programmed.
�� RD and WR: control signal input to 8255RD and WR: control signal input to 8255
�� IOR and IOW in peripheral I/OIOR and IOW in peripheral I/O
�� MEMR and MEMW in memoryMEMR and MEMW in memory--mapped I/Omapped I/O
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– I/O InterfaceI/O Interface
Microprocessor 8086/8088Microprocessor 8086/8088
�� Programmable Peripheral Interface (PPI) 8255Programmable Peripheral Interface (PPI) 8255
�� RESET: Active high input signal to 8255RESET: Active high input signal to 8255
�� Used to clear the internal control registerUsed to clear the internal control register
�� When activated, all ports are initialized as input ports.When activated, all ports are initialized as input ports.
�� Usually connect to the RESET output of the system bus or Usually connect to the RESET output of the system bus or groundground
�� A0, A1, and CSA0, A1, and CS
�� CS selects the entire chip, A0 and A1 select the specified portCS selects the entire chip, A0 and A1 select the specified port
�� Used to access port A, B, C,Used to access port A, B, C, CS A1 A0 Select
or control registeror control register 0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Reg.
1 x x Not Selected
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– I/O InterfaceI/O Interface
Microprocessor 8086/8088Microprocessor 8086/8088
�� Programmable Peripheral Interface (PPI) 8255Programmable Peripheral Interface (PPI) 8255
�� Control WordControl Word
Port C Lower PC3-PC0
1 = input, 0 = output
Port B
1 = input, 0 = output
Mode Selection
0 = Mode0, 1 = Mode1
Port C Upper PC7-PC4
1 = input, 0 = output
Port A
1 = input, 0 = output
Mode Selection
00 = Mode0, 01 = Mode1
1x = Mode 2
1 = I / O Mode
0 = BSR Mode
Group BGroup B
Group AGroup A
D7 D6 D3 D2 D1 D0D5 D4
Prof. Fayez F. M. El-Sousy
Memory Interface Memory Interface –– I/O InterfaceI/O Interface
Microprocessor 8086/8088Microprocessor 8086/8088
�� PPI 8255 Mode SelectionPPI 8255 Mode Selection
�� Mode 0: simple I/OMode 0: simple I/O
�� Any ports: A, B, CL, CU. No control of individual bitsAny ports: A, B, CL, CU. No control of individual bits
�� Mode 1: I/O (ports A and B) with handshaking (port C)Mode 1: I/O (ports A and B) with handshaking (port C)
�� Synchronizes communication between an intelligent Synchronizes communication between an intelligent
device (printer)device (printer)
�� Mode 2: BiMode 2: Bi--directional I/O with handshakingdirectional I/O with handshaking
�� Port A: bidirectional I/O with handshaking through Port A: bidirectional I/O with handshaking through
port Cport C
�� Port B: Simple I/O or in handshake mode 1Port B: Simple I/O or in handshake mode 1
�� BSR Mode: Bit set/reset BSR Mode: Bit set/reset
�� Only the individual bits on Port C can be programmed Only the individual bits on Port C can be programmed
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