High-speed communication with FPD-Link - TI Training · 2020. 5. 21. · Clock jitter is a critical...

High-speed communication with FPD-Link TI Precision Labs - FPD-Link

Prepared by Vijaya Ceekala

Presented by Casey McCrea

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FPD-Link enables high-speed video transport

Camera ECU Head Unit

Central Information

Display

Rear Seat Entertainment Control Unit

DVD

LCD LCD

Instrument Cluster Display

Instrument Cluster ECU

Head-Up Controller

Head-Up Display

Front View Cameras

Display Interfaces Camera Interfaces

An example of high-speed serial FPD-Link

• Serialization reduces pin counts and connector requirements

• Adaptive Equalization and CDR techniques compensate for signal impairments

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De-serializer

Serializer

PLL

PCLK

P->S

Ref. clk

S->P

BC Rx

Par. data

BC Tx

CDR A-EQ

Display

Panel

/

Video

Processor

Par. data

PCLK

Processor

/

Imager/ISP

Clk_in

Vcc Vcc

Tx Rx

PLL in FPD-Link • PLL stands for Phase Locked Loop

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PFD Charge

Pump VCO

1/N

up

down

Reference

clock Output

clock Loop

Filter

Feedback

clock

Clock and Data Recovery circuit

D Q

Phase

Detector

Loop Filter

Voltage

Controller

Oscillator

PLL

Recovered/

Retimed Data

Incoming

Data

Sampler

Recovered

Clock

Control

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Eye diagram to study FPD-Link end-to-end jitter

• The size of the eye opening determines the quality of the signal

1 UI

Jitter limits performance

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Scope Results

Clock jitter is a critical requirement in High Speed Serial Link

Bathtub Curve Performance

Random jitter reduces the eye opening

10-12

10-15

BER

0 1.0 0.5 0.2 0.8

Minimize Random Jitter (RJ)

via clean clocks

Minimize Deterministic Jitter (DJ) via

Equalization

1UI = 1/ Data Rate

DJ DJ

RJ RJ ISI, DDJ, VCC

Noise

ISI, DDJ, VCC

Noise

Eye closing due to jitter

Eye Open

FPD-Link system jitter components

• 3 main system components: transmitter, channel & receiver jitter

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De-serializer

Serializer

PLL

PCLK

P->S

Ref. clk

S->P

BC Rx

Par. data

BC Tx

CDR A-EQ

Display

Panel

/

Video

Processor

Par. data

PCLK

Processor

/

Imager/ISP

Clk_in

Vdd Vdd

Channel:

PCB+Connector+cable

Transmitter Jitter Channel Jitter Receiver Jitter

Channel jitter due to PCB traces and cable

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• Signal conditioning – coping with the loss

• Equalizing the channel – compensating for insertion loss in a channel

RG-174 Cable Attenuation Measurements (S21)

-24

-18

-12

-6

0

1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10S

21

(d

B)

Frequency (Hz)

1m55m10m10+5m15m1m5+1m51m5+5+1m5

700 M 1.4G -1.35684 -1.96093 -3.29194 -4.78308 -6.52766 -9.46343-9.75449 -14.1672 -9.70192 -14.077 -2.64264 -3.96488 -5.93373 -8.77949

Channel Equalization

EQTX CDR

Channel

Data

Input

Re-

timed

Data

High-speed FPD-Link

serializer output After the channel Equalized output

Inverted channel characteristics

EQ characteristics

Quiz

1. What kind of jitter is introduced due to signal attenuation inside a cable?

a) Random Jitter

b) Deterministic jitter

c) Periodic jitter

2. What kind of method is used to compensate for random jitter introduced due to power supply

noise?

a) Adaptive Equalizer (AEQ)

b) Random jitter introduced due to power supply cannot be reduced

c) Some of the random jitter effects due to power supply noise can reduced by filtering the

data stream

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Thank you

To find more FPD-Link technical resources and search products, visit

ti.com/interface/fpd-link-serdes/products.html

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