[IEEE 2010 IEEE International Microwave Workshop Series on "RF Front-ends for Software Defined...

Architecture for Dynamic Range Extension of Analogue-to-Digital Conversion

Pedro Cruz#1, Nuno Borges Carvalho#2 #Instituto de Telecomunicações, Universidade de Aveiro

Campus Universitário de Santiago, Aveiro, Portugal 1pcruz@av.it.pt

2nbcarvalho@ua.pt

Abstract— This paper presents a new technique to extend the

dynamic range of the signal conversion from the analogue domain to the digital domain. It is based in a new technique to split the incoming analogue signal into two portions and then convert it to the digital domain using for that two parallel analogue-to-digital converters, ADC, and afterwards reconstruct the signal in the digital domain.

The proposed architecture will be explained giving more emphasis on the analogue signal splitter. Then, this architecture will be validated through several simulations.

We will demonstrate an improvement of around 6 dB in the dynamic range for different signal excitations, in which are included one-tone, two-tones and multisine signals.

I. INTRODUCTION

The holy grail of future RF architectures is that they will be able to receive any type of signal despite its bandwidth and dynamic range. Even though it is considered a holy grail, the path is moving towards multi-norm, multi-standard radios that are supported in Software Defined Radios (SDR), and thus on that are capable of receiving a huge range of bandwidth combined with very different power levels, and this means high dynamic range approaches. As was proposed by Mitola in [1] the receiving unit of an SDR the radio should have a very wide bandwidth analogue-to-digital converter (ADC) to gather and convert all the signals from analogue to digital, and this ADC should have a strong dynamic range associated, since it should receive low power signals combined with high power ones, and considering that if the radio has to receive several different signals, they should not combine each other. Other important field of researching is in the test and measurement area [2], in which we are led to find solutions that allow a correct characterization of such demanding radio architectures. The existent digital modulations conjugated with orthogonal frequency division multiplexing (OFDM), which SDR must be aware, can have very high peak-to-average power ratios (PAPR). A helpful solution could be the use of peak reduction techniques but it may adversely affect the bit error rate. Also, the emergence of RF mixed signal circuits as the SDR and the next step up Cognitive Radio (CR) approaches [3] open the attractive situation where RF (mainly based on analogue devices) and digital components are functionally adjacent and work in cooperation.

In that sense, this paper aims to propose a new technique to increase the receiving dynamic range of the analogue-to-digital (A/D) signal conversion stage. This architecture could be more easily applied to applications in the test and measurement field where it can be more valuable and

designed in an efficient way but this detail does not prevent the use in other fields.

This paper is organized in the following way. Firstly, a detailed explanation of the proposed architecture is given, in which we will emphasize the operation of the analogue signal splitter stage. Then, in section III, the proposed architecture will be demonstrated by means of several simulations in Matlab/Simulink software package using ideal device models for the analogue signal splitter followed by a pipelined ADC model when it is subject to a CW excitation. In section IV, we will present a partial validation of the proposed technique delivering to the projected architecture several non-constant envelope signals. Finally, some conclusions will be drawn accounting for with the obtained results.

II. EXPLANATION OF THE PROPOSED ARCHITECTURE This section is devoted to explain in depth the proposed

architecture to increase the dynamic range of the A/D conversion by using an analogue signal splitter stage followed by a second stage that is composed of two ADCs in parallel.

The concept of the proposed architecture is depicted in Fig. 1. Analyzing that figure we can observe a block called analogue signal splitter that divides the input signal into two parallel waveforms depending on the reference voltage selected. Normally, this reference voltage should be chosen taking into account the limits of the first converter, ADC1, in order to not place this device into clipping and thus generate a lot of distortion. After the division these signals are applied to two parallel ADCs of same type, same number of bits and off course sampled with the same clock signal. Just to mention, we have decided to use pipeline ADCs because they achieve very high throughput with relatively high resolutions by introducing a constant latency time that is not so important for the purpose.

Fig. 1 – Proposed architecture to extend the dynamic range in the analogue-to-digital conversion.

978-1-4244-5753-3/10/$26.00 ©2010 IEEE

Given that now the signals are nothing more than digital samples, and thus they can be processed by a digital signal processor (DSP). So, we can easily correct some impairments that can occur in the components of the analogue circuitry.

Nevertheless, this circuit may contain some other limitations. For example, the analogue signal splitter should provide sufficient bandwidth to not degrade the input signal before its conversion to the digital domain. Also, the ADCs should have a consequential wide bandwidth, i.e., a high sampling rate. In that sense, the input signal should be already an intermediate frequency (IF) signal in order to produce better results. This could be performed by a down-conversion stage placed before the proposed circuitry. However, taking into account that we plan to use pipelined ADC’s which normally have a high bandwidth sample-and-hold circuit in its input, such architecture can operate as a band-pass sampling receiver [4]. It is obvious that such band-pass operation will be more dependent on the analogue signal splitter stage performance. In this work we will only consider the approach of an IF incoming signal.

Next, we will explain more concretely what is the intrinsic configuration of the analogue signal splitter proposed. In order to accomplish such device we have considered the concept shown in Fig. 2.

Fig. 2 – Proposed configuration for the analogue signal splitter.

Looking at previous figure we use a voltage limiting amplifier as, for instance, the one presented in [5] to produce the small amplitude signal, which is placed at the output. The ideal voltage limiter is characterized by the following equation:

⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

>

≥≥

>

=

INLL

HINL

HINH

OUT

VVV

VVVVin

VVV

V

,

,

, (1)

where VH and VL are the upper and lower limit voltages, respectively.

Then, this small amplitude signal is also fed into another stage that is no more than a common difference amplifier. Considering a real circuit implementation we must use in this point a power splitter to provide one signal to ADC1 (small amplitude signal) and another to one input of the difference amplifier in order to be subtracted by the input signal. Regarding that a power splitter divides the signal into two

equal parts (delivers, at least, -3 dB in each output port), the voltage limiter amplifier should account for with this and provide a voltage gain of 2 V/V. As we can see in [5] we can easily control the voltage gain of this amplifier and also manage the upper and lower limit voltages (VH and VL), which can be easily reconfigured by means of a simple resistive divider. Moreover, such amplifier may operate with dual-supply (±VCC) or single-supply (VCC, GND) voltages, which provides an increased flexibility to the described analogue signal splitter.

After that the input signal is subtracted in the difference amplifier by the obtained small amplitude signal and a large amplitude component is produced. A simple difference amplifier [6] can be constructed with four resistors and an operational amplifier. Moreover, its ideal operation can be represented by the following expression:

( ) GVVV ininOUT *−+ −= (2)

where Vin+ and Vin- are the input signals in the positive and negative inputs, respectively, and G represents the voltage gain of the amplifier that is normally given by a relation of two resistors.

Furthermore, the difference amplifier should have an indispensable wide input bandwidth in order not to degrade the signals before its conversion to the digital domain. Moreover, there are other fundamental problems with this simple circuit. For instance, the input impedance seen by the two inputs is not balanced and this configuration can also be quite problematic in terms of common-mode ratio (CMR), since even a small source impedance imbalance will degrade the workable CMR.

Finally, it was also needed a model for the pipelined ADC that is shown in Fig. 3. The constructed model in Simulink was based on the premises presented in [7]. This model accounts for with quantization phenomena and clipping behaviour. Moreover, a 10-bit ADC was considered, which from theory could ideally achieve a maximum signal-to-noise ratio (SNR) of approximately 62 dBFS.

It is important to refer that in the following sections we will present several simulation results for two different configurations, one considers only a single ADC and the other architecture is the one proposed here. Notice that the ADCs used in both architectures have the same characteristics.

Fig. 3 – General configuration of a pipelined ADC.

(a)

(b)

(c)

Fig. 4 – Obtained results for the two tested architectures with a one-tone excitation demonstrating several figures of merit: (a) Pin vs. Pout, (b) SNR and SINAD, and (c) SFDR and THD, (solid line – 1 ADC architecture) (dashed-circle/square line – Proposed architecture).

III. ARCHITECTURE VALIDATION WITH CW EXCITATION In this section we will evaluate the performance of the two

mentioned configurations when subjected to a one-tone excitation centred at 10 MHz. In order to perform some simulations, we have used an ideal voltage limiter, expression (1), an ideal difference amplifier, expression (2), and the developed pipelined ADC model that accounts for with quantization noise and full-scale range limits. In this case, the ADC has a full-scale range of 1 Vpp, i.e., admits a maximum input power of +4 dBm starting to clip after this value. The clock frequency used was equal to 90 MHz.

These simulations have taken into consideration the ADC testing standard [8] and were performed accordingly to the coherent sampling theorem. As it is well explained in the ADC testing standard we may use several figures of merit to characterize an ADC when it is being excited by a sine wave waveform, wherein are included measures like output power (Pout), signal-to-noise ratio (SNR), signal-to-noise and distortion ratio (SINAD), spurious-free dynamic range (SFDR), and total harmonic distortion (THD).

In that sense, we have determined those figures of merit for the two configurations when the input signal power is being varied from -48 dBm to +11 dBm. The obtained results are shown in Fig. 4 (a)-(c).

Looking at Fig. 4 (a) we can observe that the output signal from the proposed configuration continues to grow above +10 dBm contrarily to the single ADC configuration that starts to clip at +4 dBm, i.e., it provides an improvement of around 6 dB. Observing Figs. 4 (b) and (c) we can state that the proposed architecture preserves the performance of the single ADC architecture in the linear range and is able to clearly improve the SNR, SINAD, SFDR and THD after the clipping point of single ADC for more 6 dB.

It is worth to mention that in each graph where the input signal power is varied we depict two more vertical black lines (at +4 dBm and +10 dBm) to represent the full-scale limits of each configuration.

IV. SIMULATION RESULTS USING NON-CONSTANT ENVELOPE SIGNALS

In order to partially validate the concept demonstrated in the previous sections we have conducted several simulations with two different non-constant envelope signals (a two-tone signal and a 20-tone multisine signal with Gaussian statistics).

Firstly, we carried out simulations using a two-tone excitation with a bandwidth of 1 MHz centred at same carrier frequency of the one-tone excitation. In Fig. 5 is shown, for the two architectures, the total output power of the two fundamental tones accompanied by the power in the upper third-order intermodulation distortion (IMD) product.

As can be seen the output power rises linearly with the input power for the two configurations and reaching again a 6 dB improvement for the proposed architecture. As well, we can observe the upper 3rd-order IMD is ruled by the ADC quantization noise and starts to strongly degrade after +1 dBm (single ADC) and +7 dBm (proposed architecture), which is easily explained by the 3 dB PAPR value originated by a two-tone signal.

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After that we have used the 20-tone multisine signal with Gaussian statistics as excitation of both architectures. This multisine has a total occupied bandwidth of 1 MHz and create a signal PAPR of around 7 dB.

Fig. 6 presents the simulated results for the total power at the excitation frequencies accompanied by the total power in the upper adjacent channel (adjacent channel power, ACP) arising from intermodulation distortion.

Again the small-signal behaviour of the ACP is characterized mainly by the noise, as was seen in the two-tone case. The ACP starts to rise for values where the output signal begins to approach the respective limits of each configuration, demonstrating an improvement once again of 6 dB for the proposed architecture.

As a middle conclusion, we should refer that the presented results were obtained with ideal device models and so, when a real implementation of such architecture be constructed we should expect a reduction in the measured figures of merit at the output.

Fig. 5 – Obtained results for the two tested architectures with a two-tone excitation signal, (solid line - 1 ADC architecture) (dashed-circle/square line – Proposed architecture).

Fig. 6 – Obtained results for the two tested architectures with a Gaussian distributed multisine excitation signal, (solid line - 1 ADC architecture) (dashed-circle/square line – Proposed architecture).

CONCLUSIONS We have proposed an architecture to increase the dynamic

range of the analog-to-digital conversion based on an analogue signal splitter followed by two parallel ADCs and then reconstructing the signal by means of DSP.

Obviously, the processing requirements in the DSP for this architecture have increased when the signal peak exceeds the full-scale range (above the defined reference voltage). It is also true that the number of devices have increased, which may increase the total DC power consumption. On the other hand, we were able to design a much more robust front-end in what concerns to interference issues and PAPR variations.

Actually, the simulated results with 1-tone, 2-tones and multisine excitations confirmed an improvement in the dynamic range of approximately 6dB’s when compared to a simple ADC architecture.

As regard to future work the proposed circuitry, mainly the analogue signal splitter, should be evaluated in a circuit simulator followed by the respective implementation of the real circuit in order to assess its truly applicability

ACKNOWLEDGEMENT The authors would like to thank Portuguese Science and

Technology Foundation (FCT) for the PhD grant given to the first author (ref. 61527/2009), and financial support provided under Project PTDC/EEA-TEL/099646/2008 TACCS and also to the FP7 COST action ic0803 RFCSET.

REFERENCES [1] J. Mitola, “The software radio architecture”, IEEE

Communications Magazine, vol. 33, no. 5, pp. 26-38, May 1995. [2] Agilent Application Note, “Addressing SDR Design and

Measurement Challenges,” Agilent Technologies, Inc. 2009, August 03, 2009.

[3] J. Mitola, G.Q. Maguire, “Cognitive radio: making software radios more personal,” IEEE Personal Communications, vol. 6, no. 4, pp. 13-18, Aug 1999.

[4] R. Vaughan, N. Scott, and D. White, “The Theory of Bandpass Sampling,” IEEE Trans. on Signal Processing, vol. 39, no. 9, pp. 1973-1984, Sept. 1991.

[5] Texas Instruments Datasheet, “OPA698 - Unity-Gain Stable, Wideband Voltage Limiting Amplifier,” Texas Instruments, Inc. 2009, December 2008.

[6] Analog Devices Tutorial, “MT068 - Difference and Current Sense Amplifiers,” Analog Devices 2009.

[7] P. Cruz, N.B. Carvalho, K.A. Remley, “Evaluation of Nonlinear Distortion in ADCs using Multisines,” IEEE MTT-S Intl. Microwave Symp. Dig., Atlanta, GA, pp. 1433-1436, June 2008.

[8] Waveform Measurement and Analysis Technical Committee of the IEEE Instrumentation and Measurement Society, “1241-2000 - IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters,” IEEE Standard, June 13, 2001.

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