Instricp Parameters of transistors

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    PROJECT REPORTON

    Development of Software Program To Evaluate

    Intrinsic Parameters Of A Transistor

    Under the guidance of By

    Dr. Chanchal Sharma Ajay ajan

      !Scientist  ‘C’) A"itya ajan

     

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    Department of Solid State Physics Lab

    DEFENCE RESEARCH AND DEVELOPEN! OR"N#SA!#ONNE$ DELH#% #ND#A

    A#stract

     In this proect! the soft"are for the e#a$uation of intrinsic para%eter of a transistor has &een de#e$oped'

    This soft"are can &e used for con#erting one para%eter to other para%eter! storing different para%eter in

    different fi$e' This proect is he$pfu$ for those engineer "hich re(uired there para%eter in different for%'

    This  paper pro#ides ta&$es "hich contain the con#ersion &et"een the #arious co%%on t"oport para%eter

    *! +! h! ,BC-! .! and T' The con#ersions are #a$id for co%p$e/ nor%a$i0ing i%pedances' ,n e/a%p$e is pro

    #ided "hich #erifies the con#ersions to and fro% . para%eters'

    , ne" %ethod to deter%ine the s%a$$‐signa$ e(ui#a$ent circuit of 1ET2s is proposed' This %ethod consists i

    a direct deter%ination of e$trinsic s%a$$‐signa$ para%eters in a $o"‐ fre(uency &and' This %ethod is fast an

    accurate! and the deter%ined e(ui#a$ent circuit fits the .‐ para%eters #ery "e$$ up to %&.' ()*'

    3e ha#e de#e$oped the soft"are progra% in C++ to find out the different para%eters using .‐Para%eter'

    ii

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    !able of Contents

    Abstract...................................................................................................................... ii

    INTRODUCTION...........................................................................................................1

    DERIVATION……………………………………………………………………………………………………………

    ……………………………….2

    MEASURMENT OF CIRCUIT (INTRINSIC).......................................................................5

    RESULT..................................................................................................................... 11

    SUMMER AND CONCLUSIONS..................................................................................1!

    REFERENCES............................................................................................................ 1"

    A##ENDI$………………………………………………………………………………………………………………

    ………………………………1%

      SOURCE CODE

    ……………………………………………………………………………………………………………………………

    … 1%

      S&

    #ARAMETER……………………………………………………………………………………………………………

    …………………….'

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    Chapter

    I-TODCTIO-

    /OST %icro"a#e te/t&oo4s these days see% to pro#ide a ta&$e of the con#ersion &et"een the #arious * port para%eters' These *port para%eters often inc$ude *5i%pedance)! 0 5ad%ittance)! h 5hy&rid)! ,BC

    5chain)!. 5scattering)! and T 5chain scattering or chain transfer)'3hi$e the scattering para%eters ha#e &eesho"n 1l2 to &e #a$id for co%p$e/ nor%a$i0ing i%pedances 5"ith positi#e rea$ parts)! the ta&$es in 6*7689

    are not #a$id for co%p$e/ source and $oad i%pedances' Often! the ta&$es on$y pro#ide con#ersions for th

    cases "here port , and port * nor%a$i0ing i%pedances are e(ua$! i'e'! :o$ ; *

    >no"$edge of s%a$$circuit e(ui#a$ent circuit of a fie$d effect transistor is #ery usefu$ for the de#ic

     perfor%ance ana$ysis 5gain! noise! etc') in designing of %icro"a#e circuits and characteri0ing the de#ic

    techno $ogica$ process' Usua$$y! the s%a$$signa$ e(ui#a$ent circuit is o&tained &y opti%i0ing the co%ponen

    #a$ues to c$ose$y fit the s%a$$signa$ %icro"a#e scattering para%eters %easured on the de#ice' =o"e#er! thi

    e(ui#a$ent circuit deter%ination has se#era$ dra"&ac4s?

    i' ,ccurate &road&and .para%eter %easure%ent is re(uired'ii' 1or s%a$$ differences in the error function! the opti%u% e$e%ent #a$ues can #ary depending upon th

    opti%i0ation %ethod and the starting #a$ues'iii' To ha#e a physica$ significance! the e(ui#a$ent circuit re(uires a pre$i%inary deter%ination of certai

     para%eters 5gate resistance or inductances! for e/a%p$e)'

    In order to o#erco%e these difficu$ties "e ha#e chosen to de#e$op a ne" %ethod to deter%ine the 1ET s%a$

    signa$ e(ui#a$ent circuit' This %ethod consists in a direct! fast! and accurate %easure%ent of the differen

    e$e%ents per for%ed at re$ati#e$y $o" fre(uency' ,$though this %ethod "as de#e$oped in our $a&oratory fo

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    chip de#ices in a test fi/ture! it is #ery "e$$ suited for "aferpro&ing syste%s! and the first resu$ts o&tained

    using such pro&es are #ery pro%ising' Therefore! a $arge a%ount of data direct$y connected "ith the desig

    or the process of 1ET2s can &e o&tained "ithout any #ery high fre(uency %easure%ents or i%portan

    co%putationa$ effort'

    8

     

    Chapter

    DEI5ATIO-

    T"oport para%eters are defined for a genera$ *port net"or4 as sho"n in 1ig' 8' Using the #o$tages an

    currents defined in this figure! the #arious *port para%eters are "ritten as /anuscript receive" Decem#e

    %3 ,66%7 revise" April ,83 ,668 the author is with E(9( I"aho3 I"aho :alls3 ID ;8

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    *

    T Para%eters

    a8; T88'&* A T8*'a* 5Da)

     &8 ; T*8'&* A T**'a* 5&)

    3here the a2s and &2s are sho"n in 1ig' * and defined &e$o"'

    3here F indicates co%p$e/ conugate and :! is the nor%a$i0ing i%pedance for the th port' 1or t"oport

    net"or4s! :o8 and :o0 are the source and $oad i%pedances of the syste% in "hich the S para%eters of thet"oport are %easured or ca$cu$ated' I  j7 and Iij are the incident and ref$ected currents for the

    th port' >no"in

    that

    3e can so$#e 5a) and 5&) for Iji and Ij, and su&stitute the% into 5G) to get!

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    >no"ing a$so that!

     

    3here Vji and Vj, are the incident and ref$ected #o$tage at the th port! "e can su&stitute the e/pressions for

    13; and IjT a$ong "ith

     Into 58

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    as "e$$ as are straight for"ard' These con#ersions are acco%p$ished &y rearranging one set ofe(uations into the for% of the other' These con#ersions appear in %any of the references cited and are

    inc$uded here for co%p$eteness'

     

    Chapter

    /EAS/E-T O: CICIT !I-TI-SIC

     A. Determination of the Parasitic Resistances and Inductances

      ,s -ia%ant and a#iron ha#e suggested! the .para%eter %easure%ents at 0ero drain &ias #o$tage ca

     &e used for the e#a$uation of de#ice parasitic &ecause the e(ui#a$ent circuit is %uch si%p$er 6*7' Curtice

    and Ca%isa 6H7 ha#e used this &iasing condition to opti%i0e the de#ice parasitic using the progra%

    .UPERCOP,CT' ,n a$ternati#e approach is proposed in this "or4 "here a$$ the parasitic are direct$y

    deduced fro% %easure%ents per for%ed at @ds ;

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    9

     

    3here n is the idea$ity factor! 4 the Bo$t0%ann constant! T the te%perature! Cg! the gate capacitance! and

    Ig! the dc gate current'

    ,s the gate current increases! R!! decreases and C! increases &ut the e/ponentia$ &eha#ior of R!! #ersus

    @gs is the do%inant factorK conse(uent$y the ter% R dy' Cg' o tends to 0ero for gate current densities c$os

    to 9'8<

    8<G

     ,L%*' In that case! "e ha#e

     

    1or such a gate current! the capaciti#e effect of the gate disappears and the :$$ para%eter &eco%es rea$?

     

    In addition! the inf$uence of the Cpg and Cpd ! parasitic capacitances is neg$igi&$e and conse(uent$y the

    e/trinsic : para%eters are si%p$y deter%ined &y adding the parasitic resistances Rs! Rd! Rg! and

    inductances g! s! d to the intrinsic : para%eters' Then "e ha#e

     

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    D

    These e/pressions sho" that the i%aginary part of the * para%eters increases $inear$y #ersus fre(uency

    "hi$e the rea$ part is fre(uency independent' In addition it %ust &e noted that the rea$ part of :88 

    increases as $LIg' ,s sho"n in 1igs' and 9 the theoretica$ e/pressions 589)! 58D)! and 58) are in (uite

    good agree%ent "ith e/peri%enta$ findings'

    To o&tain these figures! the . para%eters of the de#ice "ere %easured using the =P G98< net"or4

    ana$y0er and then transfor%ed into : para%eters using the "e$$4no"n trans$ation for%u$as' These

    figures sho" a $inear e#o$ution of the : para%eters’ i%aginary parts "hi$e the rea$ part of :88 increases a

    $LIg' ,s a conse(uence! the parasitic inductances can &e pro#ided &y these p$ots? s! fro% I%5:8*)! g!

    fro% I%5:$$)! and d! fro% I%5 :**)' In addition! the $inear e/trapo$ation of the p$ot Re5:88) #ersus $LIg to

    the ordinate gi#es the #a$ue of Rs A RgA RcL' Therefore the : para%eters’ rea$ parts pro#ide three

    re$ations &et"een the four un4no"ns Rs! Rg! Rd! and Rc' ,t this step! an additiona$ re$ation is needed to

    separate the four un4no"ns' This additiona$ re$ation can &e?

    i' The #a$ue of the su% R s A R d deter%ined &y the con#entiona$ %ethod 697! 6D7' It %ust &e

    e%phasi0ed that this deter%ination can &e carried out "ith the net"or4 ana$y0er using the rea$

     part of :**ii' The #a$ue of R g if it can &e pro#ided fro% the resistance %easure%ent fro% pad to pad'

    iii' The #a$ue of R s and R d pro#ided &y dc %easure%ent 67i#' The #a$ue of R c if the channe$ techno$ogica$ para%eters are 4no"n'

      Therefore! the deter%ination of the four para%eters Rs! Rg! Rd! and Rc! does not constitute a rea

     pro&$e% since so%e redundant re$ations are a#ai$a&$e in %ost cases'

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    ,t this step! it shou$d &e noted that the gate resistance introduced in e/pression 589) is the gate resistance a

    re$ati#e$y high gate current' In that case! a gate finger has to &e considered as a $adder containing incre%entaseries resistances! shunt .chott4y diodes! and series channe$ resistances 6G7' This resu$ts in a non$inea

    character of R g! that &eco%es different to its #a$ue "hen the 1ET is nor%a$$y &iased as an a%p$ifier

    =o"e#er! for gate %eta$$i0ation resistances co%%on$y encountered 58

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    G

     

    Thus! the three un4no"ns c&! Cpg! and Cpd can &e ca$cu$ated using 58G)5*

     

    ,s sho"n in 1ig' the i%aginary parts of the e/peri%enta$ + para%eters increase $inear$y #ersu

    fre(uency! "hich is in (uite good agree%ent "ith e/pressions 58G)5*

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    H

    1ina$$y it has &een sho"n that a$$ the de#ice parasitic e$e%ents can &e %easured under 0ero drain &ia

    #o$tage conditions' Conse(uent$y it is possi&$e to deter%ine the intrinsic + para%eters and the e(ui#a$en

    circuit co%ponents for any gate and drain &ias #o$tages fo$$o"ing the %ethod descri&ed in .ection 88

    Before presenting so%e e/peri%enta$ resu$ts concerning the s%a$$signa$ e(ui#a$ent circuit! it see%

    i%portant to discuss the fre(uency range used for these %easure%ents' In fact! the fre(uency has to &e $o"

    enough in order for e/pressions 59)5G) to &e #a$id! "hi$e the $o" fre(uency &oundary is %ain$y deter%ine

     &y the net"or4 ana$y0er' In addition! the fre(uency range has to &e "ide enough in order to accurate$y defin

    the para%eter e#o$ution $a"s #ersus fre(uency' In the fo$$o"ing part! the resu$ts "i$$ &e gi#en in the case o

    %easure%ents perfor%ed in the range 89 =0' This fre(uency range has &een successfu$$y used for gat

    $ength in the range

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    Chapter

    ES=

      ,s pre#ious$y %entioned! this ne" %ethod for deter%ining the 1ET e(ui#a$ent circuit is (uite suita&$for %icro "a#e "afer pro&ing e(uip%ent' =o"e#er! since such a syste% is not yet in operation in ou

    $a&oratory! the %ethod "as de#e$oped for chip de#ices in a test fi/ture' , test fi/ture photograph is sho"n i

    1ig' G'

    This test fi/ture co%prises a center &$oc4 sand"iched &et"een t"o $atera$ &$oc4s' The chip is %ounted othe center &$oc4 and &onded to 9< M %icro strip $ines on

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    88

    i. The Equivalent Circuit Paraeter!

    In the case of a co%%ercia$

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     1ig' 8< sho"s the e#o$ution of the s%a$$signa$ para%eters g%! gd! Cgs! cgd! cds! R i and #ersus @gs fo

    t"o different draintosource &ias #o$tages' These e#o$utions are (uite si%i$ar to those o&tained using th

    con#entiona$ $easts(uares fit of the . para%eters 68

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    ii'  Broa"#Ban" S Paraeter!

    In order to sho" the #a$idity of our approach! the . para%eters "ere %easured in the range 8*D'9 =

    and co%pared "ith the . para%eters co%puted fro% the e(ui#a$ent circuit' The resu$ts of thi

    co%parison are gi#en in 1ig' 88 in a typica$ case'

    The a&sence of resonances or noise in the e/peri%enta$ data can &e noted' This figure sho"s that the

    ca$cu$ated . para%eters are in (uite good agree%ent "ith e/peri%enta$ findings for

    8

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    The three para%eters .88! .*8! .** "hi$e the %ain difference concerns .I*! "hich is not surprising'

    Therefore! the e(ui#a$ent circuit deduced fro% $o"fre(uency %easure%ents can fit #ery "e$$ the de#ice

    s para%eters up to *D'9 =S' The e(ui#a$ent circuit deter%ined in a $o"fre(uency range can thus &e

    used as an e$ectrica$ characteri0ation of the techno$ogica$ process as "e$$ as for the design of &oth hy&rid

    and %ono$ithic %icro"a#e circuits'

    89

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    Chapter

    S&ER' AND CONCL&S#ONS

    , ne" %ethod for deter%ining the s%a$$signa$ e(ui#a$ent circuit co%ponents of 1ET’s has &een descri&edThis %ethod consists in a direct deter%ination of a$$ the 1ET parasitic e$e%ents! inc$uding the Cpg and Cpd

     pad capacitances' The 4no"$edge of these parasitic e$e%ent #a$ues a$$o"s us to deter%ine the intrinsic s%a$

    signa$ para%eters after a fe" si%p$e %atri/ %anipu$ations' Co% pared "ith the con#entiona$ %ethod! &ase

    on . para%eters fit in a &road fre(uency range! this ne" %ethod has se#era$ ad#antages?

    8' ,$$ the e/trinsic and intrinsic co%ponents are direct$y deter%ined'

    *' This ne" %ethod is fast and accurate and on$y a net"or4 ana$y0er is needed'

    ' The %ethod is #ery "e$$ suited for "aferpro&ing syste%s since it is #ery fast and is perfor%ed in

    $o"fre(uency range'' The %ethod is #ery "e$$ suited to o&tain a $arge a%ount of data direct$y connected "ith the desig

    or the process of 1ET’s'

    8D

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    REFERENCES

    687 R' ,' inasian! .i%p$ified a,s E.1ET %ode$ to 8< =0! Electron. $ett '! #o$' 8! no' G! pp'

    9H98! 8H'

    6*7 1' -ia%ant and ' a#iron! easure%ent of the e/trinsic series e$e%ents of a %icro"a#e

    E.1ET under 0ero current condition! in Proc. 12th Euro%ean &icro'ave Con( '! 8HG*! pp' 989D'

    67 >' 3' ee! >' ee! ' .' .hur! Tho T' @u! P' C' T' Ro&erts! and ' J' =e$i/! .ource! drain and

    gate series resistances and e$ectron saturation #e$ocity in ion i%p$anted a,s 1ET’s! IEEE Tran!

     Electron Device!! #o$' E-*! pp' HGHH*! ay 8HG9'67 ,' Cappy! Proprietes physi(ues et perfor%ances potentie$$es des co%posants su&%icroni(ues a

    effet de cha%p? .tructure con #entionne$$e et V ga0 d’i$ectron &idi%ensionne$! These de

    -octorat! i$$e! 1rance! 8HGD'

    697 P' ' =o"er and N' ' Bechte$! Current saturation and s%a$$ signa$ characteristics of a,s fie$d

    effect transistors ,) *EEE Trun!. Electron Device!! #o$' E-*

    E-8! pp' 89889! ,ug' 8HG

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    SOCE CODE

    LL 1untion for con#et . Para%eter into + Para%eter'

    #oid con#ersion??funt*5)

    W

      ifstrea% fin*5XsYpara8't/tX!ios??in)K

      fin*'see4g5

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    W ofstrea% fout5XyYpara8't/tX!ios??out]ios??ate)K

      dou&$e d6G7!-697K

    d687;5558AsYpara%687687687)F58AsYpara%6*76*7687))5sYpara%6876876*7FsYpara%6*76*76*7))K

    d6*7;5558AsYpara%687687687)FsYpara%6*76*76*7)A5sYpara%6876876*7F58AsYpara%6*76*7687)))K

    d67;55sYpara%6876*7687FsYpara%6*7687687)5sYpara%6876*76*7FsYpara%6*76876*7))K

    d67;55sYpara%6876*7687FsYpara%6*76876*7)A5sYpara%6876*76*7FsYpara%6*7687687))K

      d697;d687d67K

      d6D7;d67d6*7K

      d67;5d697Fd697)A5d6D7Fd6D7)K

    -687;d697K

    -6*7;d6D7K

    -67;d697Ld67K

    -67;d6D7Ld67K

    LLLLLLLLLLLLLy88LLLLLLLLLLLLLLLLLLLLLLLLLLL

    dou&$e $6G7K

    $687;5558sYpara%687687687)F58AsYpara%6*76*7687))5sYpara%6876876*7FsYpara%6*76*76*7))K

    $6*7;5558sYpara%687687687)FsYpara%6*76*76*7)A5sYpara%6876876*7F58AsYpara%6*76*7687)))K

      $67;d67K

      $67;d67K  $697;$687A$67K

      $6D7;5$6*7A$67)F58)K

    yYpara%687687687;55$697F-67)5$6D7F-67))K

    yYpara%6876876*7;55$697F-67)5$6D7F-67))K

    foutXZnXfre(K

    goto/y5!co$)K

    coutX XyYpara%687687687K

    foutX XyYpara%687687687K

    goto/y58!co$)K

    coutX XyYpara%6876876*7K

    foutX XyYpara%6876876*7K

    8H

    LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLy*8LLLLLLLLLLLLLLLLLLLLLLLLLLL

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    yYpara%6*7687687;59

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    yYpara%6*76*76*7;55%697F-67)5%6D7F-67))K

    goto/y59H!co$)K

    coutX XyYpara%6*76*7687K

    foutX XyYpara%6*76*7687K

    goto/y5DG!co$)K

    coutX XyYpara%6*76*76*7K

    foutX XyYpara%6*76*76*7K

    fout'c$ose5)K

    \

    *8

    LL 1untion for create changes in + Para%eter 

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    #oid con#ersion??step*a5)

    W

    int i!K

    dou&$e f;

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    W

    dou&$e "!#!cpg;

    int i!K

    ofstrea% fout5XyYpara*'t/tX!ios??out]ios??ate)K

    ";5*'

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    #oid con#ersion??funt5)

    W

    int i!K

    dou&$e f;

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    W

    ofstrea% fout5X0Ypara't/tX!ios??out]ios??ate)K

    dou&$e p6G7!d!r67K

    foutXZnXfre(K

    goto/y58!co$)K

    coutfre(K

     p687;5yYpara%*687687687FyYpara%*6*76*7687)5yYpara%*6876876*7FyYpara%*6*76*76*7)K

     p6*7;5yYpara%*687687687FyYpara%*6*76*76*7)A5yYpara%*6876876*7FyYpara%*6*76*7687)K

     p67;5yYpara%*6876*7687FyYpara%*6*7687687)5yYpara%*6876*76*7FyYpara%*6*76876*7)K

     p67;5yYpara%*6876*7687FyYpara%*6*76876*7)A5yYpara%*6876*76*7FyYpara%*6*7687687)K

     p697;p687p67K

     p6D7;p6*7p67K

    d;5p697Fp697)A5p6D7Fp6D7)K

    r687;p697LdK

    r6*7;p6D7LdK

    LLLLLLLLLLLLLLLLLLLL088LLLLLLLLLLLLLLLLLLLLLLLLLLLL

    0Ypara%687687687;55yYpara%*6*76*7687Fr687)5yYpara%*6*76*76*7Fr6*7))K

    0Ypara%6876876*7;55yYpara%*6*76*7687Fr6*7)A5yYpara%*6*76*76*7Fr687))K

    foutX X0Ypara%687687687K

    goto/y5!co$)K

    coutX X0Ypara%687687687K

    foutX X0Ypara%6876876*7K

    goto/y58!co$)K

    coutX X0Ypara%6876876*7K

    *9

    LLLLLLLLLLLLLLLL0*8LLLLLLLLLLLLLLLLLLLLLLLLLLLL

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    0Ypara%6*7687687;55yYpara%*6*7687687Fr687)5yYpara%*6*76876*7Fr6*7))F58)K

    0Ypara%6*76876*7;55yYpara%*6*7687687Fr6*7)A5yYpara%*6*76876*7Fr687))F58)K

    foutX X0Ypara%6*7687687K

    goto/y5**!co$)K

    coutX X0Ypara%6*7687687K

    foutX X0Ypara%6*76876*7K

    goto/y58!co$)K

    coutX X0Ypara%6*76876*7K

    LLLLLLLLLLLLLLLL08*LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL

    0Ypara%6876*7687;55yYpara%*6876*7687Fr687)5yYpara%*6876*76*7Fr6*7))F58)K

    0Ypara%6876*76*7;55yYpara%*6876*7687Fr6*7)A5yYpara%*6876*76*7Fr687))F58)K

    foutX X0Ypara%6876*7687K

    goto/y58!co$)K

    coutX X0Ypara%6876*7687K

    foutX X0Ypara%6876*76*7K

    goto/y59

    coutX X0Ypara%6876*76*7K

    LLLLLLLLLLLLLLLL0**LLLLLLLLLLLLLLLLLLLLLLLLLLLL

    0Ypara%6*76*7687;55yYpara%*687687687Fr687)5yYpara%*6876876*7Fr6*7))K

    0Ypara%6*76*76*7;55yYpara%*687687687Fr6*7)A5yYpara%*6876876*7Fr687))K

    foutX X0Ypara%6*76*7687K

    goto/y59G!co$)K

    coutX X0Ypara%6*76*7687K

    foutX X0Ypara%6*76*76*7K

    goto/y5D!co$)K

    coutX X0Ypara%6*76*76*7K

    \

    *D

    LL1untion for con#ert : Para%eter to + Para%eter'

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    30/34

    #oid con#ersion??funtH5)

    W

    int i!K

    dou&$e f;

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    #oid con#ersion??funt8

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    32/34

    LLLLLLLLLLLLLLLLy*8LLLLLLLLLLLLLLLLLLLLLLLLLLLL

    yYpara%6*7687687;550Ypara%6*7687687Fr687)50Ypara%6*76876*7Fr6*7))F58)K

    yYpara%6*76876*7;550Ypara%6*7687687Fr6*7)A50Ypara%6*76876*7Fr687))F58)K

    foutX XyYpara%6*7687687K

    goto/y5**!co$)K

    coutX XyYpara%6*7687687K

    foutX XyYpara%6*76876*7K

    goto/y58!co$)K

    coutX XyYpara%6*76876*7K

    LLLLLLLLLLLLLLLLy8*LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL

    yYpara%6876*7687;550Ypara%6876*7687Fr687)50Ypara%6876*76*7Fr6*7))F58)K

    yYpara%6876*76*7;550Ypara%6876*7687Fr6*7)A50Ypara%6876*76*7Fr687))F58)K

    foutX XyYpara%6876*7687K

    goto/y58!co$)K

    coutX XyYpara%6876*7687K

    foutX XyYpara%6876*76*7K

    goto/y59

    coutX XyYpara%6876*76*7K

    LLLLLLLLLLLLLLLLy**LLLLLLLLLLLLLLLLLLLLLLLLLLLL

    yYpara%6*76*7687;550Ypara%687687687Fr687)50Ypara%6876876*7Fr6*7))K

    yYpara%6*76*76*7;550Ypara%687687687Fr6*7)A50Ypara%6876876*7Fr687))K

    foutX XyYpara%6*76*7687K

    goto/y59G!co$)K

    coutX XyYpara%6*76*7687K

    foutX XyYpara%6*76*76*7K

    goto/y5D!co$)K

    coutX XyYpara%6*76*76*7K

    \

    *H

    .P,R,ETER

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    33/34

    ^1REM=: ,6.887 ,N6.887 ,6.*87 ,N6.*87 ,6.8*7 ,N6.8*7 ,6.**7 ,N6.**7

    ^ E.1ET E.1ET E.1ET E.1ET E.1ET E.1ET E.1ET E.1ET

    _ =0 . , R 9

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     **'

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