Interface 8088 I/F with basic IO, RAM and 8255 and 8255

InterfaceInterface

8088 I/F with basic IO, RAM8088 I/F with basic IO, RAM

and 8255and 8255

TopicsTopics

Timing diagramTiming diagram• Address Bus, R/W, DataAddress Bus, R/W, Data• Memory Map I/OMemory Map I/O

Address DecodingAddress Decoding• CPU is addressable lager than devices.CPU is addressable lager than devices.

Chip SupportsChip Supports• TTL : De-multiplexer, Latch, BufferTTL : De-multiplexer, Latch, Buffer

Timing DiagramTiming Diagram : Read Cycle: Read Cycle

Timing DiagramTiming Diagram : Write Cycle: Write Cycle

BUS Buffering and LatchingBUS Buffering and Latching

Basic ArchitectureBasic Architecture

Dr.Jim Plusquellic, University of Maryland, Baltimore CountyDr.Jim Plusquellic, University of Maryland, Baltimore Countyhttp://www.csee.umbc.edu/~plusquel/310/http://www.csee.umbc.edu/~plusquel/310/

Bus ArchitectureBus Architecture

Address: Address: • If I/O, a value between 0000H and FFFFH If I/O, a value between 0000H and FFFFH

is issued. is issued. • If memory, it depends on the If memory, it depends on the

architecture: architecture: 20 -bits (8086/8088) 20 -bits (8086/8088) 24 -bits (80286/80386SX) 24 -bits (80286/80386SX) 25 -bits (80386SL/SLC/EX) 25 -bits (80386SL/SLC/EX) 32 -bits (80386DX/80486/Pentium) 32 -bits (80386DX/80486/Pentium) 36 -bits (Pentium Pro/II/III) 36 -bits (Pentium Pro/II/III)

Bus ArchitectureBus Architecture

Data: Data: • 8 -bits (8088) 8 -bits (8088) • 16 -bits (8086/80286/80386SX/SL/SLC/EX) 16 -bits (8086/80286/80386SX/SL/SLC/EX) • 32 -bits (80386DX/80486/Pentium) 32 -bits (80386DX/80486/Pentium) • 64 -bits (Pentium/Pro/II/III) 64 -bits (Pentium/Pro/II/III)

Control: Control: • Most systems have at least 4 control bus Most systems have at least 4 control bus

connections (active low). connections (active low). • MRDC (Memory ReaD Control), MWRC , IORC MRDC (Memory ReaD Control), MWRC , IORC

(I/O Read Control), IOWC (I/O Read Control), IOWC

Bus StandardsBus Standards ISA ISA ((Industry Standard ArchitectureIndustry Standard Architecture ): ): 8 MHz 8 MHz

• 8-bit 8-bit ((8086/80888086/8088 ) )• 16-bit 16-bit ((80286-Pentium80286-Pentium ) )

EISA EISA : : 8 MHz 8 MHz • 32-bit 32-bit ((older 386 and 486 machinesolder 386 and 486 machines ). ).

PCI PCI ((Peripheral Component InterconnectPeripheral Component Interconnect ): ):• 33 MHz 32-bit or 64-bit 33 MHz 32-bit or 64-bit ((PentiumsPentiums))

VESA (Video Electronic Standards Association):VESA (Video Electronic Standards Association):• 32-bit or 64-bit (Pentiums), Runs at processor speed. 32-bit or 64-bit (Pentiums), Runs at processor speed. • Only disk and video. Competes with the PCI but is not Only disk and video. Competes with the PCI but is not

popular. popular.

Bus StandardsBus Standards USB (Universal Serial Bus):USB (Universal Serial Bus):

• 12 Mbps / 480 Mbps, Serial connection to 12 Mbps / 480 Mbps, Serial connection to microprocessor. microprocessor.

• For keyboards, the mouse, modems and sound cards. To For keyboards, the mouse, modems and sound cards. To reduce system cost through fewer wires. reduce system cost through fewer wires.

IEEE 1394IEEE 1394• 400 Mbps, primary target is audio/visual consumer 400 Mbps, primary target is audio/visual consumer

electronic devices electronic devices AGP (Advanced Graphics Port): 66MHz AGP (Advanced Graphics Port): 66MHz

• 64-bits for 533MB/sec, Fast parallel connection, video 64-bits for 533MB/sec, Fast parallel connection, video cards. To accommodate the new DVDcards. To accommodate the new DVD(Digital Versatile Disk) players.(Digital Versatile Disk) players.

Memory : Blank LayoutMemory : Blank Layout

Memory : Blank LayoutMemory : Blank Layout

Memory : Blank LayoutMemory : Blank Layout

Basic I/O ArchitectureBasic I/O Architecture

Interrupt VectorInterrupt Vector : DOS PC: DOS PC

IO SpaceIO Space

Basic I/O Interface : InputBasic I/O Interface : Input

Basic I/O Interface : OutputBasic I/O Interface : Output

I/O Port DecodingI/O Port Decoding

MEMORYMEMORY

Memory TypesMemory Types

Two basic types:Two basic types:• ROM: Read-only memoryROM: Read-only memory• RAM: Read-Write memoryRAM: Read-Write memory

Four commonly used memories:Four commonly used memories:• ROMROM• Flash (EEPROM)Flash (EEPROM)• Static RAM (SRAM)Static RAM (SRAM)• Dynamic RAM (DRAM)Dynamic RAM (DRAM)

Memory ChipsMemory Chips The data pins are typically bi-directional in The data pins are typically bi-directional in

read-write memories. read-write memories. • The number of data pins is related to the size The number of data pins is related to the size

of the memory location. For example, an 8-bit of the memory location. For example, an 8-bit wide (byte-wide) memory device has 8 data wide (byte-wide) memory device has 8 data pins. pins.

Each memory device has at least one chip Each memory device has at least one chip select (CS) or chip enable (CE) or select (S) select (CS) or chip enable (CE) or select (S) pin that enables the memory device. pin that enables the memory device. • This enables read and/or write operations. This enables read and/or write operations. • If more than one are present, then all must be If more than one are present, then all must be

0 in order to perform a read or write. 0 in order to perform a read or write.

SRAM vs. DRAMSRAM vs. DRAM

SRAMsSRAMs• SRAMs used for caches have access times as SRAMs used for caches have access times as

low as 10ns . low as 10ns .

DRAMsDRAMs• SRAMs are limited in size (up to about 128Kb). SRAMs are limited in size (up to about 128Kb). • DRAMs are available in much larger sizes, e.g., DRAMs are available in much larger sizes, e.g.,

64M X 1. 64M X 1. • DRAMs MUST be refreshed every 2 to 4 ms DRAMs MUST be refreshed every 2 to 4 ms • Since they store their value on an integrated Since they store their value on an integrated

capacitor that loses charge over time. capacitor that loses charge over time.

Memory Address Memory Address DecodingDecoding

Memory Address DecodingMemory Address Decoding The processor can usually address a The processor can usually address a

memory space that is much larger memory space that is much larger than the memory space covered by than the memory space covered by an individual memory chip. an individual memory chip.

In order to splice a memory device In order to splice a memory device into the address space of the into the address space of the processor, decoding is necessary. processor, decoding is necessary.

For example, the 8088 issues 20-bit For example, the 8088 issues 20-bit addresses for a total of 1MB of addresses for a total of 1MB of memory address space. memory address space.

Ex. Memory Address DecodingEx. Memory Address Decoding

The BIOS on a 2716 EPROM has only The BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins. 2KB of memory and 11 address pins.

A decoder can be used to decode the A decoder can be used to decode the additional 9 address pins and allow additional 9 address pins and allow the EPROM to be placed in any 2KB the EPROM to be placed in any 2KB section of the 1MB address space. section of the 1MB address space.

Ex. Memory Address DecodingEx. Memory Address Decoding

To determine the address range that a To determine the address range that a device is mapped into: device is mapped into:

Ex. Memory Address DecodingEx. Memory Address Decoding

This 2KB memory segment maps into This 2KB memory segment maps into the reset location of the 8086/8088 the reset location of the 8086/8088 (FFFF0H).(FFFF0H).

NAND gate decoders are not often NAND gate decoders are not often used. Rather the 3-to-8 Line Decoder used. Rather the 3-to-8 Line Decoder (74LS138) is more common.(74LS138) is more common.

3-to-8 Line Decoder3-to-8 Line Decoder

G2A, G2B, and G1 must be active.G2A, G2B, and G1 must be active. Each output of the decoder can be attached to an Each output of the decoder can be attached to an

2764 EPROM ( 8K X 8 ). 2764 EPROM ( 8K X 8 ).

EPROM 2764 x 8EPROM 2764 x 8

More on Address DecodingMore on Address Decoding

Yet a third possibility is a PLD Yet a third possibility is a PLD (Programmable Logic Device). (Programmable Logic Device). • PLDs come in three varieties: PLDs come in three varieties: • PLA (Programmable Logic Array) PLA (Programmable Logic Array) • PAL (Programmable Array Logic) PAL (Programmable Array Logic) • GAL (Gated Array Logic) GAL (Gated Array Logic)

A PAL example (16L8) is commonly used to decode the A PAL example (16L8) is commonly used to decode the memory address, particularly for 32-bit addresses memory address, particularly for 32-bit addresses generated by the 80386DX and above.generated by the 80386DX and above.

PLD as address decoderPLD as address decoder

AMD 16L8 PAL decoder. AMD 16L8 PAL decoder. It has 10 fixed inputs (Pins 1-9, 11), two fixed outputs (Pins It has 10 fixed inputs (Pins 1-9, 11), two fixed outputs (Pins

12 and 19) and 6 pins that can be either (Pins 13-18). 12 and 19) and 6 pins that can be either (Pins 13-18).

8088 Memory Interface8088 Memory Interface

The memory systems "sees" the 8088 as a The memory systems "sees" the 8088 as a device with: device with: • 20 address connections (A19 to A0). 20 address connections (A19 to A0). • 8 data bus connections (AD7 to AD0). 8 data bus connections (AD7 to AD0). • 3 control signals, IO/M, RD, and WR. 3 control signals, IO/M, RD, and WR.

Interfacing the 8088 with: Interfacing the 8088 with: • 32K of EPROM (at addresses F8000H-FFFFFH). 32K of EPROM (at addresses F8000H-FFFFFH). • 512K of SRAM (at addresses 00000H-7FFFFH). 512K of SRAM (at addresses 00000H-7FFFFH).

8088 Memory Interface: EPROM8088 Memory Interface: EPROM

8088 Memory Interface: EPROM8088 Memory Interface: EPROM

The EPROM will also require the The EPROM will also require the generation of a wait state. generation of a wait state. • The EPROM has an access time of 450ns . The EPROM has an access time of 450ns . • The 74LS138 requires 12ns to decode. The 74LS138 requires 12ns to decode.

The 8088 runs at 5MHz and only allows The 8088 runs at 5MHz and only allows 460ns for memory to access data. 460ns for memory to access data.

A wait state adds 200ns of additional timeA wait state adds 200ns of additional time

8088 Memory Interface: RAM8088 Memory Interface: RAM

8088 Memory Interface: RAM8088 Memory Interface: RAM

The 62256s on the previous slide are The 62256s on the previous slide are actually SRAMs. Access times are on actually SRAMs. Access times are on order of 10ns . order of 10ns .

Flash memory can also be interfaced Flash memory can also be interfaced

to the 8088. However, the write time to the 8088. However, the write time ( 400ms !) is too slow to be used as ( 400ms !) is too slow to be used as RAM.RAM.

8088 I/F with8088 I/F with Programmable Peripheral Programmable Peripheral

Interface 8255Interface 8255Part IPart I

PPI : 82C55PPI : 82C55 The 82C55 is a popular interfacing component, The 82C55 is a popular interfacing component,

that can interface any TTL-compatible I/O device that can interface any TTL-compatible I/O device to the microprocessor. to the microprocessor.

It is used to interface to the keyboard and a It is used to interface to the keyboard and a parallel printer port in PCs (usually as part of an parallel printer port in PCs (usually as part of an integrated chipset). integrated chipset).

Requires insertion of wait states if used with a Requires insertion of wait states if used with a microprocessor using higher that an 8 MHz clock. microprocessor using higher that an 8 MHz clock.

PPI has 24 pins for I/O that are programmable in PPI has 24 pins for I/O that are programmable in groups of 12 pins and has three distinct modes of groups of 12 pins and has three distinct modes of operation. operation.

In the PC, an 82C55 or its equivalent is decoded In the PC, an 82C55 or its equivalent is decoded at I/O ports 60H-63H. at I/O ports 60H-63H.

8255 Block Diagram8255 Block Diagram

Pin layout of 8255Pin layout of 8255

Interfacing 8255 PPIInterfacing 8255 PPI

That’s allThat’s all