View
30
Download
1
Category
Preview:
DESCRIPTION
Introduction to Digital Electronics
Citation preview
EEE 4343
Dr. Fan - eee4343_note1 11
Introduction to Digital Electronics
Department of Electrical and Computer EngineeringFlorida International University
Instructor: Dr. Jeffrey Fan
MOS Field-Effect
Dr. Fan - eee4343_note1 22
Transistors (MOSFETs)
Dr. Fan - eee4343_note1 3
Device Structure
Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b)
cross-section.
• Typically L = 0.1 to 3 µm (channel length), less than 0.1 – nanometer, n+ heavily
doped n-type silicon
• W = 0.2 to 100 µm (channel width), used as resistors or capacitors
• Thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
Dr. Fan - eee4343_note1 4
• NMOS transistor with a positive voltage applied to the gate (G)
• p-substrate for NMOS, depletion region is thin
• B (Bulk), S (Source) and D (Drain) grounded
• n channel is induced at the top of the substrate beneath the gate.
• n type MOS – called NMOS ( p type MOS is called ? )
Dr. Fan - eee4343_note1 5
• NMOS transistor with vGS > Vt and with a small vDS applied. (Vt: threshold voltage)
• Device acts as a resistance whose value is determined by vGS.
• Channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS –
Vt) vDS. Induced channel is also called “inversion layer”.
Dr. Fan - eee4343_note1 6
The iD–vDS characteristics of the MOSFET when the voltage applied
between drain and source, vDS, is kept small. The device operates as a
linear resistor whose value is controlled by vGS.
vGS – Vt: excess gate voltage, effective voltage or overdrive voltage
Dr. Fan - eee4343_note1 7
• Operation of the enhancement NMOS transistor as vDS is increased.
• Induced channel acquires a tapered shape, resistance increases as vDS increases.
• vGS is kept constant at a value > Vt
• Pinch-off on channel – Tunneling effort
Dr. Fan - eee4343_note1 8
Enhancement-type NMOS transistor operated with vGS > Vt. (threshold voltage)
The voltage at saturation VSDsat = VGS – Vt
Triode Region: Active region, overdrive region
Dr. Fan - eee4343_note1 9
Dr. Fan - eee4343_note1 10
• Cross-section of a CMOS integrated circuit.
• PMOS transistor is formed in a separate n-type region, known as n well.
• n-type body is used and the n device is formed in a p well.
• SiO2 for isolation
Device Structure and Device Physics
Dr. Fan - eee4343_note1 11
(a) Circuit symbol for the n-channel enhancement-type MOSFET.
(b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it
from the drain and to indicate device polarity (i.e., n channel).
(c) Simplified circuit symbol to be used when the source is connected to the body or
when the effect of the body on device operation is unimportant.
S: Source G: Gate D: Drain B: Bulk
Regions of Operation of the Enhancement NMOS Transistor
Dr. Fan - eee4343_note1 12
Dr. Fan - eee4343_note1 13
The relative levels of the terminal voltages of the enhancement NMOS
transistor for operation
- in the triode region (active region)
- in the saturation region.
Dr. Fan - eee4343_note1 14
(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with
the normal directions of current flow indicated.
(b) The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2.
(c) Triode, Saturation, and Cutoff (vGS – Vt < 0) regions
Dr. Fan - eee4343_note1 15
iD–vGS characteristic for an enhancement-type NMOS transistor in
saturation (Vt = 1 V, k’n W/L = 1.0 mA/V2). Vt: threshold voltage
Dr. Fan - eee4343_note1 16
• Large-signal equivalent-circuit model of an n-channel MOSFET
operating in the saturation region.
• Acting like a current source (because of saturation)
Dr. Fan - eee4343_note1 17
• Large-signal equivalent circuit model of the n-channel MOSFET (NMOS) in
saturation
• Incorporating the output resistance ro. (acting as a load)
• The output resistance models the linear dependence of iD on vDS
Dr. Fan - eee4343_note1 18
• Effect of vDS on iD in the saturation region.
• MOSFET parameter VA depends on the process technology and, for a given
process (lamda), is proportional to the channel length L.
• lamda – related to channel length modulation (ideal value = 0)
PMOS Device
Dr. Fan - eee4343_note1 19
(a) Circuit symbol for the p-channel enhancement-type MOSFET. (PMOS)
(b) Modified symbol with an arrowhead on the source lead.
(c) Simplified circuit symbol - source is connected to the body.
(d) The MOSFET with voltages applied and the directions of current flow indicated.
Regions of Operation of the Enhancement PMOS Transistor
Dr. Fan - eee4343_note1 20
Dr. Fan - eee4343_note1 21
The relative levels of the terminal voltages of the enhancement-type
PMOS transistor for operation
- in the triode region
- in the saturation region.
Summary of MOSFET Current Voltage (i-v) Characteristics
Dr. Fan - eee4343_note1 22
NMOS and PMOS in conditions for triode and saturation regions
Recommended