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October 2008Revision: EB26_02.4
LatticeMico32/DSP Development Board for LatticeECP2
User’s Guide
2
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Introduction
This document describes the features and functionality of the LatticeMico32™/DSP Development Board forLatticeECP2™ devices. This board is designed as a hardware platform for design and development with theLatticeMico32 microprocessor, as well as for the LatticeMico8™ microcontroller, and for various DSP functions.
Note: There are two versions of this board, named version 1 (v1) and version 2 (v2). Differences between the v1and v2 boards are described in this document as required. The appendices of this document contain schematics ofboth versions. In summary, v2 boards include the following changes:
•
Copper plating indicates v2 in text (HPEminiv2)
•
A pushbutton has been added for USB reset. This allows the FPGA to be reset independently from the USB Cable circuitry.
•
Boards are populated with a MachXO-2280 device (v1 boards were populated with a MachXO-640).
•
Board color is blue, and board is fully RoHS compliant.
This document describes the numerous functional elements of the board. The schematics of the board can befound in the appendices at the end of this document.
Features
• Lattice ECP2-50 FPGA with 48 kLUTs, 387 kbit of Embedded Block RAM, 18 sysDSP™ blocks, 72 18x18 multi-pliers, 6 PLLs, and 500 user I/O pins
• Lattice MachXO™ with 640 LUTs and 6.1 kbit of RAM
• Serial Flash with at least 8 Mbit for non-volatile storage of FPGA configuration data.
• DDR SODIMM socket for DDR SDRAM modules (DDR1, 100-133MHz, 32-bit data bus)
• Parallel Flash 2x128 Mbit, organized as 8M 32-bit words
• SRAM 2x4 Mbit, organized as 256K 32-bit words
• USB 2.0 connector and integrated ispDOWNLOAD
®
cable for JTAG programming the FPGA
• Flywire connector for programming using an ispDOWNLOAD cable (available separately)
• 9-pin RS232 serial port (230 Kbps)
• 15-pin VGA (64 color encoding)
• Ethernet 10/100 M full/half duplex
• Two USB 2.0 compatible host connectors
• One USB 2.0 compatible target connector
• One USB OTG (On-the-Go) connector
• Expansion connector with 46 user I/Os
• 12x12 prototyping area for the integration of individual components (connections to the FPGA)
• Sigma Delta D/A converter
• Two SATA interfaces with four LVDS signal pairs for high-speed data transfer
(Note: Full SATA implementation is not supported)
• AC’97 Stereo Audio Codec with line input and output
• LCD connector for character displays, with contrast potentiometer
• 25 MHz oscillator with clock distribution buffer
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
• Eight LEDs with test points for each LED
• Two-character 7-segment display
• Green LED to indicate the proper operation of the 3.3V and 2.5 V power supplies
• Blue LED which shows the configuration status (“DONE”)
• Red LED to signal that the FPGA can be configured (“INIT”)
• Yellow LED indicating the FPGA PROGRAM# I/O is asserted (“PROGRAM#”)
• 3x4 key matrix
• Four DIP switches
• Single step key
• Program key to initiate the configuration sequence of the FPGA from SPI Flash memory
• Reset key
• 5V power supply
• Switching regulator for the generation of the 3.3V I/O voltage, the 2.5V DDR and LVDS voltages and the 1.2V core voltage
Getting Started
1. Unpack all components and compare them to the packaging list. All boards leave the factory fully tested. Detailed information can be found in the Troubleshooting section of this document.
2. Place the board in front of you so that the keyboard is on the left side.
3. Take the regulated DC power supply which has been supplied with the package and connect it to the power jack on the board. Two green power-on LEDs will illuminate to confirm that power is correctly applied to the board (regulating 5V to 3.3V and 2.5V).
4. To check the basic functionality, please see the Troubleshooting section of this document.
A number of example and demonstration programs are available for the LatticeMico32/DSP Development Board forLatticeECP2. Check the Lattice web site at: www.latticesemi.com/boards (and navigate to the correct board) to findadditional documentation, such as the LatticeMico32 Tutorial, which describes how to use the LatticeMico32 Sys-tem software to develop microprocessor solutions for this board. Additional sample programs are included with theLatticeMico32 System software. Check the software help to find these examples.
Note: Unless described otherwise, positional statements (left, right etc.) refer to the board positioned in front of youso that the key pad is in the bottom left corner.
Related Literature
•
LatticeMico32 Development Kit User’s Guide
: This guide includes a tutorial for using the LatticeMico32 Sys-tem software with the LatticeMico32/DSP Development Board. This document is written for the first generation board (with LatticeECP-33 FPGA), which is similar to the board described in this document. While this document may be useful, please remember there are differences in the designs of these boards.
Be sure to check the Lattice web site for updates to this document as well.
These documents can be downloaded from the Lattice web site at: www.latticesemi.com/boards. Select the
FPGA/FPSC Boards -> LatticeMico32/DSP Development board for LatticeECP2
and click on the
User Manu-als
link.
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Overview
The following block diagram gives you an overview of the functionality of your LatticeMico32/DSP DevelopmentBoard. Subsequent pages illustrate the position of connectors, user interfaces, and modules.
Figure 1. LatticeMico32/DSP Development Board Block Diagram
Table 1. Board Defaults
Item TypeDefault Status Comments
LatticeECP2-50 FPGA Programmed
The bitstream is based on Example PlatformA and the LED7SegsTest_ecp2 project. The LED7SegsTest_ecp2.mem and LED7SegsTest_ecp2.bit files are included in the LED7SegsTest_ecp2 project.
Visual indications of operation are:• Left to Right and Right to Left scanning of the 8 LEDs.• Upcount and roll over of the 7 segment displays from 0 to 99
decimal at ~1 second intervals.
LCD Backlight (X5) Jumper Open Backlight is off.
Configuration Switch TMS Switch Off (Down) LatticeECP2-50 FPGA can be programmed.
Sigma Delta DAC Converter Jumper Open
Contrast Control Reostat Variable Not set to any specific level.
4-place DIP - Logic 1 Switch Off Logic 0 on selected pins - see Table 18.
SODIMM DDR 400 Setting (X18) Jumper Shorts Pins 1 and 2 Set to below DDR400 memory use.
LatticeECP2-50
672 fpBGA
AC97
Ethernet10/100
3p LVDSSATA
3p LVDSSATA
ExpansionConnector
RS232
PRGTo PC
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Peripheral Interfaces
This section describes all peripheral interfaces of the LatticeMico32/DSP Development Board for LatticeECP2 inalphabetical order.
Figure 2 shows the position of peripheral interfaces available on the board.
Figure 2. Peripheral Interfaces (Version 1 Board Shown in this Figure)
AudioLine In
Line Out
Mini USBOTG Connector
VGAConnector
Power Plug Ethernet10/100M
RS232Connector
ExpansionConnector
DDR SDRAMSockel
USB HostConnector
SATA LVDSConnectors
2.5VTestpoint
3.3VTestpoint
GNDTestpoint
1.2VTestpoint
CLKTestpoint
FlywireConnector
High-SpeedUSB for
Configuration
LCDConnector
In Version 2 of this board, the on-board USB cable circuit has been updated.
1. A USB RESET# pushbutton has been added. The Version 1 board includes a single Reset pushbutton that resets both the LatticeECP2 FPGA and the USB cable. The addition of the USB RESET# button allows the FPGA to be reset independent from the USB cable circuit.
2. In the Version 2 board, the MachXO device has been changed from a MachXO640 to a MachXO2280 device.
Sigma DeltaDAC Connector
USB ResetPushbutton(v.2 board)
MachXO-640(v.1 board),
MachXO-2280(v.2 board)
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Audio Interface
The audio interface has two connectors for 3.5 mm stereo jacks. The upper one is for line-out, the lower for line-in.They are connected to the audio codec LM4549B by National Semiconductor.
Table 2. Audio Codec U1001 Pin Definitions
The signal CODEC CS# has a pull-up resistor of 10 k
Ω
. The Signal CODEC MODE selects the interface to use forthe codec. Driving it high corresponds to SPI, low to I
2
C.
Detailed information on the audio codec can be found at the National Semiconductor website at www.national.com.
Clock Sources
A 25MHz oscillator supplies the FPGA (pin AD15), the CPLD (pin A8), the Ethernet controller and the ExpansionConnector (pin 29 of X12). The frequency can be measured via testpoint CLK. To generate other clock frequenciesuse the PLLs of the FPGA. You can find detailed information on the usage of the PLLs on the Lattice website and inthe LatticeECP2/M Family Data Sheet.
The USB controller requires a 24MHz quartz for configuration. Another 12MHz quartz supplies the USBhost/peripheral controller.
Note: Since the Ethernet controller demands a 25MHz clock, no other basic clock can be used. Use the PLLs of theFPGA to generate custom frequencies.
DDR SODIMM Socket for DDR SDRAM Modules
The board includes a standard DDR1 SODIMM socket with 200 contacts (DDR SDRAM Module is not included).The upper four bytes of the data bus (D[63:32]) are not connected. Thus, only half of the capacity of the memorymodule is available.
The DDR SODIMM socket is factory configured to provide a regulated 2.5V. DDR400 modules require a powersupply of 2.6V (±0.1V). Using a jumper on connector X21 (below the 5V power supply jack), the DDR power supplycan be changed to suit the needs of DDR400 modules.
Note: If you want to use the DDR SDRAM interface with a 16-bit data bus, provide your HDL design with an addi-tional input port that is assigned to pin P9 of bank 6 (connected to schematic net DDR_VREF).
Do not use this signal in your design. Deactivate the internal pull-up of the pin in the ispLEVER software. It safe-guards the DDR RAM memory from getting an incorrect supply voltage which will happen when the pin is unusedat a data bus width of 16 bits.
When using a 32-bit data bus, you do not have to assign this pin—ispLEVER will take care of it automatically.
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
6 AC97_BITCLK B24 47 AC97_EAPD C23
2 AC97_EXT_CLK D25 11 AC97_RESET# B25
8 AC97_SDATA_IN C26 5 AC97_SDATA_OUT C25
10 AC97_SYNC D24
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Table 3. DDR SODIMM Socket (X4) - Data Bus
Table 4. DDR SODIMM Socket (X4) - Address Bus
Table 5. DDR SODIMM Socket (X4) - Other Signals
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
11 DDR_DQS0 AE6 47 DDR_DQS2 AB3
12 DDR_DM0 AF6 48 DDR_DM2 AB2
5 DDR_DQ0 AD9 41 DDR_DQ16 AE2
7 DDR_DQ1 AD4 43 DDR_DQ17 AD1
13 DDR_DQ2 Y5 49 DDR_DQ18 AD2
17 DDR_DQ3 AD8 53 DDR_DQ19 AD3
6 DDR_DQ4 AC8 42 DDR_DQ20 AC1
8 DDR_DQ5 AB8 44 DDR_DQ21 AC2
14 DDR_DQ6 AF7 50 DDR_DQ22 Y5
18 DDR_DQ7 AE7 54 DDR_DQ23 Y6
25 DDR_DQS1 AA6 61 DDR_DQS3 T1
26 DDR_DM1 AB6 62 DDR_DM3 T2
19 DDR_DQ8 AF5 55 DDR_DQ24 V1
23 DDR_DQ9 AE5 59 DDR_DQ25 U1
29 DDR_DQ10 AD5 65 DDR_DQ26 P4
31 DDR_DQ11 AC5 67 DDR_DQ27 P5
20 DDR_DQ12 AF4 56 DDR_DQ28 P6
24 DDR_DQ13 AE4 60 DDR_DQ29 N3
30 DDR_DQ14 AD4 66 DDR_DQ30 N4
32 DDR_DQ15 AC4 68 DDR_DQ31 N5
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
112 DDR_A0 AD10 111 DDR_A1 AD14
110 DDR_A2 AB12 109 DDR_A3 AC12
108 DDR_A4 AD12 107 DDR_A5 AB13
106 DDR_A6 AC13 105 DDR_A7 AD13
102 DDR_A8 AB15 101 DDR_A9 AB14
115 DDR_A10 AC10 100 DDR_A11 AC14
99 DDR_A12 AD14 123 DDR_A13 AB10
117 DDR_BA0 AD7 116 DDR_BA1 AC7
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
35 DDR_CK0+ AE12 37 DDR_CK0- AF12
160 DDR_CK1+ Y1 158 DDR_CK1- AA2
96 DDR_CKE0 AF11 95 DDR_CKE1 AF10
118 DDR_RAS# AE9 119 DDR_WE# AE10
120 DDR_CAS# AF9 121 DDR_S0# AF8
122 DDR_S1# AE8
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Ethernet Interface
An Intel LXT971A is included for Ethernet PHY. This is an IEEE-compliant Fast Ethernet PHY Transceiver thatdirectly supports both 100BASE-TX and 10BASE-T applications, full and half duplex. For more information, pleaserefer to the data sheet of this component.
Each board has its own unique MAC address so that no conflicts with other components in the network will occur.Specify this MAC address for synthesis of Ethernet designs. It can be found on the sticker at the bottom side ofyour board.
Table 6. Ethernet Controller U0801 Pin Definition
Expansion Connector
The expansion connector provides 46 user I/Os connected to the FPGA. The remaining pins serve as power andclock supplies for expansion boards. The expansion connector is configured as two 2x20 100mil centered pin head-ers (X12 and X13). Tables 7 and 8 describe the connections to the FPGA.
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
4 HPE_RESOUT# AE24 42 ETH_MDIO N25
43 ETH_MDC M26 45 ETH_RXD3 W25
46 ETH_RXD2 W26 47 ETH_RXD1 Y26
48 ETH_RXD0 AA26 49 ETH_RXDV R25
52 ETH_RXCLK L26 53 ETH_RXER P26
54 ETH_TXER U26 55 ETH_TXEN R26
56 ETH_TXCLK L25 57 ETH_TXD0 V26
58 ETH_TXD1 V25 59 ETH_TXD2 V24
60 ETH_TXD3 V23 62 ETH_COL P25
63 ETH_CRS N26 64 ETH_MDINTR# W24
Table 7. Expansion Connector X13
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
1 GND — 2 NC (coding) —
3 VCC2V5 — 4 EXPCON_IO29 H4
5 EXPCON_IO30 H5 6 EXPCON_IO31 H6
7 EXPCON_IO32 H7 8 EXPCON_IO33 H8
9 EXPCON_IO34 G1 10 EXPCON_IO35 G2
11 EXPCON_IO36 G3 12 EXPCON_IO37 G4
13 EXPCON_IO38 F1 14 EXPCON_IO39 F2
15 EXPCON_IO40 F5 16 EXPCON_IO41 F6
17 EXPCON_IO42 E1 18 EXPCON_IO43 E2
19 EXPCON_IO44 E3 20 EXPCON_IO45 E4
21 VCC5V0 — 22 GND —
23 VCC2V5 — 24 GND —
25 VCC3V3 — 26 GND —
27 VCC3V3 — 28 GND —
29 EXPCON_OSC — 30 GND —
31 EXPCON_CLKIN — 32 GND —
33 EXPCON_CLKOUT — 34 GND —
35 VCC3V3 — 36 GND —
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Table 8. Expansion Connector X14
ispDOWNLOAD Cable Connector
There are two ways to configure the programmable Lattice devices on the board. The USB connector requires astandard USB cable, and is described later in this document. Connector X3 is available to connect a Lattice isp-DOWNLOAD cable. An ispDOWNLOAD cable is used to program IEEE 1532 compliant programmable devices.Lattice provides either a parallel port or a USB port download cable. The FPGA and CPLD are programmed usingthe cable and ispVM
®
programming software.
Important Note:
The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAGpins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device and render theboard inoperable.
DIP switch SW0302
1
controls the device to be configured: the FPGA or the MachXO. If it is on (in top position), theMachXO is selected; if off, the FPGA is selected.
The ispVM System software can be downloaded from the Lattice web site at: www.latticesemi.com/ispvm.
Note: Do not change the switch when the configuration of a device is in progress!
37 VCC3V3 — 38 GND —
39 VCC3V3 — 40 GND —
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
1 HPE_RESET# — 2 GND —
3 EXPCON_IO0 R1 4 EXPCON_IO1 R2
5 EXPCON_IO2 P1 6 EXPCON_IO3 P2
7 EXPCON_IO4 N1 8 EXPCON_IO5 M6
9 EXPCON_IO6 L2 10 EXPCON_IO7 L5
11 EXPCON_IO8 L6 12 EXPCON_IO9 L7
13 EXPCON_IO10 L8 14 EXPCON_IO11 K1
15 EXPCON_IO12 K2 16 EXPCON_IO13 K3
17 EXPCON_IO14 K4 18 EXPCON_IO15 K5
19 GND — 20 VCC3V3 —
21 EXPCON_IO16 K6 22 GND —
23 EXPCON_IO17 K7 24 GND —
25 EXPCON_IO18 K8 26 GND —
27 EXPCON_IO19 J1 28 EXPCON_IO20 J2
29 EXPCON_IO21 J3 30 GND —
31 EXPCON_IO22 J4 32 EXPCON_IO23 J5
33 EXPCON_IO24 J8 34 GND —
35 EXPCON_IO25 J9 36 EXPCON_IO26 H1
37 EXPCON_IO27 H2 38 CARDSEL# D1
39 EXPCON_IO28 H3 40 GND —
1. Caption on the board: CONF.
Table 7. Expansion Connector X13 (Continued)
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Note: The board as configured from the factory, has a built-in USB ispDOWNLOAD cable. The built-in cable and anexternal ispDOWNLOAD cable cannot be used at the same time. Doing so may damage the board.
Table 9. ispDOWNLOAD Connector X4 Pin Definition
LCD Connector (Optional)
The LCD connector is a 16-pin header with a standard pinning for LCD modules with back-light (e.g. Truly MTC-C202DPRN-1N). In order to use an LCD module, attach it to the connector via a 16-pin ribbon cable.
Note: The LCD module is tied to a 5V supply. The LatticeECP2-50 to LCD interface is 3.3V.
Put a jumper on connector X6 to turn on the backlight of the LCD. The contrast of the LCD module is adjustablewith the potentiometer R0526, because different LCD modules need different voltages for the best contrast.
Figure 3. LCD Panel (Not Included)
Table 10. LCD Connector X6 Pin Definition
SATA Interfaces
Find the jacks X15 and X16 for connecting SATA cables on the right side of the board. This provides a convenientmethod for evaluating or using LVDS signals with the FPGA. This board does not support implementation of a fullSATA solution. These SATA jacks have differential nets with high-speed signals connected to them. See Table 11for SATA pinning information. The positive signal is connected with a plus (+), the negative with a minus (-). Everydifferential signal pair can act as receiver or transmitter depending on the configuration of the FPGA.
Pin Signal Name Pin Signal Name
1 VCC3V3 2 JTAG_TDO
3 JTAG_TDI 4 JTAG_PROG
5 JTAG_TRST 6 JTAG_TMS
7 GND 8 JTAG_TCK
9 JTAG_DONE 10 JTAG_INIT
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
1 GND — 2 VCC5V —
3 CONTRAST — 4 LCD_REGSEL K24
5 LCD_RW J24 6 LCD_ENABLE J22
7 SEG_A# M24 8 SEG_B# N23
9 SEG_C# M22 10 SEG_D# M21
11 SEG_E# M20 12 SEG_F# L22
13 SEG_G# L21 14 SEG_DP# K22
15 BACKLIGHT — 16 GND —
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Table 11. SATA Jacks X15 (Left Column) and X16 (Right Column) Pin Definition
Serial Interface
The board includes an RS232 serial interface port. The interface provides transmit (TX), receive (RX), and hard-ware handshaking. The Maxim MAX3232 data sheet provides detailed information on the interface circuit. A 9-pinfemale to 9-pin female null modem cable is required.
Table 12. Serial Interface X9 Pin Definition
Sigma Delta D/A Converter
The board includes a low-pass filter connected to a dedicated pin (C14) of the FPGA. With this, a sigma delta con-verter can be realized. Great results can be achieved by using a resolution of 8 to 10 bits. Example VHDL code isprovided.
Power Supply
Four different voltages are needed: 3.3V I/O voltage, 2.5V DDR and LVDS voltages as well as 1.2V core voltage.The 3.3V supply draws up to 1A, the 2.5V and 1.2V supplies up to 2A of current.
For more information, see the power supply information in the Components section of this document.
Test Points
In order to check the various voltage levels used, several test points are provided. There is one test point for 1.2V,2.5V, 3.3V, one for ground, and one for accessing the 25MHz oscillator. The 25MHz clock signal can be checkedwith another test point.
USB Host/Peripheral Interface
There are one mini USB OTG and two USB host connectors on board. These are connected to the CypressCY7C67300 USB Host/Peripheral Controller U0702. This controller is compliant with the Universal Serial BusSpecification 2.0. You can transmit and receive serial data at both full-speed (12 Mbps) and low-speed (1.5 Mbps)data rates. For more information, please refer to the data sheet of the USB controller. U0703 and U0704 are USBpower control switches, which must be enabled by the user via the USB PWEN signals. The USB OC signal pullslow to indicate voltage, current and thermal issues.
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
2 SATA_X1D0+ M4 2 SATA_X2D0+ U3
3 SATA_X1D0- M5 3 SATA_X2D0- U4
5 SATA_X1D1+ P3 5 SATA_X2D1+ V2
6 SATA_X1D1- R3 6 SATA_X2D1- W2
Sub-D Pin Signal FPGA Pin Direction RS232 Function
3 RS_TXD_LVTTL K26 Out Transmit Data
7 RS_RTS_LVTTL K25 Out Request to Send
2 RS_RXD_LVTTL J25 In Receive Data
8 RS_CTS_LVTTL J26 In Clear to Send
Table 13. USB GPIO Connections (U0702)
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
94 USB_GPIO0 AE20 93 USB_GPIO1 AC18
92 USB_GPIO2 AE13 91 USB_GPIO3 AB20
90 USB_GPIO4 AA20 89 USB_GPIO5 AF19
87 USB_GPIO6 AE19 86 USB_GPIO7 AD19
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Table 14. Additional USB GPIO Connections (U0702, U0704, and U0704)
USB Configuration Connector
In addition to the ispDOWNLOAD connector, the FPGA and the MachXO can also be configured by a standardUSB connection. The USB target connector is wired to the Cypress CY7C68013A device (U0301).
This programming method requires the use of the ispVM System software. This can be downloaded from the Lat-tice web site at: www.latticesemi.com/ispvm.
This connection will appear to the ispVM System software as if a regular USB-based ispDOWNLOAD cable is con-nected to the PC.
The CY7C68013A in combination with the MachXO CPLD acts as a built-in ispDOWNLOAD cable. The MachXO isconnected to the ispDOWNLOAD Connector X3, and can program the LatticeECP2-50. The LatticeECP2-50 canbe programmed when DIP switch SW0302 is ‘off’ (pushed down).
Note: Like the ispDOWNLOAD connector, the MachXO drives the JTAG signals when it is programmed for USBconfiguration. Only use the built-in ispDOWNLOAD cable or an external ispDOWNLOAD cable exclusively. It is notrecommended to switch between cables without first power cycling the board. Failure to follow this recommenda-tion may cause unpredictable results and may possibly damage the board.
66 USB_GPIO8 AC19 65 USB_GPIO9 AB19
61 USB_GPIO10 AA19 60 USB_GPIO11 AF18
59 USB_GPIO12 AE18 58 USB_GPIO13 AD18
57 USB_GPIO14 AC18 56 USB_GPIO15 AB18
55 USB_GPIO16 AF17 54 USB_GPIO17 AE17
53 USB_GPIO18 AD17 52 USB_GPIO19 AC17
50 USB_GPIO20 AB17 49 USB_GPIO21 AF16
48 USB_GPIO22 AE16 47 USB_GPIO23 AF15
46 USB_GPIO24 AE15 45 USB_GPIO25 AF14
44 USB_GPIO26 AE14 43 USB_GPIO27 AF13
42 USB_GPIO28 AE13 41 USB_GPIO29 -
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
U0703:1 USB_PWEN0 Y17 U0703:2 USB_OC0# AA16
U0703:4 USB_PWEN1 Y16 U0703:3 USB_OC1# Y20
U0704:1 USB_PWEN2 AA21 U0704:2 USB_OC2# Y19
U0702:85 HPE_RESOUT# AE24
Table 15. Connections Between the USB Controller (CY7C68013A) and the MachXO
Cypress Pin Signal Name MachXO Pin Cypress Pin Signal Name MachXO Pin
34 GP_D0 G14 35 GP_D1 N14
36 GP_D2 H14 37 GP_D3 H13
44 GP_D4 H12 45 GP_D5 J13
46 GP_D6 J12 47 GP_D7 K14
80 GP_D8 K13 81 GP_D9 K12
82 GP_D10 L14 83 GP_D11 M13
95 GP_D12 M14 96 GP_D13 M12
Table 13. USB GPIO Connections (U0702) (Continued)
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
VGA Interface
The board includes a VGA connector for driving a VGA monitor. The VGA interface is connected to a 15-pin plugsocket. The pin definitions are listed in Table 16.
VGA RD0 and VGA RD1 are both connected to pin 1, but have different series resistors (see Figure 4). Thus, a 6-bit VGA interface is realized. Figure 4 shows the connection of the RGB signals. The FPGA is responsible for gen-erating correct HSYNC and VSYNC sweep frequencies. Understand the SYNC frequencies of the VGA monitorbeing connected to the VGA plug and adjust the FPGA frequencies as required.
Table 16. VGA Connector X1B Pin Definition, n.c. ... Not Connected
97 GP_D14 N14 98 GP_D15 N13
57 GP_ADR0 H1 58 GP_ADR1 H2
59 GP_ADR2 J1 60 GP_ADR3 J3
61 GP_ADR4 K1 62 GP_ADR5 K2
63 GP_ADR6 L1 64 GP_ADR7 L3
93 GP_ADR8 M1 69 GP_SLOE M3
67 GP_INT0 N7 68 GP_INT1 M6
71 GP_FIFOADR0 M4 72 GP_FIFOADR1 N4
70 GP_WU2 N3 73 GP_PKTEND P5
74 GP_SLCS# G3 79 USBCF_WAKE N9
3 GP_RDY0 D3 4 GP_RDY1 E2
5 GP_RDY2 F2 6 GP_RDY3 F3
7 GP_RDY4 G1 8 GP_RDY5 G2
54 GP_CTL0 D1 55 GP_CTL1 C3
56 GP_CTL2 C2 51 GP_CTL3 C1
52 GP_CTL4 B2 76 GP_CTL5 B1
23 GP_T0 M2 24 GP_T1 N1
25 GP_T2 P1 28 GP_BKPT F12
100 USB_CLK_O M7 26 GP_IFCLK M8
41 GP_RXD0 E13 40 GP_TXD0 E14
43 GP_RXD1 F13 42 GP_TXD1 F14
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
1 VGA_RD0 AF24 1 VGA_RD1 AE23
2 VGA_GR0 AF23 2 VGA_GR1 AE22
3 VGA_BL0 AF22 3 VGA_BL1 AE21
4 n.c. — 5 n.c. —
6 GND — 7 GND —
8 GND — 9 n.c. —
10 GND — 11 n.c. —
12 n.c. — 13 VGA_HSYNC AF20
14 VGA_VSYNC AF21 15 n.c. —
Table 15. Connections Between the USB Controller (CY7C68013A) and the MachXO (Continued)
Cypress Pin Signal Name MachXO Pin Cypress Pin Signal Name MachXO Pin
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 4. VGA Connector
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
User Interface
Figure 5 shows the position of the user interface elements.
Figure 5. User Interface Features (Version 1 Board Shown in this Figure)
AudioLine In
Line Out
Mini USBOTG Connector
VGAConnector
Power Plug Ethernet10/100M
RS232 Connector
DDR SDRAMSockel
SATA LVDSConnectors
2.5 VTestpoint
3.3 VTestpoint
GNDTestpoint
1.2 VTestpoint
CLKTestpoint
FlywireConnector
High-Speed USB for
Configuration
LCD Connector
Sigma DeltaDAC Connector
ExpansionConnector
USB HostConnector
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
7-Segment Display
The 7-segment display is wired as follows:
Table 17. 7-Segment Display U0502 Pin Definition
The signals of the 7-segment display are low-active, which means that with a logic ‘0’, the segment is lit. SEG A# ...SEG F# and SEG DP# drive not only the two 7-segment displays, but also the LCD. To write different data to thesethree components, the user must drive the signals alternately to the components. This can be realized with the sig-nals SEG CA0#, SEG CA1# and LCD ENABLE. They serve to activate the two 7-segment displays and the LCD,respectively.
DIP Switches
There is a 4-bit DIP switch on the board. When the switch is turned to the on position, a logic ‘1’ will be seen. Theconnections are in Table 18.
Table 18. DIP Switches SW0514 Connection
LEDs
Eight LEDs can be used for custom status signaling. They are low-active; with a logic ‘0’ the LED is on. You cancontrol the LEDs via the signals below.
Table 19. LED LD0501 ... LD0508 Connection
Key Matrix
The board also features a key matrix with 12 push-buttons, which are not debounced. They must be driven withthree column lines and can be read with four rows. The following table shows the connections.
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
A SEG_A# M24 E SEG_E# M20
B SEG_B# N23 F SEG_F# L22
C SEG_C# M22 G SEG_G# L21
D SEG_D# M21 DP SEG_DP# K22
right SEG_CA0# K21 left SEG_CA1# K20
Switch Signal Name FPGA Pin Switch Signal Name FPGA Pin
SW315 SW316
1 DSW0 F26 2 DSW1 F25
3 DSW2 E26 4 DSW3 E25
Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
1 LED0# R24 5 LED4# P23
2 LED1# R23 6 LED5# P22
3 LED2# R22 7 LED6# P21
4 LED3# R21 8 LED7# N22
A
B
C
D
E
F G
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Table 20. Key Matrix with the Keys SW302 ... SW313 Definition
Table 21. Key Matrix with the Keys SW302 ... SW313 Connection
To query all keys of the matrix, you must poll the column driver signals (TST COL0, TST COL1, and TST COL2). Ifyou press a key, a logic ‘1’ appears in the corresponding row. The following diagram explains the functionality:
Figure 6. Polling of the Key Matrix
You do not need the polling method if only four keys are used. Connect the column driver signals of one column toVCC, the other two to GND and query the row data signals.
CPU Reset Key
The CPU reset key is a global reset. Please refer to the Reset Chip section of this document for detailed informa-tion.
Single Step Key
The single step key is connected to a normal input of the FPGA and can be used by the application as required.This key is connected to a Schmitt trigger, meaning it is debounced. This key can be used as a single clock for test-ing your design.
Signal Name TST_COL0 TST_COL1 TST_COL2
TST_ROW0 1 2 3
TST_ROW1 4 5 6
TST_ROW2 7 8 9
TST_ROW3 C 0 E
Signal Name FPGA Pin Signal Name FPGA Pin
TST_ROW0 H26 TST_COL0 G26
TST_ROW1 H25 TST_COL1 G25
TST_ROW2 H24 TST_COL2 G24
TST_ROW3 H23
Col0
Col1
Col2
Row0
Row1
1 pressed 3 pressed
6 pressed6 pressed
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
ComponentsFigure 7 illustrates the position of major components.
Figure 7. Components (Version 1 board Shown in this Figure)
USB Host/Target/OTGController
AC‘97 Audio Codec
EthernetPHY
CPLDMachXO
USB Configuration
Controller
SPIFlash
ParallelFlash
AsynchronousSRAM
ResetController
Prototyping Area
FPGALFEC250
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
12 x 12 FPGA Prototyping Area of The FPGAA 12x12 prototyping area is available. The lead-wire spacing of the prototyping area is 100mil (2.54 mm). Figure 8shows the prototyping area in top view. 14 plated-through-holes on its left side are connected to the FPGA. Eightthrough-holes on the right side are wired to a 2.5V I/O bank. In the top row of the prototyping area there are sixconnections to the 3.3V power supply as well as three to 2.5V. The bottom row has ten plated-through-holes con-nected to GND.
Table 22. FPGA Connections for the 12x12 Prototyping Area
LRF Pin Signal Name FPGA Pin LRF Pin Signal Name FPGA Pin
TP0901 BB3V3_IO0 A15 TP0902 BB3V3_IO1 B15
TP0903 BB3V3_IO2 C15 TP0904 BB3V3_IO3 D15
TP0905 BB3V3_IO4 A16 TP0906 BB3V3_IO5 B16
TP0907 BB3V3_IO6 E16 TP0908 BB3V3_IO7 A17
TP0909 BB3V3_IO8 B17 TP0910 BB3V3_IO9 C17
TP0911 BB3V3_IO10 D17 TP0912 BB3V3_IO11 E17
TP09133 BB3V3_IO12 A18 TP09134 BB3V3_IO13 B18
TP09135 BB3V3_IO14 C18 TP09136 BB3V3_IO15 D18
TP09137 BB3V3_IO16 E18 TP09138 BB3V3_IO17 A19
TP09139 BB3V3_IO18 B19 TP09140 BB3V3_IO19 C19
TP09141 BB3V3_IO20 D19 TP09142 BB3V3_IO21 E19
TP09143 BB3V3_CLK0+ D14 TP09144 BB3V3_CLK0- F14
TP0913 VCC3V3 — TP0925 VCC3V3 —
TP0937 VCC3V3 — TP0949 VCC3V3 —
TP0961 VCC3V3 — TP0973 VCC3V3 —
TP0985 VCC3V3 — TP0997 VCC3V3 —
TP09109 VCC3V3 — TP09121 VCC3V3 —
TP0924 GND — TP0936 GND —
TP0948 GND — TP0960 GND —
TP0972 GND — TP0984 GND —
TP0996 GND — TP09108 GND —
TP09120 GND — TP09132 GND —
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 8. Schematic Illustration of the Prototyping Area
Asynchronous SRAMThe board is populated with two asynchronous K6R4016V1D SRAMs from Samsung. Each is 4 Mbit in size with adata bus width of 16 bits. They are wired as one memory with a 32-bit data bus and a depth of 256 k. The 18-bitaddress bus, the data bus and the control signals are connected directly to the FPGA. The 18-bit address bus,named MEMORY_A0 through MEMORY_A17, addresses word (4 bytes) locations.
Table 23. Address Signals of the Asynchronous SRAM Chips U0404 and U0405
SRAM Pin Signal Name FPGA Pin SRAM Pin Signal Name FPGA Pin
1 MEMORY_A0 C1 2 MEMORY_A1 B2
3 MEMORY_A2 C2 4 MEMORY_A3 A3
5 MEMORY_A4 B3 18 MEMORY_A5 C3
19 MEMORY_A6 D3 20 MEMORY_A7 A4
21 MEMORY_A8 B4 22 MEMORY_A9 C4
23 MEMORY_A10 D4 24 MEMORY_A11 A5
25 MEMORY_A12 B5 26 MEMORY_A13 C5
27 MEMORY_A14 D5 42 MEMORY_A15 E5
43 MEMORY_A16 A6 44 MEMORY_A17 B6
BB3V3_IO[21:0]
BB3V3_IO3
BB3V3_IO2
BB3V3_IO1
BB3V3_IO0
BB3V3_IO4
BB3V3_IO5
BB3V3_IO6
BB3V3_IO7
BB3V3_IO8
BB3V3_IO9
BB3V3_IO10
BB3V3_IO11
BB3V3_IO12
BB3V3_IO[21:0]
BB3V3_IO13
BB3V3_IO14
BB3V3_IO15
BB3V3_IO16
BB3V3_IO17
BB3V3_IO18
BB3V3_IO19
BB3V3_IO20
BB3V3_IO21
BB3V3_CLK0-
BB3V3_CLK0+
VCC3V3
GND
DIFF
TP09104
TP0935
TP0996TP0912
TP0963
TP09124
TP0954
TP09117
TP0944TP0908
TP09106
TP0936
TP0921
TP0964
TP0986
TP09125
TP0957
TP09115
TP0946
TP09107
TP09135
TP0926
TP0965
TP0985
TP09126
TP0955
TP0920 TP09116
TP0947
TP09108
TP0909
TP0975
TP09136
TP0925
TP0966
TP09129
TP0934
TP0956
TP09118
TP0948
TP0976
TP0998
TP09137
TP0969
TP0922
TP09127
TP0958
TP0903
TP09119
TP0938
TP0977
TP09133
TP0910
TP09138
TP0967
TP09128
TP0901
TP0959
TP0987
TP09120
TP0937
TP0923
TP0978
TP09141
TP0968
TP09130
TP0927
TP0960
TP0904 TP0988
TP09110
TP0981
TP0911
TP09139
TP0970
TP0924
TP09131
TP0928
TP0950
TP09121
TP0915
TP0989
TP0979
TP09140
TP0971
TP0999
TP09132
TP0929
TP0949
TP0990
TP0980
TP0914
TP09142
TP0939
TP0972
TP0916 TP09100
TP0905
TP09122
TP0930
TP0993
TP0982
TP09143
TP0940
TP0962
TP09109
TP09101
TP0933
TP0913
TP0991
TP0917
TP0983
TP0902
TP09111
TP09144
TP0941
TP0961
TP09102TP0906
TP0931
TP0992
TP0984
TP0951
TP09112
TP09134
TP0942
TP09105
TP0918
TP0932
TP0994
TP0952
TP0974
TP0997
TP09113
TP0945
TP09103TP0907
TP0995
TP09123
TP0953
TP0919
TP0973
TP09114
TP0943
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Table 24. Data Signals of the Asynchronous SRAM Chip U0404
Table 25. Data Signals of the Asynchronous SRAM Chip U0405
Table 26. Control Signals of the Asynchronous SRAM Chips U0404 and U0405
MachXOThe LCMXO640 is a non-volatile, instant-on, reprogrammable logic device. It supports “background programming”called TransFR™ (i.e., the device can be programmed while in operation).
The MachXO comes preprogrammed from the factory. The factory program permits the CY7C68013A/MachXOcombination to work as a built-in USB ispDOWNLOAD cable. Using ispVM software the built-in download cablepermits the FPGA, and SPI PROM, to be programmed. It is not recommended for the MachXO to be repro-grammed. However, the MachXO does provide some connections to the LatticeECP2-50 FPGA, and to an 8x6 pro-totyping area.
For further information, please consult the MachXO Family Data Sheet.
SRAM Pin Signal Name FPGA Pin SRAM Pin Signal Name FPGA Pin
7 MEMORY_DQ0 E7 8 MEMORY_DQ1 F7
9 MEMORY_DQ2 G7 10 MEMORY_DQ3 A8
13 MEMORY_DQ4 B8 14 MEMORY_DQ5 C8
15 MEMORY_DQ6 D8 16 MEMORY_DQ7 E8
29 MEMORY_DQ8 F8 30 MEMORY_DQ9 G8
31 MEMORY_DQ10 A9 32 MEMORY_DQ11 B9
35 MEMORY_DQ12 C9 36 MEMORY_DQ13 D9
37 MEMORY_DQ14 E9 38 MEMORY_DQ15 A10
SRAM Pin Signal Name FPGA Pin SRAM Pin Signal Name FPGA Pin
7 MEMORY_DQ16 B10 8 MEMORY_DQ17 C10
9 MEMORY_DQ18 D10 10 MEMORY_DQ19 E10
13 MEMORY_DQ20 F10 14 MEMORY_DQ21 G10
15 MEMORY_DQ22 A11 16 MEMORY_DQ23 B11
29 MEMORY_DQ24 E11 30 MEMORY_DQ25 F11
31 MEMORY_DQ26 G11 32 MEMORY_DQ27 C12
35 MEMORY_DQ28 D12 36 MEMORY_DQ29 E12
37 MEMORY_DQ30 F12 38 MEMORY_DQ31 G12
SRAM Pin Signal Name FPGA Pin SRAM Pin Signal Name FPGA Pin
SRAM Pin Signal Name FPGA Pin
17 MEMORY_WE# C13 41 MEMORY_OE# D13
39 SRAM_BE0# F13 40 SRAM_BE1# G13
6 SRAM_CE# E13
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Table 27. Interface Between the MachXO and the FPGA
FPGAThe LatticeECP2-50 FPGA represents the heart of the board. It has the following features:
• 48 k Look-Up Tables (LUTs)
• 96 kbit of distributed RAM
• 387 kbit of EBR SRAM
• 21 EBR SRAM blocks
• 18 sysDSP blocks
• 72 18 x 18 multipliers
• 6 PLLs: 2 GPLLs, 2 SPLLs, 2 GDLLs
• 500 user I/Os
• DDR memory support (DDR1-400, DDR2-400)
• Supported I/O standards: LVCMOS, LVTTL, SSTL, HSTL, LVDS, PCI, differential
• HSTL, differential SSTL, RSDS, Bus LVDS, MLVDS, LVPECL
The ispLEVER design software can be used to develop/modify programs for the FPGA using Verilog or VHDLdesign entry methods. For more information on the ispLEVER software, see www.latticesemi.com/software.
Sample programs for the FPGA are available on-line as well. These can be found at www.latticesemi.com/boards.Select FPGA/FPSC Boards -> LatticeMico32/DSP Development board for LatticeECP2 and click on theDesign Files link.
For further information please consult the LatticeECP2/M Family Data Sheet.
Parallel FlashTwo parallel MX29LV128MBTI-90Q Flash components from Macronics (or equivalents) are provided on the boardfor program code and data. As with the SRAM, a 32-bit data bus is realized with these two devices. Thus, Flash canbe accessed as a 8Mx32 memory. The 23-bit address bus, the data bus and the control signals are connecteddirectly to the FPGA. The 23-bit address bus, named MEMORY_A0 through MEMORY_A22, addresses word (4bytes) locations.
CPLD Pin Signal Name FPGA Pin CPLD Pin Signal Name FPGA Pin
A1 MACHXO_IO0 A20 A2 MACHXO_IO1 A23
A3 MACHXO_IO2 C20 B3 MACHXO_IO3 D20
A4 MACHXO_IO4 E20 C4 MACHXO_IO5 A21
A5 MACHXO_IO6 B21 B5 MACHXO_IO7 E21
A6 MACHXO_IO8 A22 B6 MACHXO_IO9 B22
B10 MACHXO_IO10 C22 A11 MACHXO_IO11 D22
A12 MACHXO_IO12 A23 B12 MACHXO_IO13 B23
A13 MACHXO_IO14 E23 A14 MACHXO_IO15 A24
C8 MACHXO_CLK0 H13 B8 MACHXO_CLK0 H13
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Note: The LatticeMico32/DSD Development Board generates byte enable outputs at the top-level HDL module. Theboard does not use these outputs, which causes ispLEVER to generate some warning messages. The warningscorrectly tell the user that these pins are not connected or assigned to any location. The warnings can be avoidedby either commenting out these byte enable outputs, or assigning them to unused I/O.
Table 28. Address Signals of the Flash Chips U0402 and U0403
Table 29. Data Signals of the Flash Chip U0402
Table 30. Data Signals of the Flash Chip U0403
Flash Pin Signal Name FPGA Pin Flash Pin Signal Name FPGA Pin
31 MEMORY_A0 C1 26 MEMORY_A1 B2
25 MEMORY_A2 C2 24 MEMORY_A3 A3
23 MEMORY_A4 B3 22 MEMORY_A5 C3
21 MEMORY_A6 D3 20 MEMORY_A7 A4
10 MEMORY_A8 B4 9 MEMORY_A9 C4
8 MEMORY_A10 D4 7 MEMORY_A11 A5
6 MEMORY_A12 B5 5 MEMORY_A13 C5
4 MEMORY_A14 D5 3 MEMORY_A15 E5
54 MEMORY_A16 A6 19 MEMORY_A17 B6
18 MEMORY_A18 E6 11 MEMORY_A19 A7
12 MEMORY_A20 B7 15 MEMORY_A21 C7
2 MEMORY_A22 D7
Flash Pin Signal Name FPGA Pin Flash Pin Signal Name FPGA Pin
35 MEMORY_DQ0 E7 37 MEMORY_DQ1 C9
39 MEMORY_DQ2 A11 41 MEMORY_DQ3 F12
44 MEMORY_DQ4 B8 46 MEMORY_DQ5 C8
48 MEMORY_DQ6 D8 50 MEMORY_DQ7 E8
36 MEMORY_DQ8 F8 38 MEMORY_DQ9 G8
40 MEMORY_DQ10 A9 42 MEMORY_DQ11 B9
45 MEMORY_DQ12 C9 47 MEMORY_DQ13 D9
49 MEMORY_DQ14 E9 51 MEMORY_DQ15 A10
Flash Pin Signal Name FPGA Pin Flash Pin Signal Name FPGA Pin
35 MEMORY_DQ16 B10 37 MEMORY_DQ17 C10
39 MEMORY_DQ18 D10 41 MEMORY_DQ19 E10
44 MEMORY_DQ20 F10 46 MEMORY_DQ21 G10
48 MEMORY_DQ22 A11 50 MEMORY_DQ23 B11
36 MEMORY_DQ24 E11 38 MEMORY_DQ25 F11
40 MEMORY_DQ26 G11 42 MEMORY_DQ27 C12
45 MEMORY_DQ28 D12 47 MEMORY_DQ29 E12
49 MEMORY_DQ30 F12 51 MEMORY_DQ31 G12
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Table 31. Control Signals of the Flash Chips U0402 and U0403
SPI FlashThe LatticeECP2-50 FPGA is an SRAM-based programmable device, and is therefore volatile. In order for it to beautomatically configured upon power-up, a non-volatile 16 Mbit SPI Flash device is provided. The SPI Flash can beprogrammed with configuration bitstream data. The SPI Flash can be configured either through the ispDOWN-LOAD connector or via the integrated USB configuration interface.
Table 32. Title?
To program the SPI Flash configuration device, use the FPGA Loader function of the ispVM System software. TheFPGA Loader programming scheme provides an in-system JTAG programming method for configuration devices.The FPGA acts as a bridge between the JTAG interface and the SPI interface of the serial configuration device.
Configure the SPI Flash as follows:
1. In the ispVM System software, choose Edit -> Add Device to open the Device Information dialog box.
2. Click Select to open the Select Device dialog box. Select device family LatticeECP2, device LFE2-50E, and package 672 fpBGA from the drop-down lists.
3. Change the Device Access Options to SPI Flash Programming.
4. Select Flash Device : STMicro SPI-M25P16 and click OK.
5. Browse Data File: Select the ECP2-50 bitstream to program into the SPI PROM, click OK.
6. Click OK to close the SPI Serial Flash Device dialog.
7. Click OK to close the Device Information dialog
8. Click GO. The ispVM System software programs the SPI Flash via the FPGA.
9. Disconnect and then reconnect the power supply. The FPGA will take about three seconds to be programmed by the SPI Flash.
Power SupplyPower is supplied via a 2.1 mm DC power jack in the top left corner of the board. The board is protected againstreversed power supply. The input supply is 5V DC.
Flash Pin Signal Name FPGA Pin Flash Pin Signal Name FPGA Pin
34 MEMORY_OE# D13 13 MEMORY_WE# C13
32 FLASH_CE# A13 16 FLASH_WP#/ACC A12
14 FLASH_RESET B14 17 FLASH_RY/BY#_A A14
53 FLASH_BYTE# B12
SPI Pin Signal Name FPGA Port Name FPGA Direction FPGA Pin
CS CSSPIN CEJ Output V22
CLK CCLK SCK Output NC/E19
Q SPIDO SO Input W23
DI SISPI SI Output Y25
WPn WP# WPJ Output AA25 (FPGA NC)
HOLDn HOLD# HOLDJ Output SB26 (FPGA NC)
Note: The SPI CLK pin can be connected to FPGA E19. This allows the LatticeMico32 to access the SPI PROM for data retrieval/storage purposes.
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
A two-phase synchronous step-down switching regulator generates the 3.3V (1A max.) I/O voltage and the 1.2V(2A max.) core voltage.
Note: If you use a power supply other than the one included in the shipment, make sure it supplies regulated 5V.
Reset ChipAfter power-up, a power surveillance chip (U0601) waits until the 5V supply and the 3.3V I/O voltage are stable.Then, after 200 ms, it drives the signal HPE RESET# (pin M25 of the FPGA) high. If you press the reset button, thesupervisory circuit will generate a low on the HPE RESET# signal.
The surveillance chip has an I2C serial 2 kbit CMOS EEPROM. The four most significant bits of the 8-bit slaveaddress are programmable; the default being 1010. Detailed information on the reset circuit and the I2C interfacecan be found in the data sheet of the Catalyst Semiconductor CAT1026.
TroubleshootingIf your board is not working properly, please follow these steps for diagnosis.
1. Check the 3.3V and 2.5V LEDs to ensure that the power supply is working correctly.
2. Make sure that the INIT LED is lit.
3. Load test program.
4. Make sure the FPGA has been configured properly (DONE LED must be lit).
5. Start test program 1.
Circuit diagrams for the localization of errors can be found in the appendix.
Electrical SpecificationsPower requirement: regulated 5V DCInput current: 2000 mA
Mechanical SpecificationsDimensions: 160 mm [L] x 160 mm [W] x 31 mm [H]Net weight: 160 gTemperature range: 0 to 50oC
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
FPGA Pin InformationTable 33. Pin Table
Pin Name Signal Name Area
M24 SEG_A# 7-Segment Display
N23 SEG_B# 7-Segment Display
M22 SEG_B# 7-Segment Display
K21 SEG_CA0# 7-Segment Display
K20 SEG_CA0# 7-Segment Display
M21 SEG_D# 7-Segment Display
K22 SEG_DP# 7-Segment Display
M20 SEG_E# 7-Segment Display
L22 SEG_F# 7-Segment Display
L21 SEG_G# 7-Segment Display
B24 AC97_BITCLK AC97 Audio Codec
C23 AC97_EAPD AC97 Audio Codec
D25 AC97_EXT CLK AC97 Audio Codec
B25 AC97_RESET# AC97 Audio Codec
C26 AC97_SDATA_IN AC97 Audio Codec
C25 AC97_SDATA_OUT AC97 Audio Codec
D24 AC97_SYNC AC97 Audio Codec
W4 ADC- Analog Digital Converter
W3 ADC+ Analog Digital Converter
Y3 ADCS Analog Digital Converter
AA22 CCLK Configuration
AC24 CFG0 Configuration
W20 CFG1 Configuration
AD24 CFG2 Configuration
V22 CSSPIN Configuration
Y24 DOUT Configuration
AC3 EC_TCK Configuration
AA8 EC_TDI Configuration
AA5 EC_TDO Configuration
AB4 EC_TMS Configuration
AD25 JTAG_DONE Configuration
AB24 JTAG_INIT Configuration
V19 PROGRAM# Configuration
Y25 SISPI Configuration
W23 SPIDO Configuration
AB25 SPIFASTN# Configuration
AD10 DDR_A0 DDR SDRAM
AB11 DDR_A1 DDR SDRAM
AC10 DDR_A10 DDR SDRAM
AC14 DDR_A11 DDR SDRAM
AD14 DDR_A12 DDR SDRAM
AB10 DDR_A13 DDR SDRAM
AB12 DDR_A2 DDR SDRAM
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
AC12 DDR_A3 DDR SDRAM
AD12 DDR_A4 DDR SDRAM
AB13 DDR_A5 DDR SDRAM
AC13 DDR_A6 DDR SDRAM
AD13 DDR_A7 DDR SDRAM
AB15 DDR_A8 DDR SDRAM
AB14 DDR_A9 DDR SDRAM
AD7 DDR_BA0 DDR SDRAM
AC7 DDR_BA1 DDR SDRAM
AF9 DDR_CAS# DDR SDRAM
AF12 DDR_CK0- DDR SDRAM
AE12 DDR_CK0+ DDR SDRAM
AA2 DDR_CK1- DDR SDRAM
Y1 DDR_CK1+ DDR SDRAM
AF11 DDR_CKE0 DDR SDRAM
AF10 DDR_CKE1 DDR SDRAM
AF6 DDR_DM0 DDR SDRAM
AB6 DDR_DM1 DDR SDRAM
AB2 DDR_DM2 DDR SDRAM
T2 DDR_DM3 DDR SDRAM
AD9 DDR_DQ0 DDR SDRAM
AC9 DDR_DQ1 DDR SDRAM
AD5 DDR_DQ10 DDR SDRAM
AC5 DDR_DQ11 DDR SDRAM
AF4 DDR_DQ12 DDR SDRAM
AE4 DDR_DQ13 DDR SDRAM
AD4 DDR_DQ14 DDR SDRAM
AC4 DDR_DQ15 DDR SDRAM
AE2 DDR_DQ16 DDR SDRAM
AD1 DDR_DQ17 DDR SDRAM
AD2 DDR_DQ18 DDR SDRAM
AD3 DDR_DQ19 DDR SDRAM
AB9 DDR_DQ2 DDR SDRAM
AC1 DDR_DQ20 DDR SDRAM
AC2 DDR_DQ21 DDR SDRAM
Y5 DDR_DQ22 DDR SDRAM
Y6 DDR_DQ23 DDR SDRAM
V1 DDR_DQ24 DDR SDRAM
U1 DDR_DQ25 DDR SDRAM
P4 DDR_DQ26 DDR SDRAM
P5 DDR_DQ27 DDR SDRAM
P6 DDR_DQ28 DDR SDRAM
N3 DDR_DQ29 DDR SDRAM
AD8 DDR_DQ3 DDR SDRAM
Table 33. Pin Table (Continued)
Pin Name Signal Name Area
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
N4 DDR_DQ30 DDR SDRAM
N5 DDR_DQ31 DDR SDRAM
AC8 DDR_DQ4 DDR SDRAM
AB8 DDR_DQ5 DDR SDRAM
AF7 DDR_DQ7 DDR SDRAM
AE7 DDR_DQ7 DDR SDRAM
AF5 DDR_DQ8 DDR SDRAM
AE5 DDR_DQ9 DDR SDRAM
AE6 DDR_DQS0 DDR SDRAM
AA6 DDR_DQS1 DDR SDRAM
AB3 DDR_DQS2 DDR SDRAM
T1 DDR_DQS3 DDR SDRAM
AE9 DDR_RAS# DDR SDRAM
AF8 DDR_S0# DDR SDRAM
AE8 DDR_S1# DDR SDRAM
AF3 DDR_VREF DDR SDRAM
P9 DDR_VREF DDR SDRAM
AE10 DDR_WE# DDR SDRAM
C14 DAC_DIG Digital Analog Converter
F26 DSW0 DIP Switch
F25 DSW1 DIP Switch
E26 DSW2 DIP Switch
E25 DSW3 DIP Switch
P25 ETH_COL Ethernet
N26 ETH_CRS Ethernet
M26 ETH_MDC Ethernet
W24 ETH_MDINTR# Ethernet
N25 ETH_MDIO Ethernet
L26 ETH_RXCLK Ethernet
AA26 ETH_RXD0 Ethernet
Y26 ETH_RXD1 Ethernet
W26 ETH_RXD2 Ethernet
W25 ETH_RXD3 Ethernet
R25 ETH_RXDV Ethernet
P26 ETH_RXER Ethernet
L25 ETH_TXCLK Ethernet
V26 ETH_TXD0 Ethernet
V25 ETH_TXD1 Ethernet
V24 ETH_TXD2 Ethernet
V23 ETH_TXD3 Ethernet
R26 ETH_TXEN Ethernet
U26 ETH_TXER Ethernet
D1 CARDSEL# Expansion Connector
L1 EXPCON_CLKIN Expansion Connector
Table 33. Pin Table (Continued)
Pin Name Signal Name Area
29
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
M1 EXPCON_CLKOUT Expansion Connector
R1 EXPCON_IO0 Expansion Connector
R2 EXPCON_IO1 Expansion Connector
L8 EXPCON_IO10 Expansion Connector
K1 EXPCON_IO11 Expansion Connector
K2 EXPCON_IO12 Expansion Connector
K3 EXPCON_IO13 Expansion Connector
K4 EXPCON_IO14 Expansion Connector
K5 EXPCON_IO15 Expansion Connector
K6 EXPCON_IO16 Expansion Connector
K7 EXPCON_IO17 Expansion Connector
K8 EXPCON_IO18 Expansion Connector
J1 EXPCON_IO19 Expansion Connector
P1 EXPCON_IO2 Expansion Connector
J2 EXPCON_IO20 Expansion Connector
J3 EXPCON_IO21 Expansion Connector
J4 EXPCON_IO22 Expansion Connector
J5 EXPCON_IO23 Expansion Connector
J8 EXPCON_IO24 Expansion Connector
J9 EXPCON_IO25 Expansion Connector
H1 EXPCON_IO26 Expansion Connector
H2 EXPCON_IO27 Expansion Connector
H3 EXPCON_IO28 Expansion Connector
H4 EXPCON_IO29 Expansion Connector
P2 EXPCON_IO3 Expansion Connector
H5 EXPCON_IO30 Expansion Connector
H6 EXPCON_IO31 Expansion Connector
H7 EXPCON_IO32 Expansion Connector
H8 EXPCON_IO33 Expansion Connector
G1 EXPCON_IO34 Expansion Connector
G2 EXPCON_IO35 Expansion Connector
G3 EXPCON_IO36 Expansion Connector
G4 EXPCON_IO37 Expansion Connector
F1 EXPCON_IO38 Expansion Connector
F2 EXPCON_IO39 Expansion Connector
N1 EXPCON_IO4 Expansion Connector
F5 EXPCON_IO40 Expansion Connector
F6 EXPCON_IO41 Expansion Connector
E1 EXPCON_IO42 Expansion Connector
E2 EXPCON_IO43 Expansion Connector
E3 EXPCON_IO44 Expansion Connector
E4 EXPCON_IO45 Expansion Connector
M6 EXPCON_IO5 Expansion Connector
L2 EXPCON_IO6 Expansion Connector
Table 33. Pin Table (Continued)
Pin Name Signal Name Area
30
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
L5 EXPCON_IO7 Expansion Connector
L6 EXPCON_IO8 Expansion Connector
L7 EXPCON_IO9 Expansion Connector
B12 FLASH_BYTE# Flash/SRAM
A13 FLASH_CE# Flash/SRAM
B14 FLASH_RESET# Flash/SRAM
A14 FLASH_RY/BY# A Flash/SRAM
B13 FLASH_RY/BY# B Flash/SRAM
A12 FLASH_WP#/ACC Flash/SRAM
C1 MEMORY_A0 Flash/SRAM
B2 MEMORY_A1 Flash/SRAM
D4 MEMORY_A10 Flash/SRAM
A5 MEMORY_A11 Flash/SRAM
B5 MEMORY_A12 Flash/SRAM
C5 MEMORY_A13 Flash/SRAM
D5 MEMORY_A14 Flash/SRAM
E5 MEMORY_A15 Flash/SRAM
A6 MEMORY_A16 Flash/SRAM
B6 MEMORY_A17 Flash/SRAM
E6 MEMORY_A18 Flash/SRAM
A7 MEMORY_A19 Flash/SRAM
C2 MEMORY_A2 Flash/SRAM
B7 MEMORY_A20 Flash/SRAM
C7 MEMORY_A21 Flash/SRAM
D7 MEMORY_A22 Flash/SRAM
A3 MEMORY_A3 Flash/SRAM
B3 MEMORY_A4 Flash/SRAM
C3 MEMORY_A5 Flash/SRAM
D3 MEMORY_A6 Flash/SRAM
A4 MEMORY_A7 Flash/SRAM
B4 MEMORY_A8 Flash/SRAM
C4 MEMORY_A9 Flash/SRAM
E7 MEMORY_DQ0 Flash/SRAM
F7 MEMORY_DQ1 Flash/SRAM
A9 MEMORY_DQ10 Flash/SRAM
B9 MEMORY_DQ11 Flash/SRAM
C9 MEMORY_DQ12 Flash/SRAM
D9 MEMORY_DQ13 Flash/SRAM
E9 MEMORY_DQ14 Flash/SRAM
A10 MEMORY_DQ15 Flash/SRAM
B10 MEMORY_DQ16 Flash/SRAM
C10 MEMORY_DQ17 Flash/SRAM
D10 MEMORY_DQ18 Flash/SRAM
E10 MEMORY_DQ19 Flash/SRAM
Table 33. Pin Table (Continued)
Pin Name Signal Name Area
31
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
G7 MEMORY_DQ2 Flash/SRAM
F10 MEMORY_DQ20 Flash/SRAM
G10 MEMORY_DQ21 Flash/SRAM
A11 MEMORY_DQ22 Flash/SRAM
B11 MEMORY_DQ23 Flash/SRAM
E11 MEMORY_DQ24 Flash/SRAM
F11 MEMORY_DQ25 Flash/SRAM
G11 MEMORY_DQ26 Flash/SRAM
C12 MEMORY_DQ27 Flash/SRAM
D12 MEMORY_DQ28 Flash/SRAM
E12 MEMORY_DQ29 Flash/SRAM
A8 MEMORY_DQ3 Flash/SRAM
F12 MEMORY_DQ30 Flash/SRAM
G12 MEMORY_DQ31 Flash/SRAM
B8 MEMORY_DQ4 Flash/SRAM
C8 MEMORY_DQ5 Flash/SRAM
D8 MEMORY_DQ6 Flash/SRAM
E8 MEMORY_DQ7 Flash/SRAM
F8 MEMORY_DQ8 Flash/SRAM
G8 MEMORY_DQ9 Flash/SRAM
D13 MEMORY_OE# Flash/SRAM
C13 MEMORY_WE# Flash/SRAM
F13 SRAM_BE0# Flash/SRAM
G13 SRAM_BE1# Flash/SRAM
E14 SRAM_BE2# Flash/SRAM
E15 SRAM_BE3# Flash/SRAM
E13 SRAM_CE# Flash/SRAM
AD15 CLK_FPGA FPGA Clock
U25 CLK_FPGA FPGA Clock
F14 BB3V3_CLK0- FPGA Prototyping Area
D14 BB3V3_CLK0+ FPGA Prototyping Area
A15 BB3V3_IO0 FPGA Prototyping Area
B15 BB3V3_IO1 FPGA Prototyping Area
D17 BB3V3_IO10 FPGA Prototyping Area
E17 BB3V3_IO11 FPGA Prototyping Area
A18 BB3V3_IO12 FPGA Prototyping Area
B18 BB3V3_IO13 FPGA Prototyping Area
C18 BB3V3_IO14 FPGA Prototyping Area
D18 BB3V3_IO15 FPGA Prototyping Area
E18 BB3V3_IO16 FPGA Prototyping Area
A19 BB3V3_IO17 FPGA Prototyping Area
B19 BB3V3_IO18 FPGA Prototyping Area
C19 BB3V3_IO19 FPGA Prototyping Area
C15 BB3V3_IO2 FPGA Prototyping Area
Table 33. Pin Table (Continued)
Pin Name Signal Name Area
32
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
D19 BB3V3_IO20 FPGA Prototyping Area
E19 BB3V3_IO21 FPGA Prototyping Area
D15 BB3V3_IO3 FPGA Prototyping Area
A16 BB3V3_IO4 FPGA Prototyping Area
B16 BB3V3_IO5 FPGA Prototyping Area
E16 BB3V3_IO6 FPGA Prototyping Area
A17 BB3V3_IO7 FPGA Prototyping Area
B17 BB3V3_IO8 FPGA Prototyping Area
C17 BB3V3_IO9 FPGA Prototyping Area
T21 I2C_SCL1 I2C EEPROM
T22 I2C_SDA1 I2C EEPROM
G26 TST_COL0 Key Matrix
G25 TST_COL1 Key Matrix
G24 TST_COL2 Key Matrix
H26 TST_ROW0 Key Matrix
H25 TST_ROW1 Key Matrix
H24 TST_ROW2 Key Matrix
H23 TST_ROW3 Key Matrix
J22 LCD_ENABLE LCD
K24 LCD_REGSEL LCD
J24 LCD_RW LCD
R24 LED0# LED
R23 LED1# LED
R22 LED2# LED
R21 LED3# LED
P23 LED4# LED
P22 LED5# LED
P21 LED6# LED
N22 LED7# LED
H13 MACHXO_CLK0 MachXO
H14 MACHXO_CLK1 MachXO
A20 MACHXO_IO0 MachXO
B20 MACHXO_IO1 MachXO
C22 MACHXO_IO10 MachXO
D22 MACHXO_IO11 MachXO
A23 MACHXO_IO12 MachXO
B23 MACHXO_IO13 MachXO
E23 MACHXO_IO14 MachXO
A24 MACHXO_IO15 MachXO
C20 MACHXO_IO2 MachXO
D20 MACHXO_IO3 MachXO
E20 MACHXO_IO4 MachXO
A21 MACHXO_IO5 MachXO
B21 MACHXO_IO6 MachXO
Table 33. Pin Table (Continued)
Pin Name Signal Name Area
33
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
E21 MACHXO_IO7 MachXO
A22 MACHXO_IO8 MachXO
B22 MACHXO_IO9 MachXO
M25 HPE_RESET# Reset
AE24 HPE_RESOUT# Reset
J26 RS CTS_LVTTL RS232
K25 RS RTS_LVTTL RS232
J25 RS RXD_LVTTL RS232
K26 RS TXD_LVTTL RS232
M5 SATA_X1D0- SATA
M4 SATA_X1D0+ SATA
R3 SATA_X1D1- SATA
P3 SATA_X1D1+ SATA
U4 SATA_X2D0- SATA
U3 SATA_X2D0+ SATA
W2 SATA_X2D1- SATA
V2 SATA_X2D1+ SATA
E24 TST_STEP Single Step Key
AB21 USB_CTS USB Interface
AE20 USB_GPIO0 USB Interface
AD20 USB_GPIO1 USB Interface
AA19 USB_GPIO10 USB Interface
AF18 USB_GPIO11 USB Interface
AE18 USB_GPIO12 USB Interface
AD18 USB_GPIO13 USB Interface
AC18 USB_GPIO14 USB Interface
AB18 USB_GPIO15 USB Interface
AF17 USB_GPIO16 USB Interface
AE17 USB_GPIO17 USB Interface
AD17 USB_GPIO18 USB Interface
AC17 USB_GPIO19 USB Interface
AC20 USB_GPIO2 USB Interface
AB17 USB_GPIO20 USB Interface
AF16 USB_GPIO21 USB Interface
AE16 USB_GPIO22 USB Interface
AF15 USB_GPIO23 USB Interface
AE15 USB_GPIO24 USB Interface
AF14 USB_GPIO25 USB Interface
AE14 USB_GPIO26 USB Interface
AF13 USB_GPIO27 USB Interface
AE13 USB_GPIO28 USB Interface
AB20 USB_GPIO3 USB Interface
AA20 USB_GPIO4 USB Interface
AF19 USB_GPIO5 USB Interface
Table 33. Pin Table (Continued)
Pin Name Signal Name Area
34
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Ordering Information
Technical Support AssistanceHotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)e-mail: techsupport@latticesemi.comInternet: www.latticesemi.com
AE19 USB_GPIO6 USB Interface
AD19 USB_GPIO7 USB Interface
AC19 USB_GPIO8 USB Interface
AB19 USB_GPIO9 USB Interface
AD23 USB_MISO USB Interface
AB16 USB_MOSI USB Interface
AA16 USB_OC0# USB Interface
Y20 USB_OC1# USB Interface
Y19 USB_OC2# USB Interface
Y17 USB_PWEN0 USB Interface
Y16 USB_PWEN1 USB Interface
AA21 USB_PWEN2 USB Interface
AB22 USB_RTS USB Interface
AC23 USB_RXD USB Interface
AC22 USB_SCK USB Interface
AD22 USB_SSI# USB Interface
AA17 USB_TXD USB Interface
AF22 VGA_BL0 VGA Interface
AE21 VGA_BL1 VGA Interface
AF23 VGA_GR0 VGA Interface
AE22 VGA_GR1 VGA Interface
AF20 VGA_HSYNC VGA Interface
AF24 VGA_RD0 VGA Interface
AE23 VGA_RD1 VGA Interface
AF21 VGA_VSYNC VGA Interface
DescriptionOrdering Part
NumberChina RoHS Environment-Friendly Use Period (EFUP)
LatticeMico32/DSP Development Board for LatticeECP2 LFE2-50E-D-EV
Table 33. Pin Table (Continued)
Pin Name Signal Name Area
10
35
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Revision History
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are aslisted at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks oftheir respective holders. The specifications and information herein are subject to change without notice.
Portions copyright 2005 - 2008 Gleichmann and Company Electronics GmbH.
Date Version Change Summary
February 2007 01.0 Initial release.
March 2007 01.1 Added Ordering Information section.
April 2007 01.2 Updated SATA Interfaces information.
Reset Chip section - updated FPGA pin number for the the HPE RESET signal.
April 2007 01.3 Ordering information (EFUP) updated.
April 2007 01.4 Added important information for proper connection of ispDOWNLOAD (Programming) Cables.
July 2007 01.5 Various minor updates to improve readability, and correct typographical errors.
August 2007 01.6 Updated information for pins 4-7 in the Expansion Connector X14 table.
Updated information for LRF pin TP0902 in the FPGA Connections for the 12x12 Prototyping Area table.
September 2007 01.7 Updated Ascynchronous SRAM text section and corresponding table.
Updated Parallel Flash text section.
February 2008 01.8 Updated Ordering Information.
March 2008 01.9 Corrected Schematic Illustration of the Prototyping Area diagram.
April 2008 02.0 Updated 7-Segment Display U0502 Pin Definition table.
June 2008 02.1 Updated Schematic Illustration of the Prototyping Area.
October 2008 02.2 Updated Peripheral Interfaces diagram with Board Version 2 information.Updated Data Signal of the Asynchronous SRAM Chip U0404 table.
SPI Flash text section - Updated SPI Flash density to 16 bits. Added table. Updated steps for programing the SPI Flash memory.
Added note to Parallel Flash text section.
Added Appendix B. Board Version 2 Schematics.
October 2008 02.3 Address Signals of the Asynchronous SRAM Chips U0404 and U0405 table - updated FPGA Pin information for MEMORY_A1 and MEMORY_A2.
Address Signals of the Flash Chips U0402 and U0403 table - updated FPGA Pin information for MEMORY_A1 and MEMORY_A2.
October 2008 02.4 Updated photo used in User Interface Features figure.
Updated photo used in Components figure.
36
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Appendix A. Board Version 1 SchematicsFigure 9.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SE
G_
CA
0#
SE
G_A
#S
EG
_B#
SE
G_
C#
SE
G_
D#
SE
G_E
#S
EG
_F
#
SE
G_
DP
#
DS
W0
DS
W1
DS
W2
DS
W3
SE
G_
CA
1#
SE
G_G
#T
ST
_ST
EP
TS
T_C
OL0
TS
T_C
OL2
TS
T_C
OL1
LE
D7#
LE
D0#
LE
D1#
LE
D2#
LE
D3#
LE
D5#
LE
D6#
TS
T_R
OW
0
TS
T_R
OW
3T
ST
_RO
W2
TS
T_R
OW
1
LC
D_
RE
GS
EL
LC
D_
RW
LC
D_
EN
AB
LE
RS
_CT
S_L
VT
TL
RS
_RX
D_L
VT
TL
RS
_TX
D_L
VT
TL
RS
_RT
S_L
VT
TL
US
B_
GP
IO[2
8:0
]
US
B_
PW
EN
0U
SB
_O
C0
#U
SB
_P
WE
N1
US
B_
OC
1#
US
B_
PW
EN
2U
SB
_O
C2
#
CA
RD
SE
L#
VG
A_
RD
0V
GA
_R
D1
VG
A_
GR
0
VG
A_B
L0
VG
A_
GR
1V
GA
_H
SY
NC
VG
A_B
L1
VG
A_
VS
YN
C
LE
D4#
ET
H_T
XE
RE
TH
_TX
D3
ET
H_T
XD
1E
TH
_TX
D0
ET
H_T
XE
NE
TH
_TX
CLK
ET
H_R
XE
RE
TH
_RX
D3
ET
H_R
XD
2
ET
H_R
XD
0
ET
H_R
XC
LKE
TH
_RX
DV
ET
H_
CR
SE
TH
_C
OL
ET
H_R
XD
1E
TH
_TX
D2
ET
H_
MD
CE
TH
_M
DIO
ET
H_
MD
INT
R#
HP
E_
RE
SO
UT
#C
LK
_F
PG
A
EX
PC
ON
_C
LK
INE
XP
CO
N_C
LKO
UT
I2C
_S
CL
1I2
C_
SD
A1
FL
AS
H_
CE
#
SR
AM
_CE
#
ME
MO
RY
_OE
#M
EM
OR
Y_
WE
#
FL
AS
H_
WP
#/A
CC
ME
MO
RY
_A
[22
:0]
ME
MO
RY
_D
Q[3
1:0
]
FL
AS
H_
BY
TE
#
FL
AS
H_
RY
/BY
#_
AF
LA
SH
_R
Y/B
Y#
_B
SR
AM
_BE
0#S
RA
M_B
E1#
SR
AM
_BE
2#S
RA
M_B
E3#
FL
AS
H_
RE
SE
T#
HP
E_R
ES
ET
#
EX
PC
ON
_IO
[45
:0]
US
B_
MIS
OU
SB
_S
SI#
US
B_
SC
KU
SB
_M
OS
IU
SB
_TX
D
DD
R_
CK
E0
DD
R_
BA
0
DD
R_
WE
#D
DR
_R
AS
#D
DR
_C
AS
#
DD
R_
S0
#
DD
R_
DQ
[31
:0]
DD
R_
A[1
3:0
]
DD
R_
CK
0+
DD
R_
CK
0-
DD
R_
DQ
S[3
:0]
DD
R_
DM
[3:0
]
DD
R_
CK
1+
US
B_
RX
DU
SB
_R
TS
US
B_
CT
S
MA
CH
XO
_IO
[15
:0]
MA
CH
XO
_CLK
0
DD
R_
CK
E1
DD
R_
VR
EF
DD
R_
S1
#
DD
R_
BA
1
DD
R_
CK
1-
SA
TA
_X1D
1+S
AT
A_X
1D1-
SA
TA
_X2D
0+S
AT
A_X
2D0-
SA
TA
_X1D
0+S
AT
A_X
1D0-
SA
TA
_X2D
1+S
AT
A_X
2D1-
CL
K_
FP
GA
VG
A_
RD
0
VG
A_
RD
1V
GA
_G
R0
VG
A_B
L0V
GA
_G
R1
VG
A_
HS
YN
C
VG
A_B
L1V
GA
_V
SY
NC
US
B_
GP
IO0
US
B_
GP
IO1
US
B_
GP
IO2
US
B_
GP
IO3
US
B_
GP
IO4
US
B_
GP
IO5
US
B_
GP
IO6
US
B_
GP
IO7
US
B_
GP
IO8
US
B_
GP
IO9
US
B_
GP
IO10
US
B_
GP
IO11
US
B_
GP
IO12
US
B_
GP
IO13
US
B_
GP
IO14
US
B_
GP
IO15
US
B_
GP
IO16
US
B_
GP
IO17
US
B_
GP
IO18
US
B_
GP
IO19
US
B_
GP
IO21
US
B_
GP
IO22
US
B_
GP
IO23
US
B_
GP
IO24
US
B_
GP
IO25
US
B_
GP
IO26
US
B_
GP
IO27
US
B_
GP
IO28
FL
AS
H_
WP
#/A
CC
I2C
_S
DA
1
I2C
_S
CL
1
LE
D1#
LE
D3#
LE
D4#
LE
D5#
LE
D6#
LE
D7#
MA
CH
XO
_IO
5
MA
CH
XO
_IO
3
MA
CH
XO
_IO
4
MA
CH
XO
_IO
6
CL
K_
FP
GA
HP
E_R
ES
ET
#
MA
CH
XO
_CLK
0
MA
CH
XO
_IO
0
MA
CH
XO
_IO
1
MA
CH
XO
_IO
2
US
B_
MO
SI
US
B_T
XD
US
B_
OC
0#
US
B_
PW
EN
0
US
B_
PW
EN
1
US
B_
PW
EN
2
US
B_
OC
1#
US
B_
OC
2#
DD
R_
DQ
S3
DD
R_
A9
DD
R_
A1
1
DD
R_
A1
2
DD
R_
A5
DD
R_
A6
DD
R_
A7
DD
R_
A8
DD
R_
A1
DD
R_
A2
DD
R_
A3
DD
R_
A4
DD
R_
A0
DD
R_
A1
3
DD
R_
DQ
28
DD
R_
A1
0
DD
R_
DQ
24
DD
R_
DQ
25
DD
R_
DQ
29
DD
R_
DQ
30
DD
R_
DQ
31
DD
R_
CK
E1
DD
R_
CA
S#
DD
R_
RA
S#
DD
R_
VR
EF
DD
R_
WE
#
DD
R_
S0
#D
DR
_S
1#
DD
R_
DQ
0
DD
R_
DQ
6
DD
R_
DM
0D
DR
_D
QS
0
DD
R_
DQ
S2
DD
R_
DM
2
DD
R_
DQ
17
DD
R_
DQ
18
DD
R_
DQ
19
DD
R_
DQ
20
DD
R_
DQ
21
DD
R_
DQ
22
DD
R_
DQ
23
DD
R_
CK
0+
DD
R_
CK
0-
DD
R_
CK
1+
DD
R_
CK
1-
DD
R_
VR
EF
DD
R_
DQ
7
DD
R_
DQ
1
DD
R_
DQ
12
DD
R_
DQ
13
DD
R_
DQ
14
DD
R_
DQ
15
DD
R_
CK
E0
BB
3V
3_C
LK0-
BB
3V
3_
IO[2
1:0
]
BB
3V3_
CLK
0+
EX
PC
ON
_IO
1
EX
PC
ON
_IO
3E
XP
CO
N_I
O2
EX
PC
ON
_IO
0
EX
PC
ON
_IO
7
EX
PC
ON
_IO
14
EX
PC
ON
_IO
4
EX
PC
ON
_IO
8
EX
PC
ON
_IO
9
EX
PC
ON
_IO
5
EX
PC
ON
_IO
23
EX
PC
ON
_IO
24
EX
PC
ON
_IO
22
EX
PC
ON
_IO
27E
XP
CO
N_I
O26
EX
PC
ON
_IO
25
EX
PC
ON
_IO
30
EX
PC
ON
_IO
29E
XP
CO
N_I
O28
EX
PC
ON
_IO
32
EX
PC
ON
_IO
31
EX
PC
ON
_IO
35
EX
PC
ON
_IO
33
EX
PC
ON
_IO
34
EX
PC
ON
_IO
10
EX
PC
ON
_IO
13E
XP
CO
N_I
O12
EX
PC
ON
_IO
6
EX
PC
ON
_IO
15
EX
PC
ON
_IO
11
EX
PC
ON
_IO
18
EX
PC
ON
_IO
16
EX
PC
ON
_IO
19E
XP
CO
N_I
O20
EX
PC
ON
_C
LK
IN
EX
PC
ON
_CLK
OU
T
EX
PC
ON
_IO
21
EX
PC
ON
_IO
36E
XP
CO
N_I
O37
EX
PC
ON
_IO
38
AC
97
_S
YN
C
AC
97
_E
AP
D
AC
97
_S
DA
TA
_IN
AC
97_
SD
AT
A_O
UT
AC
97_
RE
SE
T#
AC
97_E
XT
_CLK
HP
E_
RE
SO
UT
#
US
B_
MIS
O
US
B_
SS
I#
US
B_
SC
K
US
B_
RX
D
US
B_
RT
S
US
B_
CT
S
ME
MO
RY
_D
Q5
ME
MO
RY
_D
Q6
ME
MO
RY
_D
Q1
ME
MO
RY
_D
Q0
ME
MO
RY
_D
Q7
ME
MO
RY
_D
Q9
ME
MO
RY
_D
Q8
ME
MO
RY
_D
Q2
ME
MO
RY
_D
Q4
ME
MO
RY
_A9
ME
MO
RY
_A10
ME
MO
RY
_A15
ME
MO
RY
_D
Q3
ME
MO
RY
_A11
ME
MO
RY
_A13
ME
MO
RY
_A12
ME
MO
RY
_A14
ME
MO
RY
_A16
ME
MO
RY
_A22
ME
MO
RY
_A5
ME
MO
RY
_A6
ME
MO
RY
_A2
ME
MO
RY
_A21
ME
MO
RY
_A17
ME
MO
RY
_A19
ME
MO
RY
_A18
ME
MO
RY
_A20
ME
MO
RY
_A7
ME
MO
RY
_A4
ME
MO
RY
_A1
ME
MO
RY
_A3
ME
MO
RY
_A0
ME
MO
RY
_A8
ME
MO
RY
_D
Q2
6
ME
MO
RY
_D
Q2
4
ME
MO
RY
_D
Q1
9
ME
MO
RY
_D
Q2
1
ME
MO
RY
_D
Q1
5M
EM
OR
Y_
DQ
16
ME
MO
RY
_D
Q2
3
ME
MO
RY
_D
Q2
8
ME
MO
RY
_D
Q2
7
ME
MO
RY
_D
Q1
1
ME
MO
RY
_D
Q1
2
ME
MO
RY
_D
Q1
7
ME
MO
RY
_D
Q1
8
ME
MO
RY
_D
Q2
2
ME
MO
RY
_D
Q1
0
ME
MO
RY
_D
Q3
1M
EM
OR
Y_
DQ
29
ME
MO
RY
_D
Q2
5
ME
MO
RY
_D
Q3
0
ME
MO
RY
_W
E#
ME
MO
RY
_D
Q1
4M
EM
OR
Y_
DQ
13
ME
MO
RY
_D
Q2
0
ME
MO
RY
_OE
#
SR
AM
_CE
#
SR
AM
_BE
1#
SR
AM
_BE
0#
XR
ES
FL
AS
H_
RY
/BY
#_
B
FL
AS
H_
BY
TE
#
FL
AS
H_
RY
/BY
#_
A
FL
AS
H_
CE
#
SR
AM
_BE
3#
SR
AM
_BE
2#
FL
AS
H_
RE
SE
T#
BB
3V
3_IO
0
BB
3V
3_IO
1
BB
3V
3_IO
2
BB
3V
3_IO
3
BB
3V
3_IO
12B
B3
V3_
IO13
BB
3V
3_IO
14
BB
3V
3_IO
15
BB
3V
3_IO
16
BB
3V
3_IO
17
BB
3V
3_IO
18
BB
3V
3_IO
19
BB
3V
3_IO
20
BB
3V
3_IO
21
BB
3V
3_IO
4
BB
3V
3_IO
5
BB
3V
3_IO
6
BB
3V
3_C
LK0-
BB
3V
3_IO
7B
B3
V3_
IO8
BB
3V
3_IO
9B
B3
V3_
IO10
BB
3V
3_IO
11
DA
C_
DIG
MA
CH
XO
_IO
7
MA
CH
XO
_IO
8
MA
CH
XO
_IO
9
MA
CH
XO
_IO
10
MA
CH
XO
_IO
11
MA
CH
XO
_IO
12
MA
CH
XO
_IO
13
MA
CH
XO
_IO
14
MA
CH
XO
_IO
15
MA
CH
XO
_CLK
1
BB
3V3_
CLK
0+
AC
97
_B
ITC
LK
TS
T_C
OL1
TS
T_R
OW
3
TS
T_R
OW
0T
ST
_RO
W1
TS
T_R
OW
2
TS
T_C
OL2
TS
T_C
OL0
TS
T_S
TE
P
DS
W0
DS
W1
DS
W2
DS
W3
SE
G_
C#
SE
G_
DP
#S
EG
_G#
SE
G_
D#
SE
G_
CA
0#
SE
G_
CA
1#
SE
G_B
#
SE
G_
F#
SE
G_A
#
SE
G_E
#
LC
D_
RW
LC
D_
RE
GS
EL
LC
D_
EN
AB
LE
RS
_CT
S_L
VT
TL
RS
_RX
D_L
VT
TL
RS
_RT
S_L
VT
TL
RS
_TX
D_L
VT
TL
ET
H_T
XE
R
ET
H_R
XD
V
ET
H_
CR
S
ET
H_
CO
L
ET
H_
MD
C
ET
H_
MD
IO
ET
H_
MD
INT
R#
ET
H_T
XC
LKE
TH
_RX
CLK
ET
H_T
XD
3
ET
H_T
XD
1
ET
H_T
XE
N
ET
H_T
XD
2
ET
H_R
XE
R
ET
H_R
XD
2
ET
H_R
XD
0E
TH
_RX
D1
ET
H_R
XD
3
ET
H_T
XD
0
LE
D0#
LE
D2#
US
B_
GP
IO20
DD
R_
DQ
5
DD
R_
DQ
4D
DR
_D
Q3
DD
R_
DQ
2
DD
R_
BA
0D
DR
_B
A1
DD
R_
DM
1
DD
R_
DQ
8
DD
R_
DQ
S1
DD
R_
DQ
9
DD
R_
DQ
10
DD
R_
DQ
11
SA
TA
_X2D
1-S
AT
A_X
2D1+
SA
TA
_X1D
0+
SA
TA
_X1D
1+S
AT
A_X
1D1-
SA
TA
_X1D
0-
DD
R_
DQ
16
DD
R_
DM
3
DD
R_
DQ
27
DD
R_
DQ
26
SA
TA
_X2D
0+S
AT
A_X
2D0-
EX
PC
ON
_IO
17
EX
PC
ON
_IO
39
EX
PC
ON
_IO
40E
XP
CO
N_I
O41
EX
PC
ON
_IO
42E
XP
CO
N_I
O43
EX
PC
ON
_IO
44E
XP
CO
N_I
O45
CA
RD
SE
L#
MA
CH
XO
_CLK
1
DA
C_
DIG
DA
C_
AN
AL
OG
AD
C+
AD
C-
AD
C+
AD
CS
AD
CS
AD
C-
AC
97_
SD
AT
A_O
UT
AC
97
_S
YN
CA
C9
7_
SD
AT
A_
INA
C97
_EX
T_C
LKA
C9
7_R
ES
ET
#
AC
97
_E
AP
D
AC
97
_B
ITC
LK
VC
C2
V5
GN
D
VC
C3
V3
GN
D
GN
DG
ND
GN
D
VC
C1
V2
GN
D
GN
D
VC
C1
V2
GN
D
GN
DV
CC
3V
3
VC
C3
V3
GN
D
GN
D
VC
C3
V3
GN
D
VC
C3
V3
GN
D
VC
C3
V3
GN
D
VC
C2
V5
GN
D
VC
C2
V5
GN
D
GN
D
GN
D
VC
C3
V3
GN
D
VC
C3
V3
GN
D
GN
DG
ND
_D
AC
GN
D_
DA
C
GN
D_
AD
C
GN
DG
ND
_A
DC
VC
C1
V2
DS
W0
5D
SW
15
DS
W2
5D
SW
35
TS
T_R
OW
05
TS
T_R
OW
15
TS
T_R
OW
25
LE
D0
#5
TS
T_R
OW
35
LE
D2
#5
LE
D1
#5
LE
D3
#5
LE
D5
#5
LE
D4
#5
LE
D6
#5
SE
G_
CA
0#5
LE
D7
#5
SE
G_B
#5
SE
G_
CA
1#5
SE
G_
C#
5
SE
G_E
#5
SE
G_
F#
5S
EG
_G#
5
SE
G_A
#5
SE
G_
DP
#5
TS
T_C
OL0
5S
EG
_D
#5
TS
T_C
OL1
5
TS
T_S
TE
P5
TS
T_C
OL2
5
LC
D_
RE
GS
EL
5L
CD
_R
W5
LC
D_
EN
AB
LE
5 RS
_CT
S_L
VT
TL
7R
S_R
XD
_LV
TT
L7
RS
_TX
D_L
VT
TL
7R
S_R
TS
_LV
TT
L7
US
B_
GP
IO[2
8:0
]7
US
B_
PW
EN
07
US
B_
OC
0#
7U
SB
_P
WE
N1
7U
SB
_O
C1
#7
US
B_
PW
EN
27
US
B_
OC
2#
7
CA
RD
SE
L#
9
VG
A_
RD
010
VG
A_
RD
110
VG
A_
GR
010
VG
A_
GR
110
VG
A_B
L010
VG
A_
HS
YN
C10
VG
A_B
L110
VG
A_
VS
YN
C10
ET
H_T
XE
R8
ET
H_T
XD
38
ET
H_T
XD
28
ET
H_T
XD
18
ET
H_T
XD
08
ET
H_T
XE
N8
ET
H_T
XC
LK8
ET
H_R
XE
R8
ET
H_R
XD
38
ET
H_R
XD
28
ET
H_R
XD
18
ET
H_R
XD
08
ET
H_R
XC
LK8
ET
H_R
XD
V8
ET
H_
CR
S8
ET
H_
CO
L8
ET
H_
MD
INT
R#
8
ET
H_
MD
C8
ET
H_
MD
IO8
HP
E_
RE
SO
UT
#6
,7,8
,9C
LK
_F
PG
A6
EX
PC
ON
_C
LK
IN9
EX
PC
ON
_CLK
OU
T9
I2C
_S
DA
16
I2C
_S
CL
16 F
LA
SH
_C
E#
4
SR
AM
_CE
#4
ME
MO
RY
_OE
#4
ME
MO
RY
_W
E#
4
FL
AS
H_
WP
#/A
CC
4
ME
MO
RY
_A
[22
:0]
4M
EM
OR
Y_
DQ
[31
:0]
4
FL
AS
H_
BY
TE
#4
FL
AS
H_
RY
/BY
#_
A4
FL
AS
H_
RY
/BY
#_
B4
SR
AM
_BE
0#4
SR
AM
_BE
1#4
SR
AM
_BE
2#4
SR
AM
_BE
3#4
FL
AS
H_
RE
SE
T#
4
HP
E_
RE
SE
T#
3,6 E
XP
CO
N_
IO[4
5:0
]9
US
B_
MIS
O7
US
B_
SS
I#7
US
B_
SC
K7
US
B_
MO
SI
7U
SB
_TX
D7
DD
R_
CK
E0
4D
DR
_B
A0
4D
DR
_B
A1
4
DD
R_
VR
EF
4
DD
R_
WE
#4
DD
R_
RA
S#
4D
DR
_C
AS
#4
DD
R_
S0
#4
DD
R_
S1
#4
DD
R_
DQ
[31
:0]
4
DD
R_
A[1
3:0
]4
DD
R_
CK
0+
4D
DR
_C
K0
-4
DD
R_
DQ
S[3
:0]
4
DD
R_
DM
[3:0
]4
DD
R_
CK
1+
4
US
B_
RX
D7
US
B_
RT
S7
US
B_
CT
S7
MA
CH
XO
_IO
[15
:0]
3M
AC
HX
O_C
LK0
3
DD
R_
CK
E1
4D
DR
_C
K1
-4
SA
TA
_X1D
1+9
SA
TA
_X1D
1-9
SA
TA
_X2D
0+9
SA
TA
_X2D
0-9
SA
TA
_X1D
0+9
SA
TA
_X1D
0-9
SA
TA
_X2D
1+9
SA
TA
_X2D
1-9
BB
3V
3_C
LK0-
9B
B3V
3_C
LK0+
9
BB
3V
3_
IO[2
1:0
]9
MA
CH
XO
_CLK
13
AC
97_
SD
AT
A_O
UT
10
AC
97
_S
YN
C10
AC
97
_S
DA
TA
_IN
10A
C97
_EX
T_C
LK10
AC
97_
RE
SE
T#
10
AC
97
_E
AP
D10
AC
97
_B
ITC
LK10
:te
eh
S:tc
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
visi
on
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
stra
ße
119
A-4
232
Hag
enbe
rgo
fP
age
Hp
e_
min
i LE
C2
02
_F
PG
A
csam
R0
1
Sa
turd
ay,
Ap
ril 2
9,
20
06
10
:35
:32
Mo
nd
ay,
Se
pte
mb
er
04
, 2
00
61
7:1
5:0
4
122
Latti
ce E
CP
2-50
FP
GA
Offp
age
Hum
an In
terf
ace
RS
232
US
B
Eth
erne
t
Exp
ansi
on C
onne
ctor
s an
d P
roto
typi
ng A
rea
Aud
io C
odec
VG
A
Clo
ck /
Res
et
Mem
ory
Mac
hXO
1%
DIFF
LVDS
LVDS
LVDS
LVDS
DA
C
AD
C
LVDS
LVDS
0,1%
0,1%
Sternpunkt an X1
Sternpunkt an X2
1
23
04
Place pins 0..4 near the balls of the FPGA.
These pins must also be accessible for
measurements instruments.
R0
205
33
k2
12
100n
C0
207
100n
C0
230
100n
C0
201
100n
C0
210
100n
C0
221
nb_4
p70
C0
25
1
+C
02
38
4u70
1 2
1n00
C0
24
4
100n
C0
211
100n
C0
216
100n
C0
231
+C
02
42
4u70
1 2
nbC
02
48
100n
C0
225
R0
20
4
10
k0
12
optional
A02
01Ju
mp
er
100n
C0
20
2
100n
C0
204
100n
C0
215
100n
C0
237
4p70
C0
250
100n
C0
217
1n00
C0
23
9
POWER SUPPLY
U0
20
1F
EC
P2
-50-
672B
GA
GN
DN
12
GN
DN
10
GN
DM
14
GN
DM
13
GN
DL3
GN
DL24
GN
DL17
GN
DL16
GN
DL11
GN
DL10
GN
DK
17
GN
DK
16
GN
DK
14
GN
DK
13
GN
DK
11
GN
DK
10
GN
DJ6
GN
DJ2
1G
ND
J14
GN
DJ1
3G
ND
F9
GN
DF
3G
ND
F24
GN
DF
18
GN
DC
6G
ND
C21
GN
DC
16
GN
DC
11
GN
DB
26
GN
DB
1G
ND
AF
25
GN
DA
F2
GN
DA
E26
GN
DA
E1
GN
DA
D6
GN
DA
D21
GN
DA
D16
GN
DA
D11
GN
DA
A9
GN
DA
A3
GN
DA
A24
GN
DA
A18
GN
DA
25
GN
DA
2V
CC
L12
VC
CL13
VC
CL14
VC
CL15
VC
CM
11
VC
CM
12
VC
CM
15
VC
CM
16
VC
CN
11
VC
CN
16
VC
CP
11
VC
CP
16
VC
CR
11
VC
CR
12
VC
CR
15
VC
CR
16
VC
CT
12
VC
CT
13
VC
CT
14
VC
CT
15
VC
CIO
0D
11
VC
CIO
0D
6
VC
CIO
0G
9
VC
CIO
0J1
2
VC
CIO
0K
12
VC
CIO
1D
16
VC
CIO
1D
21
VC
CIO
1G
18
VC
CIO
1J1
5
VC
CIO
1K
15
VC
CIO
2F
23
VC
CIO
2J2
0
VC
CIO
2L23
VC
CIO
2M
17
VC
CIO
2M
18
VC
CIO
3A
A23
VC
CIO
3R
17
VC
CIO
3R
18
VC
CIO
3T
23
VC
CIO
3V
20
VC
CIO
4A
C16
VC
CIO
4A
C21
VC
CIO
4U
15
VC
CIO
4V
15
VC
CIO
4Y
18
VC
CIO
5A
C11
VC
CIO
5A
C6
VC
CIO
5U
12
VC
CIO
5V
12
VC
CIO
5Y
9
VC
CIO
6A
A4
VC
CIO
6R
10
VC
CIO
6R
9
VC
CIO
6T
4
VC
CIO
6V
7
VC
CIO
7F
4
VC
CIO
7J7
VC
CIO
7L4
VC
CIO
7M
10
VC
CIO
7M
9
VC
CIO
8A
E2
5
VC
CIO
8V
18
GN
DN
13
GN
DN
14
GN
DN
15
GN
DN
17
GN
DP
10
GN
DP
12
GN
DP
13
GN
DP
14
GN
DP
15
GN
DP
17
GN
DR
13
GN
DR
14
GN
DT
10
GN
DT
11
GN
DT
16
GN
DT
17
GN
DT
24
GN
DT
3
GN
DU
10
GN
DU
11
GN
DU
13
GN
DU
14
GN
DU
16
GN
DU
17
GN
DV
13
GN
DV
14
GN
DV
21
GN
DV
6
7
KN
AB
6
KN
AB
U0
20
1D
EC
P2
-50-
672B
GA
PL46A
/PC
LK
T6_0
M4
VR
EF
2_7/P
L2A
D2
PL46B
/PC
LK
C6_0
M5
PL47A
/VR
EF
2_6
N7
PL47B
/VR
EF
1_6
P9
PL49A
N5
PL48A
N3
PL
49
BP
7
PL
48
BN
4
PL
51
BP
6P
L51A
P8
PL
50
BT
2P
L50A
/LD
QS
50
T1
PL
52
BP
4P
L5
2A
P5
PL
53
BV
1P
L5
3A
U1
PL60A
/LLM
0_G
DLLT
_IN
_A
Y1
PL
58
BR
7
PL55A
R4
PL60B
/LLM
0_G
DLLC
_IN
_A
AA
2
PL
57
BR
5P
L57A
T6
PL61B
/LLM
0_G
DLLC
_F
B_D
T7
PL58A
/LD
QS
58
R6
PL59B
Y2
PL59A
W1
PL
54
AP
3
PL56B
W2
PL
56
AV
2P
L5
5B
U2
PL61A
/LLM
0_G
DLLT
_F
B_A
T5
PL
54
BR
3
PL67A
/LD
QS
67
W3
PL
65
AV
4
PL
66
AY
3
PL64A
/LLM
0_G
PLLT
_F
B_A
V3
PL63A
/LLM
0_G
PLLT
_IN
_A
U3
PL63B
/LLM
0_G
PLLC
_IN
_A
U4
PL
70
BU
6
PL66B
Y4
PL69A
U8
PL68B
AB
1
PL64B
/LLM
0_G
PLLC
_F
B_A
U5
PL
65
BV
5
PL
71
AW
6
PL
70
AV
8
PL
67
BW
4
PL68A
AA
1
PL
71
BW
5
PL
72
AA
C1
PL
72
BA
D1
PL
73
AY
6
PL
73
BY
5
PL
74
AA
E2
PL
74
BA
D2
PL75A
/LD
QS
75
AB
3
PL
75
BA
B2
PL
76
AW
7
PL
76
BW
8
PL
77
AY
7
PL
77
BY
8
PL78A
AC
2
PL78B
AD
3
VR
EF
1_7/P
L2B
D1
PL5A
F6
PL5B
F5
PL6A
E4
PL6B
E3
PL7A
E2
PL7B
E1
PL8B
H5
LD
QS
8/P
L8A
H6
PL9A
F2
PL9B
F1
PL
10
AH
8
PL
11
AG
4P
L1
0B
J9
PL
11
BG
3
PL14B
H4
PL
12
AH
7
LD
QS
16/P
L16A
J3
PL
17
AH
1
PL
14
AH
3
PL
12
BJ8
PL
19
BJ2
PL
13
AG
2
PL15A
J5
PL16B
K4
PL
18
AK
6
PL
18
BK
7
PL19A
J1
PL
17
BH
2
PL
15
BJ4
PL
13
BG
1
PL39B
K5
LD
QS
41/P
L41A
P1
PL
37
AN
1
PL23B
K2
LU
M0_S
PLLT
_IN
_A
/PL25A
L1
PL
24
BL2
LU
M0_S
PLLC
_F
B_A
/PL26B
N2
LD
QS
24/P
L24A
K1
PL
39
AL6
LU
M0_S
PLLC
_IN
_A
/PL25B
M2
PL38A
L8
LU
M0_S
PLLT
_F
B_A
/PL26A
M1
PL
40
BL5
PL40A
L7
PL
23
AK
3
PL
38
BK
8
PL42B
N8
PL
43
AR
1
PC
LK
T7_0/P
L44A
M7
PL
42
AM
6P
L4
1B
P2
PC
LK
C7_0/P
L44B
N9
PL
43
BR
2
PL69B
U7
100n
C0
226
100n
C0
212
+C
02
43
4u70
1 2
100n
C0
208
100n
C0
234
100n
C0
203
+C
02
404u
70
1 2
100n
C0
218
100n
C0
222
100n
C0
232
R0
201
0R
00
1 2
5
KN
AB
4
KN
AB
U0
20
1C
EC
P2
-50-
672B
GA
PB
82A
/VR
EF
2_4
Y21
VR
EF
2_5/P
B2A
AE
3
PB
82B
/VR
EF
1_4
AB
23
PB
81A
Y20
PB
81B
AB
22
PB
80A
AF
24
PB
78A
/BD
QS
78
AB
21
PB
79B
AA
21
PB
80B
AE
24
PB
79A
W19
PB
78B
AC
22
PB
77B
AC
20
PB
77A
AB
20
PB
49A
/PC
LK
T4_0
AD
15
PB
49B
/PC
LK
C4_0
AC
15
PB
50A
AE
13
PB
50B
AF
13
PB
51A
/BD
QS
51
AB
17
PB
51B
Y15
PB
52A
AE
14
PB
52B
AF
14
PB
57B
AB
18
PB
54A
AC
17
PB
54B
AB
16
PB
57A
Y16
PB
55B
AF
15
PB
53A
AA
16
PB
56B
AF
16
PB
55A
AE
15
PB
56A
AE
16
PB
58B
AD
18
PB
60B
AE
17
PB
59B
AD
19
PB
58A
AD
17
PB
62A
AF
17
PB
61B
AE
19
PB
61A
AB
19
PB
59A
AC
18
PB
60A
/BD
QS
60
AC
19
PB
62B
AE
18
PB
63A
W16
PB
63B
AA
17
PB
64A
AF
18
PB
64B
AF
19
PB
65A
AA
19
PB
65B
W17
PB
66A
Y19
PB
66B
Y17
PB
67A
AF
20
PB
67B
AE
20
PB
68A
AA
20
PB
68B
W18
PB
69A
/BD
QS
69
AD
20
PB
70A
AF
21
PB
69B
AE
21
PB
70B
AF
22
PB
74A
AE
22
PB
74B
AD
22
PB
75A
AF
23
PB
75B
AE
23
PB
76A
AD
23
PB
76B
AC
23
VR
EF
1_5/P
B2B
AF
3
PB
3A
AC
4
PB
3B
AD
4
PB
4B
AF
4
PB
5B
W9
PB
5A
V9
PB
4A
AE
4
BD
QS
6/P
B6A
AA
6
PB
7B
AD
5
PB
6B
AB
6
PB
7A
AC
5
PB
9A
AE
5
PB
9B
AF
5
PB
8B
AB
7P
B8A
AA
7
BD
QS
24/P
B24A
AE
6
PB
26A
AB
9
PB
26B
AD
9
PB
21A
W11
PB
24B
AF
6
PB
23B
AB
10
PB
10B
AD
7
PB
23A
AB
8
PB
20B
Y10
PB
22B
AD
8
PB
20A
W10
PB
21B
AA
10
PB
25A
AA
11
PB
25B
AC
9
PB
10A
AC
7
PB
22A
AC
8
PB
28B
AF
7
BD
QS
33/P
B33A
AC
13
PB
32A
AD
12
PB
29A
AC
10
PB
30A
AA
12
PB
32B
AC
12
PB
34B
AC
14
PB
28A
AE
7
PB
34A
AD
13
PB
33B
AA
13
PB
31A
AB
12
PB
29B
AD
10
PB
27B
AB
11
PB
27A
Y11
PB
30B
W12
PB
31B
Y12
PB
35A
AE
8
PB
37A
AE
9
PB
36A
AB
15
PB
37B
AF
9
PB
36B
Y13
PB
38A
W13
PB
35B
AF
8
PB
38B
AA
14
PB
39A
AE
10
PB
39B
AF
10
PB
40A
W14
PB
40B
AB
13
PB
41A
Y14
PB
41B
AB
14
BD
QS
42/P
B42A
AE
11
PB
43A
AD
14
PB
43B
AA
15
PC
LK
T5_0/P
B44A
AE
12
PC
LK
C5_0/P
B44B
AF
12
PB
42B
AF
11
PB
53B
W15
3n30
C0
246
X22
12
100n
C0
235
100n
C0
223
100n
C0
233
100n
C0
227
100n
C0
209
100n
C0
205
100n
C0
213
R0
20
210
K0
12
100n
C0
228
3
KN
AB
2
KN
AB
U0
201
B
EC
P2
-50-
672B
GA
PR
2A
/VR
EF
1_2
F21
PC
LK
T3_0/P
R46A
L25
PR
2B
/VR
EF
2_2
E22
PR
5A
H20
PR
6B
D23
PR
5B
G21
PR
6A
C23
PR
8A
/RD
QS
8G
22
PR
7B
B24
PR
7A
C24
PR
9B
D24
PR
8B
H21
PR
9A
B25
PR
12B
D26
PR
14A
G23
PR
15B
J22
PR
11A
E24
PR
14B
G24
PR
10A
C25
PR
13A
J19
PR
12A
C26
PR
10B
D25
PR
11B
F22
PR
15A
H22
PR
13B
K19
PR
17A
L19
PR
17B
K20
PR
18A
F25
PR
16A
/RD
QS
16
E25
PR
16B
E26
PR
23B
H24
PR
18B
F26
PR
19A
G25
PR
23A
H23
PR
19B
G26
PR
24B
H26
PR
25A
/RU
M0_S
PLLT
_IN
_A
K23
PR
26A
/RU
M0_S
PLLT
_F
B_A
J25
PR
24A
/RD
QS
24
H25
PR
25B
/RU
M0_S
PLLC
_IN
_A
J23
PR
37B
K24
PR
38A
M21
PR
26B
/RU
M0_S
PLLC
_F
B_A
J26
PR
38B
K21
PR
37A
J24
PC
LK
C3_0/P
R46B
L26
VR
EF
1_
3/P
R4
7A
N21
VR
EF
2_3/P
R47B
N18
PR
48A
M25
PR
49A
N20
PR
48B
M26
PR
49B
N19
PR
53A
P19
PR
52A
P22
PR
52B
P23
RD
QS
50/P
R50A
N25
PR
51A
R21
PR
50B
N26
PR
53B
P21
PR
51B
N22
PR
54B
P20
PR
54A
R19
PR
55B
R24
PR
56A
P25
PR
57B
R22
PR
57A
T21
PR
56B
P26
PR
55A
R23
RLM
0_G
DLLC
_IN
_A
/PR
60A
T26
RLM
0_G
DLLT
_F
B_A
/PR
61A
U20
RD
QS
58/P
R58A
R25
RLM
0_G
DLLC
_F
B_A
/PR
61B
T19
RLM
0_G
DLLC
_IN
_A
/PR
60B
T25
PR
58B
R26
PR
59A
T22
PR
59B
T20
RLM
0_G
PLLT
_IN
_A
/PR
63A
U25
PR
65A
U26
RLM
0_G
PLLC
_F
B_A
/PR
64B
U22
PR
65B
V26
PR
66A
V25
RLM
0_G
PLLC
_IN
_A
/PR
63B
U24
PR
66B
V24
RLM
0_G
PLLT
_F
B_A
/PR
64A
U23
PR
39A
M22
PR
40A
M19
PR
40B
M20
PR
41A
/RD
QS
41
K25
PR
41B
K26
PR
42A
N23
PR
42B
M24
PR
43A
K22
PR
43B
L21
PR
44A
/PC
LK
T2_0
M23
PR
44B
/PC
LK
C2_0
N24
RD
QS
67/P
R67A
W26
PR
67B
W25
PR
68A
U19
PR
68B
U21
PR
69A
Y26
PR
69B
AA
26
PR
70A
V23
PR
70B
W24
PR
39B
L22
1n00
C0
24
510
0nC
02
36
100n
C0
219
FB
02
01B
LM
18B
D60
1SN
1
12
100n
C0
224
100n
C0
206
1n00
C0
241
100n
C0
229
R0
20
3
10
k0
12
nbC
02
49
nbC
02
47
1
KN
AB
0
KN
AB
U0
201
A
EC
P2
-50-
672B
GA
PT
37A
B8
PT
36B
E11
PT
36A
C9
PT
35B
A7
PT
35A
B7
PT
34B
F12
PT
34A
D10
PT
33B
H11
PT
33A
G11
PT
32B
A6
PT
32A
B6
PT
31B
D8
PT
31A
C8
PT
30B
F11
PT
30A
E10
PT
28B
G10
PT
29A
D9
PT
29B
E9
PT
28A
H10
PT
27B
A5
PT
27A
B5
PT
26B
C7
PT
26A
D7
PT
25B
E8
PT
25A
F10
PT
24B
F8
PT
24A
H9
PT
23B
C5
PT
23A
D5
PT
22B
B4
PT
10B
C4
PT
10A
C3
PT
9B
A4
PT
9A
A3
PT
8B
B3
PT
8A
B2
PT
7B
D4
PT
7A
D3
PT
6B
C2
PT
6A
C1
PT
5B
G8
PT
5A
G7
PT
4B
E7
PT
4A
F7
PT
3B
E6
PT
3A
E5
PT
2B
/VR
EF
2_0
G6
PT
2A
/VR
EF
1_0
G5
PT
71A
C19
PT
71B
E19
PT
70A
B20
PT
70B
B21
PT
69A
B19
PT
69B
D19
PT
68A
E18
PT
68B
G17
PT
67A
F17
PT
67B
G19
PT
66A
A19
PT
66B
A20
PT
65A
D18
PT
65B
E17
PT
64A
A18
PT
64B
B18
PT
63A
G16
PT
63B
E16
PT
62A
H18
PT
62B
F16
PT
61A
B17
PT
61B
A17
PT
60A
B16
PT
59B
C17
PT
58B
E15
PT
57B
A16
PT
56B
D15
PT
55B
A14
PT
54B
C15
PT
53B
A13
PT
52B
H17
PT
51B
D13
PT
50B
G14
PT
49B
A12
PC
LK
C1_0/P
T48B
F14
PT
60B
C18
PT
59A
D17
PT
58A
G15
PT
57A
B15
PT
56A
F15
PT
55A
B14
PT
54A
A15
PT
53A
B13
PT
52A
H15
PT
51A
C14
PT
50A
E14
PT
49A
B12
PC
LK
T1_0/P
T48A
D14
PT
37B
A8
PT
38A
G12
PT
39A
B9
PT
39B
A9
PT
40A
H12
PT
40B
G13
PT
41A
C10
PT
41B
C12
PT
42A
B10
PT
42B
A10
PT
43A
F13
PT
43B
D12
PT
44A
E13
PT
44B
C13
PT
45A
B11
PT
45B
A11
PT
46A
/PC
LK
T0_0
H13
PT
46B
/PC
LK
C0_0
H14
PT
74A
A21
PT
74B
A22
PT
75A
D20
PT
75B
C20
PT
76A
B23
PT
76B
B22
PT
77A
E20
PT
77B
C22
PT
78A
F19
PT
78B
E21
PT
79A
A23
PT
79B
A24
PT
80A
H19
PT
80B
F20
PT
81A
J18
PT
81B
G20
VR
EF
1_1/P
T82A
D22
VR
EF
2_1/P
T82B
E23
XR
ES
H16
PT
38B
E12
100n
C0
220
X2 HD
R2
12
100n
C0
214
X1
12
37
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 10. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
JTA
G_
DO
NE
SIS
PI
CC
LK
CS
SP
IN
CF
G2
CF
G1
CF
G0
JTA
G_
INIT
PR
OG
RA
M#
MA
CH
XO
_IO
[15
:0]
MA
CH
XO
_CLK
0
GP
_A
DR
8U
SB
CF
_W
AK
E
US
BC
F_
PU
SB
CF
_M
US
BC
F_
I2C
_S
DA
US
BC
F_
I2C
_S
CL
US
B_
CL
K_
O
GP
_IN
T0
GP
_IN
T1
GP
_BK
PT
GP
_CT
L5
GP
_CT
L0G
P_C
TL1
GP
_CT
L2
GP
_CT
L4G
P_C
TL3
GP
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EG
P_
WU
2G
P_
FIF
OA
DR
0G
P_
FIF
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DR
1
GP
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CL
K
GP
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KT
EN
DG
P_
SLC
S#
GP
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GP
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GP
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GP
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0G
P_
RD
Y1
GP
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2G
P_
RD
Y3
GP
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Y5
GP
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D0
GP
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D0
GP
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D1
GP
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GP
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0G
P_
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_D
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R1
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R3
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JTA
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CK
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6
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3
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GP
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8
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4
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7G
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GP
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9
GP
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10
GP
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GP
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GP
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GP
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L3
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L2G
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GP
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GP
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1
GP
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DY
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L5
GP
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11
GP
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ND
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GP
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CL
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0
CLK
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ON
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[45
:0]
HP
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1
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SP
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ALL
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7
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10
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11
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12
MA
CH
XO
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13
MA
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14
MA
CH
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15
MA
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1
HO
LD
#C
CL
KW
P#
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SS
PIN
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PI
JTA
G_T
CK
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G_T
DO
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G_T
MS
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DI
VC
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GN
D
VC
C3
V3
VC
C3
V3
VC
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F
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D
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FG
ND
P
VC
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GN
D
GN
D
VC
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V3
VC
C3
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FG
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F
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D
GN
D
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C3
V3
VC
C3
V3
VC
C3
V3
VC
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V3
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D
VC
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GN
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VC
C3
V3
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D
VC
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V3
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V3
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VC
C3
V3
VC
C3
V3
VC
C1
V2
VC
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V3
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D
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D
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C3
V3
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D
VC
C3
V3
GN
DG
ND
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D
GN
D
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D
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V3
GN
D
GN
DG
ND
GN
D
VC
C3V
3_T
VC
C2V
5_T
VC
C5
V0
VC
C1V
2_T
MA
CH
XO
_IO
[15
:0]
2
MA
CH
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02
CLK
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CH
XO
6
EX
PC
ON
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[45
:0]
2,9
HP
E_
RE
SE
T#
2,6 U
SB
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CL
7U
SB
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DA
7
MA
CH
XO
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12
:te
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S:tc
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P Au
tho
rs:
Gle
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Ele
ctro
nics
Re
visi
on
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
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stra
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119
A-4
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nim
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pH cs
amR
01
Sa
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9,
20
06
10
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Mo
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Se
pte
mb
er
04
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00
61
7:1
5:0
9
123
Latti
ce E
CP
2-50
FP
GA
(C
onfig
urat
ion)
Offp
age
M25P16-VMF6P 16Mb
Place the 4k7 resistors
close to their clock
line to keep the stub
length as short as
possible.
US
B-J
TA
G P
rogr
amm
er C
onne
ctor
USB Peripheral
for Configuration
JTAG Connector
for Configuration
CCLK
0 1
CFG2
0Reserved
Mode
1
INIT#
00
1
0
DONE
10
SPI Normal
1
000
SPI Fast
Drain
PROGRAM#
0l
amr
oN
mIPS
0
Con
figur
atio
n S
ettin
gs
Source
Reserved
SOT-23
CFG0
1Reserved
0 0SPIm Fast
Gate
CFG1
DOUT
SPIFAST#
Pull-Down
Pull-Up
X
Pull-Down
Pull-Up
X XSlave Serial
10
XReserved
1 11
0X
00
TSALL
Tes
t A
dapt
er
SP
I F
lash
for
Con
figur
atio
n
rev 1.1
RJ0
30
40
R0
0
1 2
100n
C0
31
3
TP
0305
R0
30
82
70
R
12
1n00
C0
30
1
100n
C0
320
RJ0
30
3nb
_10K
0
1 2
100n
C0
319
5n60
C0
32
6
T03
01B
SS
138/
SO
T
U0
30
1
CY
7C
68
01
3A
_T
QF
P1
00
VC
C1
VC
C33
VC
C38
VC
C49
VC
C53
VC
C66
VC
C78
VC
C85
VC
C20
GN
D2
GN
D21
GN
D39
GN
D48
GN
D50
GN
D65
GN
D75
GN
D94
GN
D99
AV
CC
16
AG
ND
19
AG
ND
12
AV
CC
9
PA
0/IN
T0
67
PA
1/IN
T1
68
PA
2/S
LO
E69
PA
3/W
U2
70
PA
4/F
IFO
AD
R0
71
PA
5/F
IFO
AD
R1
72
PA
6/P
KT
EN
D73
PA
7/F
LA
GD
/SLC
S74
PB
0/F
D0
34
PB
1/F
D1
35
PB
2/F
D2
36
PB
3/F
D3
37
PB
4/F
D4
44
PB
5/F
D5
45
PB
6/F
D6
46
PB
7/F
D7
47
PD
0/F
D8
80
PD
1/F
D9
81
PD
2/F
D10
82
PD
3/F
D11
83
PD
4/F
D12
95
PD
5/F
D13
96
PD
6/F
D14
97
PD
7/F
D15
98
PC
0/G
PIF
AD
R0
57
PC
1/G
PIF
AD
R1
58
PC
2/G
PIF
AD
R2
59
PC
3/G
PIF
AD
R3
60
PC
4/G
PIF
AD
R4
61
PC
5/G
PIF
AD
R5
62
PC
6/G
PIF
AD
R6
63
PC
7/G
PIF
AD
R7
64
PE
0/T
0O
UT
86
PE
1/T
1O
UT
87
PE
2/T
2O
UT
88
PE
3/R
XD
0O
UT
89
PE
4/R
XD
1O
UT
90
PE
5/IN
T6
91
PE
6/T
2E
X92
PE
7/G
PIF
AD
R8
93
RD
Y0/S
LR
D3
RD
Y1/S
LW
R4
RD
Y2
5
RD
Y3
6
RD
Y4
7
RD
Y5
8
XT
ALIN
11
XT
ALO
UT
10
RE
SE
T77
NC
13
NC
14
NC
15
RE
SE
RV
ED
27
DP
LU
S17
DM
INU
S18
CT
L0/F
LA
GA
54
CT
L1/F
LA
GB
55
CT
L2/F
LA
GC
56
CT
L3
51
CT
L4
52
CT
L5
76
INT
422
INT
584
T0
23
T1
24
T2
25
WA
KE
UP
79
RX
D0
41
TX
D0
40
RX
D1
43
TX
D1
42
SC
L29
SD
A30
BK
PT
28
CLK
OU
T100
IFC
LK
26
RD
31
WR
32
RJ0
30
20
R0
0
1 2
100n
C0
316
100n
C0
30
2
R0
314
10K
0
1 2
100n
C0
30
91n
00C
03
15
Q03
0124
MH
z 12
RJ0
30
8n
b_
0R00
1 2
100n
C0
30
4
12p0
C0
34
0
RJ0
31
010
K0
1 2
+C
03
24
4u70
1 2
+C
03
07
2u20
1 2
100n
C0
30
810
0nC
03
11
100n
C0
321
100n
C0
318
X23
Te
stC
on
tact
TV
i0
TV
i1
TV
i2
TV
i3
TV
o0
TV
o1
TV
o2
TV
o3
TP
0T
P1
TP
2T
P3
TP
4T
P5
TP
6T
P7
TP
8T
P9
TP
10
TP
11
TP
12
TP
13
TP
14
TP
15
TP
16
GN
D
100n
C0
322
RJ0
30
1nb
_10K
0
1 2
12p0
C0
33
9
TP
0307
SW
0302
CA
S-1
20AA
1
B3
C2
X3 US
B P
eri
phe
ral
VC
C1
DA
TA
-2
DA
TA
+3
GN
D4
SH
IELD
5
SH
IELD
6
100n
C0
31
0
FB
030
2B
LM18
PG
600S
N1
12
RJ0
30
5nb
_10K
0
1 2
R0
301
4k7
0
1 2
TP
0303
R0
30
52
70
R
12
R0
31
710
K0
1 2
1n00
C0
323
LD
030
3L
ED
ye
llow
RJ0
30
60
R0
0
1 2
X4 CO
N1
01 2 3 4 5 6 7 8 9 10
TP
0310
U0
305
M25
P16
CLK
16
DI
15
NC
14
GN
D10
WP
9
NC
13
NC
12
NC
11
HO
LD
1
VC
C2
NC
3
NC
4
NC
5
NC
6
CS
7
Q8
R0
31
610
K0
1 2
100n
C0
31
2
R0
307
4k7
0
1 2
100n
C0
31
4
R0
304
10K
0
1 2
BANK 0/0,1
BANK 1/2,3
BANK 2/4,5
BANK 3/6,7
U0
302
MA
CH
XO
-64
0/12
00-1
32cs
BG
A
PL2A
B1
PL2B
/PL3C
C1
PL3A
/PL3D
C3
PL3B
/PL4B
D1
PL3D
/PL4C
D3
PL5A
/PL6A
E2
VC
CIO
1/V
CC
IO3
L12
(GS
RN
) P
L5B
/PL6B
E3
PB
5D
/PB
7C
N8
PB
5B
/PB
7B
(P
CLK
T)
M7
PB
5A
/PB
6F
N7
SLE
EP
NN
12
PB
6A
/PB
7D
P8
PB
6B
/PB
7F
(P
CLK
T)
M8
PB
4F
/PB
6A
M6
PB
4E
/PB
5C
N6
VC
CP
6
PB
3B
M4
PB
3C
/PB
4A
N4
GN
DF
1
VC
CIO
3/V
CC
IO7
D2
PL9B
/PL12A
K2
PB
2C
M3
PB
2D
N3
PL7C
/PL10B
H1
PL8A
/PL11B
J1
PL9A
/PL11D
J3
VC
CIO
1/V
CC
IO2
E12
VC
CIO
3/V
CC
IO6
K3
PL5D
/PL6D
F2
PL6B
/PL7C
F3
PL7A
/PL8D
G3
PL7B
/PL10A
H2
PR
3C
/PR
4A
D12
PR
4D
/PR
6A
F12
PR
4C
/PR
5B
E13
PR
2B
/PR
3C
C13
VC
CIO
0/V
CC
IO1
B11
PR
2A
/PR
2A
A14
PT
9C
/PT
10F
B12
PT
5B
/PT
6F
(P
CLK
T)
C8
PT
5A
/PT
6D
B7
PT
6B
/PT
7D
(P
CLK
T)
A8
PT
6A
/PT
7B
B8
PT
4D
/PT
5D
A6
PT
4C
/PT
5C
B6
GN
DP
9
PT
3D
/PT
4B
A5
VC
CA
UX
P7
VC
CH
3
PT
3B
/PT
3D
A4
VC
CIO
0/V
CC
IO0
C5
VC
CIO
2/V
CC
IO4
M10
PT
2F
/PT
3C
C4
PT
2D
/PT
3B
A3
PT
2C
/PT
2B
A2
PT
2B
/PT
3A
B3
PT
2A
A1
PR
11A
/PR
15A
M12
PR
10B
/PR
14B
M13
PR
8B
/PR
11B
K12
PR
8A
/PR
11A
J13
PR
10A
/PR
14A
L14
PR
7C
/PR
10B
J12
PR
7B
/PR
10A
H14
PR
7A
/PR
9B
H13
PR
6B
/PR
8A
G14
VC
CIO
2/V
CC
IO5
N2
PR
8D
/PR
12B
K14
PR
5D
/PR
6C
F14
PR
5C
/PR
6B
F13
PR
8C
/PR
12A
K13
PR
6D
/PR
9A
H12
PR
4B
/PR
5A
E14
PR
6C
/PR
8B
G13
PR
3D
/PR
4B
D14
VC
CG
12
VC
CC
7
GN
DJ1
4G
ND
C9
GN
DIO
0/G
ND
IO1
A10
GN
DIO
0/G
ND
IO0
B4
GN
DIO
1/G
ND
IO3
L13
GN
DIO
1/G
ND
IO2
D13
GN
DIO
2/G
ND
IO5
P2
GN
DIO
2/G
ND
IO4
N11
GN
DIO
3/G
ND
IO7
E1
GN
DIO
3/G
ND
IO6
L2
PL2C
/PL2B
B2
PL2D
/PL4A
C2
PL6C
/PL7D
G1
PL6D
/PL8C
G2
(TS
ALL)
PL8C
/PL11C
J2
PL9C
/PL12B
K1
PL10B
/PL14B
L3
PL10A
/PL14A
L1
PL11A
/PL15A
M1
PL11B
/PL16A
N1
PL11C
/PL15B
M2
PL
11
D/P
L1
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9C
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BANK 8
AUX & PLL POWERBANK 9
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J11
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J16
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J17
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K18
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L18
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CA
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T18
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U18
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V17
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138/
SO
T
TP
0311
RJ0
30
9nb
_10K
0
1 2
38
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 11. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
ME
MO
RY
_A
[22
:0]
ME
MO
RY
_D
Q[3
1:0
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FL
AS
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T#
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ME
MO
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ME
MO
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5:0
]
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MO
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MO
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ME
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Series Resistors
Parallel Termination Resistors
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pin
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pin
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each end of the VTT island. (C04??, C04??)
(2 x
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128 Megabit
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04
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39
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 12. 5 5
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04
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day,
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tem
ber 0
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006
17
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125
8x L
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gle
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40
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 13. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
HP
E_R
ES
ET
#
CA
T_
VS
EN
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I2C
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3
:te
eh
S:t c
ejor
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tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
visi
on
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
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& C
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GH
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stra
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119
A-4
232
Hag
enbe
rgo
fP
age
tes
eR
_kcol
C_
60
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EL i
nim
_e
pH cs
amR
01
Fri
da
y, S
ep
tem
be
r 2
4,
20
04
12
:38
:11
Mon
day,
Sep
tem
ber 0
4, 2
006
17
:15
:09
126
Ext
. R
ese
t
Re
set
Bu
tto
n
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41
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 14. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
RS
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S:t c
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
visi
on
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
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ße
119
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232
Hag
enbe
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age
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e_
min
i LE
C2
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y, S
ep
tem
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4,
20
04
12
:34
:50
Mon
day,
Sep
tem
ber 0
4, 2
006
17
:15
:10
127
Offp
age
RS
232
Inte
rfac
e
US
B C
ontr
olle
r
GPIO30
GPIO31
Boot Configuration Interface
Host Port Interface (HPI)
High-Speed Serial (HSS)
Serial Peripheral Interface (SPI)
I2C EEPROM (Standalone Mode)
00 1 0
10 11
SDA
SCL
1500mA
330 Ohm @ 100 MHz
USB OTG
USB HOST
USB HOST
USB HOST
C0
70
71u
00
100n
C0
701
EXT MEMORY
EXT MEMORY CONTROL
GPIO
USB PORTS
CHARGE PUMP
RESET / CLOCK
POWER
U0
70
2
CY
7C
67
30
0_
TQ
FP
10
0
A1
1
A2
2
A4
7A
33
A6
17
A5
8
A8
24
A9
25
A7
20
A10
27
A11
30
A12
31
A13
32
A14
33
A15/C
LK
SE
L38
A16
97
A17
95
A18
96
D0
83
A0/B
EL
99
D1
82
D2
81
D3
80
D4
79
D5
78
D6
77
D7
76
D8/M
ISO
74
D9/S
SI
73
D10/S
CK
72
D11/M
OS
I71
D12/T
XD
70
D13/R
XD
69
D14/R
TS
68
D15/C
TS
67
BE
H98
WR
64
RD
62
ME
MS
EL
34
RO
MS
EL
35
RA
MS
EL
36
GP
IO0/D
094
GP
IO1/D
193
GP
IO2/D
292
GP
IO3/D
391
GP
IO4/D
490
GP
IO8/M
ISO
/D8
66
GP
IO7/D
786
GP
IO6/D
687
GP
IO9/S
SI/D
965
GP
IO5/D
589
GP
IO10/S
CK
/D10
61
GP
IO11/M
OS
I/D
11
60
GP
IO12/D
12
59
GP
IO13/D
13
58
GP
IO14/D
14
57
GP
IO15/S
SI/D
15
56
GP
IO16/T
XD
/I_A
055
GP
IO17/R
XD
/I_A
154
GP
IO18/R
TS
/I_A
253
GP
IO19/C
S0/H
_A
052
GP
IO20/C
S1/H
_A
150
GP
IO21/n
CS
49
GP
IO22/W
R/IO
W48
GP
IO23/R
D/IO
R47
GP
IO24/IN
T/IO
RD
Y46
GP
IO25
45
GP
IO26/C
TS
/PW
M3
44
GP
IO27/R
X43
GP
IO28/T
X42
GP
IO29/O
TG
ID41
GP
IO30/S
CL
40
GP
IO31/S
DA
39
VC
C88
VC
C63
VC
C37
GN
D100
GN
D75
GN
D51
GN
D26
DM
1A
22
DP
1A
23
DP
1B
19
DM
1B
18
DM
2B
4D
P2A
10
DM
2A
9
DP
2B
5
AV
CC
21
AG
ND
6
XT
ALIN
29
XT
ALO
UT
28
RE
SE
T85
RE
SE
RV
ED
84
BO
OS
TV
CC
16
VS
WIT
CH
14
BO
OS
TG
ND
15
OT
GV
BU
S11
CS
WIT
CH
A13
CS
WIT
CH
B12
R0
704
10K
0
1 2
X11
B
US
B_
Typ
eA
/Ho
st
VC
C1B
DA
TA
-2B
DA
TA
+3B
GN
D4B
SH
IELD
15
SH
IELD
16
Q07
01C
RY
ST
AL
_1
2M
Hz
12R
J07
01
nb_1
0K0
1 2
10u0
C0
71
710
0nC
07
19
nb_1
00n
C0
727
RJ0
70
40
R0
0
1 2
R0
705
10K
0
1 2
100n
C0
703
100n
C0
71
4
D0
70
1B
AT
54S
3
12
FB
070
4B
LM18
PG
600S
N1
12
R0
701
0R
00
12
FB
070
5B
LM
21P
G33
1SN
1D
1 2
X11
C
US
B_
Typ
eA
/Ho
st
VC
C1C
DA
TA
-2C
DA
TA
+3C
GN
D4C
X9 CO
N_
DS
UB
_9
M
162738495
+C
07
13
100u
U0
704
SP
252
6-1E
N
EN
A1
FLG
A2
FLG
B3
EN
B4
OU
TB
5
GN
D6
IN7
OU
TA
8
C0
71
522
p0
100n
C0
71
1
100n
C0
705
100n
C0
70
9
FB
070
3
BL
M21
PG
331S
N1D
12
R0
703
47K
0
12
C0
716
22p0
100n
C0
72
1
R0
707
10K
0
1 2
100n
C0
70
4
+C
07
10
100u
10u0
C0
702
100n
C0
72
0
R0
706
15K
0
1 2
C0
726
4u70
R0
702
0R
00
12
+C
07
08
100u
U0
701
MA
X32
32/T
SS
OP
C1+
1
C1-
3
C2+
4
C2-
5
V+
2
V-
6
T1IN
11
T2IN
10
R1IN
13
R2IN
8
T1O
UT
14
T2O
UT
7
R1O
UT
12
R2O
UT
9
VC
C16
GN
D15
C0
71
21u
00
RJ0
70
3nb
_10K
0
1 2
U0
703
SP
252
6-1E
N
EN
A1
FLG
A2
FLG
B3
EN
B4
OU
TB
5
GN
D6
IN7
OU
TA
8
100n
C0
724
FB
070
2
BL
M21
PG
331S
N1D
12
X10
US
B m
iniA
B 4
40
47
9-1
VB
US
1
D-
2
D+
3
ID4
GN
D5
SH
16
SH
27
SH
38
SH
49
R0
708
nb_1
M00
12
100n
C0
706
FB
070
1
BL
M21
PG
331S
N1D
12
C0
725
100n
X11
A
US
B_
Typ
eA
/Ho
st
VC
C1A
DA
TA
-2A
DA
TA
+3A
GN
D4A
SH
IELD
13
SH
IELD
14
1n00
C0
723
100n
C0
722
100n
C0
71
8
RJ0
70
20
R0
0
1 2
42
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 15. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
ET
H_T
XD
0
ET
H_T
XC
LK0
ET
H_R
XE
RE
TH
_RX
D3
ET
H_R
XD
2
ET
H_R
XD
0
ET
H_R
XC
LK0
ET
H_R
XD
V
ET
H_
CR
SE
TH
_C
OL
ET
H_
MD
IO
ET
H_R
XD
1
ET
H_T
X-
ET
H_R
X-
CL
K_
ET
H
ET
H_R
X+
LAN
_TX
+
ET
H_
MD
INT
R#
ET
H_
CF
G3
ET
H_
CF
G1
ET
H_
CF
G3
LAN
_TX
-
LAN
_RX
+ LAN
_RX
-
ET
H_T
XE
RE
TH
_TX
D3
ET
H_T
XD
1E
TH
_TX
D0
ET
H_T
XE
NE
TH
_TX
CLK
ET
H_R
XE
RE
TH
_RX
D3
ET
H_R
XD
2
ET
H_R
XD
0
ET
H_R
XC
LKE
TH
_RX
DV
ET
H_
CR
SE
TH
_C
OL
ET
H_R
XD
1
ET
H_T
XD
2
ET
H_
MD
CE
TH
_M
DIO
ET
H_
MD
INT
R#
ET
H_T
X+
ET
H_T
XC
LK
ET
H_R
XC
LK
ET
H_T
XD
1E
TH
_TX
D2
ET
H_T
XD
3
ET
H_T
XE
N
ET
H_T
XE
R
ET
H_
MD
C
HP
E_
RE
SO
UT
#
HP
E_
RE
SO
UT
#
ET
H_
CF
G2
ET
H_
CF
G1
ET
H_
CF
G2
CL
K_
ET
H
VC
C3
V3
VC
C3
V3
_L
AN
VC
C3
V3
_L
AN
VC
C3
V3
VC
C3
V3
_L
AN
VC
C3
V3
VC
C3
V3
GN
D
GN
D
GN
D_
LA
N
GN
D_
LA
N
GN
D
GN
D
GN
D
GN
DP
GN
D
GN
D
VC
C3
V3
VC
C3
V3
VC
C3
V3
GN
D_
LA
NG
ND
P
GN
D
ET
H_T
XE
R2
ET
H_T
XD
32
ET
H_T
XD
22
ET
H_T
XD
12
ET
H_T
XD
02
ET
H_T
XE
N2
ET
H_T
XC
LK2
ET
H_R
XE
R2
ET
H_R
XD
32
ET
H_R
XD
22
ET
H_R
XD
12
ET
H_R
XD
02
ET
H_R
XC
LK2
ET
H_R
XD
V2
ET
H_
CR
S2
ET
H_
CO
L2
ET
H_
MD
INT
R#
2
ET
H_
MD
C2
ET
H_
MD
IO2
HP
E_
RE
SO
UT
#2
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CL
K_
ET
H6
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eh
S:t c
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Gle
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Ele
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Re
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Res
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stra
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119
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the
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R0
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day,
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tem
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006
17
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128
Offp
age
Eth
erne
t
2kV
2kV
2kV
TxSLEW1
TxSLEW0
0 10 110 10
Slew Rate
2.5ns
3.1ns
3.7ns
4.3ns
R0
810
49
R9
1 2
C0
806
1n00
1 2
R0
80
84
9R
9
12
R0
81
622
K1 1
2
R0
80
12
20
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12
R0
81
32
20
R
12
R0
802
22
R0
12
C0
801
270p
12
C0
802
270p
12
R0
80
5nb
_10K
0
1 2
R0
81
810
K0
12
R0
804
nb_1
0K0
1 2
C0
810
220n 1 2
LE
D08
01L
ED
re
d
1 2
RJ0
80
5nb
_10K
0
1 2
C0
80
510
n0
1 2
RJ0
80
3nb
_10K
0
1 2
R0
809
49
R9
1 2
C0
809
220n
12
U0
802
PU
LS
E H
11
12
RD
+5
RD
-6
CT
_R
D4
TD
+1
TD
-2
CT
_T
D3
RX
+8
RX
-7
CT
_R
X9
TX
+12
TX
-11
CT
_T
X10
R0
80
74
9R
9
12
C0
80
410
0n
1 2
R0
817
10K
0
12
C0
80
71n
00
1 2
R0
81
54
9R
9
1 2
U0
801
LXT
971A
TX
_E
R54
TX
D3
60
TX
D2
59
TX
D1
58
TX
D0
57
TX
_E
N56
TX
_C
LK
55
MD
C43
MD
IO42
RX
D3
45
RX
D2
46
RX
D1
47
RX
D0
48
MD
INT
#64
RX
_C
LK
52
CR
S63
CO
L62
RX
_D
V49
RX
_E
R53
RE
SE
T#
4
TP
FO
P19
TP
FO
N20
TP
FIP
23
TP
FIN
24
LE
D/C
FG
138
PW
RD
WN
39
VC
CD
51
VC
CIO
8
VC
CIO
40
VC
CA
21
DG
ND
7D
GN
D11
DG
ND
18
AD
DR
416
TD
I27
RE
FC
LK
/XI
1
XO
2
MD
DIS
3
VC
CA
22
DG
ND
25
DG
ND
41
DG
ND
50
DG
ND
61
SD
/TP
26
TxS
LE
W0
5
TxS
LE
W1
6
RB
IAS
17
LE
D/C
FG
237
LE
D/C
FG
336
TD
O28
TM
S29
TC
K30
TR
ST
31
AD
DR
315
AD
DR
214
AD
DR
113
AD
DR
012
PA
US
E33
SLE
EP
32
TE
ST
034
TE
ST
135
nc
9
nc
10
nc
44
RP
080
21
0k0
18273645
C0
803
100n
1 2
RP
080
11
0k0
18273645
C0
81
310
n0 1 2
R0
806
22
R0
12
FB
080
2B
LM18
PG
600S
N1
12
RJ0
80
610
K0
12
R0
812
49
R9
1 2
R0
81
14
9R
9
1 2
X12
RJ-
45
-LE
D
TX
+1
TX
-2
RX
+3
nc
4
nc
5
RX
-6
nc
7
nc
8
SH
IELD
13
SH
IELD
14
LE
D2-
10
LE
D2+
9
LE
D1-
12
LE
D1+
11
R0
81
44
9R
9
1 2
C0
80
81n
00
1 2
RJ0
80
1nb
_10K
0
1 2
FB
080
1B
LM11
B75
0S
12
RJ0
80
410
K0
12
R0
803
22
0R
12
RJ0
80
210
K0
12
43
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 16. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
EX
PC
ON
_IO
1E
XP
CO
N_I
O3
EX
PC
ON
_IO
5E
XP
CO
N_I
O7
EX
PC
ON
_IO
9E
XP
CO
N_I
O11
EX
PC
ON
_IO
13E
XP
CO
N_I
O15
EX
PC
ON
_IO
20
EX
PC
ON
_IO
23
EX
PC
ON
_IO
26
EX
PC
ON
_IO
0E
XP
CO
N_I
O2
EX
PC
ON
_IO
4E
XP
CO
N_I
O6
EX
PC
ON
_IO
8E
XP
CO
N_I
O10
EX
PC
ON
_IO
12E
XP
CO
N_I
O14
EX
PC
ON
_IO
16E
XP
CO
N_I
O17
EX
PC
ON
_IO
18E
XP
CO
N_I
O19
EX
PC
ON
_IO
21E
XP
CO
N_I
O22
EX
PC
ON
_IO
24E
XP
CO
N_I
O25
EX
PC
ON
_IO
27E
XP
CO
N_I
O28
HP
E_
RE
SO
UT
#
CA
RD
SE
L#
CA
RD
SE
L#
EX
PC
ON
_C
LK
INE
XP
CO
N_C
LKO
UT
EX
PC
ON
_OS
C
HP
E_
RE
SO
UT
#
BB
3V
3_
IO[2
1:0
]
BB
3V
3_
IO[2
1:0
]
EX
PC
ON
_3V
3
EX
PC
ON
_IO
[45
:0]
BB
3V3_
CLK
0+B
B3
V3_
CLK
0-
EX
PC
ON
_IO
39E
XP
CO
N_I
O37
EX
PC
ON
_IO
35E
XP
CO
N_I
O33
EX
PC
ON
_IO
31E
XP
CO
N_I
O29
EX
PC
ON
_IO
30E
XP
CO
N_I
O32
EX
PC
ON
_IO
34E
XP
CO
N_I
O36
EX
PC
ON
_IO
38
EX
PC
ON
_2V
5
EX
PC
ON
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CE
XP
CO
N_
CL
KIN
EX
PC
ON
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T
EX
PC
ON
_3V
3
EX
PC
ON
_IO
40E
XP
CO
N_I
O41
EX
PC
ON
_IO
42E
XP
CO
N_I
O43
EX
PC
ON
_IO
44E
XP
CO
N_I
O45
BB
3V
3_IO
3
BB
3V
3_IO
2
BB
3V
3_IO
1
BB
3V
3_IO
0
BB
3V
3_IO
4
EX
PC
ON
_2V
5
BB
3V
3_IO
5
BB
3V
3_IO
6
BB
3V
3_IO
7
BB
3V
3_IO
8
BB
3V
3_IO
9
BB
3V
3_IO
10
BB
3V
3_IO
11
BB
3V
3_IO
12
BB
3V
3_
IO[2
1:0
]
BB
3V
3_IO
13
BB
3V
3_IO
14
BB
3V
3_IO
15
BB
3V
3_IO
16
BB
3V
3_IO
17
BB
3V
3_IO
18
BB
3V
3_IO
19
BB
3V
3_IO
20
BB
3V
3_IO
21
BB
3V
3_C
LK0-
BB
3V3_
CLK
0+
SA
TA
_XT
2D0+
SA
TA
_XT
2D0-
SA
TA
_XT
1D0-
SA
TA
_XT
1D0+
SA
TA
_XT
1D1-
SA
TA
_XT
1D1+
SA
TA
_XT
2D1-
SA
TA
_XT
2D1+
SA
TA
_X1D
1+S
AT
A_X
1D1-
SA
TA
_X2D
0+S
AT
A_X
2D0-
SA
TA
_X1D
0+S
AT
A_X
1D0-
SA
TA
_X2D
1+S
AT
A_X
2D1-
SA
TA
_X2D
1+S
AT
A_X
2D1-
SA
TA
_XT
2D0-
SA
TA
_XT
2D0+
SA
TA
_X2D
0+S
AT
A_X
2D0-
SA
TA
_XT
1D1-
SA
TA
_XT
1D1+
SA
TA
_XT
1D0+
SA
TA
_XT
1D0-
SA
TA
_X1D
0-S
AT
A_X
1D0+
SA
TA
_X1D
1+S
AT
A_X
1D1-
SA
TA
_XT
2D1-
SA
TA
_XT
2D1+
VC
C3
V3
GN
DG
ND
VC
C3
V3
GN
D
VC
C2
V5
GN
D
GN
D
VC
C3
V3
VC
C5
V0
GN
DG
ND
_H
S
GN
D_
HS
CA
RD
SE
L#
2
EX
PC
ON
_C
LK
IN2
EX
PC
ON
_CLK
OU
T2
EX
PC
ON
_O
SC
6
HP
E_
RE
SO
UT
#2
,6,7
,8
BB
3V
3_
IO[2
1:0
]2
EX
PC
ON
_IO
[45
:0]
2
BB
3V3_
CLK
0+2
BB
3V
3_C
LK0-
2
SA
TA
_X1D
1+2
SA
TA
_X1D
1-2
SA
TA
_X2D
0+2
SA
TA
_X2D
0-2
SA
TA
_X1D
0+2
SA
TA
_X1D
0-2
SA
TA
_X2D
1+2
SA
TA
_X2D
1-2
:te
eh
S:t c
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
visi
on
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
stra
ße
119
A-4
232
Hag
enbe
rgo
fP
age
Hp
e_
min
i LE
C2
09
_E
xpC
on
_P
roto
Are
a
csam
R0
1
Tu
esd
ay,
De
cem
be
r 1
4,
20
04
14
:28
:58
Mon
day,
Sep
tem
ber 0
4, 2
006
17
:15
:10
129
Offp
age
Exp
ansi
on C
onne
ctor
Pro
toty
ping
Are
a (R
M2.
54)
of F
PG
A
Pin 2 removed for coding
of expansion board
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Place the 0402-resistors of the LVDS termination
as close as possible to the FPGA.
LVDS
DIFF
Sternpunkt X16
SA
TA
-Con
nect
or
TP
0910
4
TP
0935
TP
0996
TP
0912
TP
0963
TP
0912
4
TP
0954
TP
0911
7
TP
0944
TP
0908
TP
0910
6
R0
907
0R
00
12
TP
0936
TP
0921
TP
0964
TP
0986
TP
0912
5
R0
901
0R
00
1 2
TP
0957
TP
0911
5
R0
909
nb
_10
0R
12
TP
0946
TP
0910
7
TP
0913
5
TP
0926
TP
0965
TP
0985
TP
0912
6
TP
0955
TP
0920
TP
0911
6
R0
914
0R
00
12
TP
0947
TP
0910
8
TP
0909
TP
0975
TP
0913
6
TP
0925
TP
0966
TP
0912
9
R0
915
nb
_10
0R
12
TP
0934
TP
0956
TP
0911
8
TP
0948
TP
0976
TP
0998
TP
0913
7
TP
0969
TP
0922
TP
0912
7
R0
913
0R
00
12
TP
0958
TP
0903
TP
0911
9
TP
0938
TP
0977
TP
0913
3
TP
0910
TP
0913
8
R0
910
0R
00
12
TP
0967
TP
0912
8
TP
0901
TP
0959
TP
0987
TP
0912
0
TP
0937
TP
0923
TP
0978
TP
0914
1
R0
911
0R
00
12
TP
0968
TP
0913
0
TP
0927
TP
0960
TP
0904
TP
0988
TP
0911
0
R0
916
0R
00
12
TP
0981
TP
0911
TP
0913
9
TP
0970
X13
HD
R4
0
12
34
56
78
910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TP
0924
TP
0913
1
X15
CO
N_
SA
TA
GN
D1
A+
2
A-
3
GN
D4
B-
5
B+
6
GN
D7
TP
0928
TP
0950
TP
0912
1
TP
0915
TP
0989
TP
0979
TP
0914
0
TP
0971
TP
0999
TP
0913
2
TP
0929
TP
0949
R0
908
0R
00
12
TP
0990
R0
904
10K
0
1 2
TP
0980
TP
0914
TP
0914
2
X14
HD
R4
0
12
34
56
78
910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TP
0939
TP
0972
TP
0916
TP
0910
0
TP
0905
TP
0912
2
TP
0930
TP
0993
TP
0982
TP
0914
3
TP
0940
TP
0962
R0
912
nb
_10
0R
12
TP
0910
9
TP
0910
1
TP
0933
TP
0913
X16
CO
N_
SA
TA
GN
D1
A+
2
A-
3
GN
D4
B-
5
B+
6
GN
D7
TP
0991
TP
0917
TP
0983
TP
0902
TP
0911
1
TP
0914
4
TP
0941
TP
0961
TP
0910
2T
P09
06
TP
0931
TP
0992
TP
0984
TP
0951
R0
905
0R
00
12
TP
0911
2
TP
0913
4
TP
0942
TP
0910
5
TP
0918
R0
90
20
R0
0
1 2
TP
0932
TP
0994
TP
0952
TP
0974
TP
0997
TP
0911
3
TP
0945
TP
0910
3T
P09
07
TP
0995
R0
906
nb
_10
0R
12
TP
0912
3
TP
0953
TP
0919
TP
0973
TP
0911
4
TP
0943
44
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 17. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
AC
97
_B
ITC
LKA
C9
7_S
DA
TA
_OU
T
AC
97
_S
YN
CA
C9
7_
SD
AT
A_
IN
AC
97_E
XT
_CLK
AC
97_
RE
SE
T#
AC
97
_E
AP
D
VG
A_
RD
0
VG
A_
GR
0
VG
A_B
L0
VG
A_
RD
1
VG
A_
GR
1
VG
A_B
L1
VG
A_
VS
YN
C
VG
A_
RD
0V
GA
_R
D1
VG
A_
GR
0
VG
A_B
L0V
GA
_G
R1
VG
A_
HS
YN
CV
GA
_BL1
VG
A_
VS
YN
C
VG
A_
HS
YN
C
VG
A_R
D_X
VG
A_G
R_X
VG
A_B
L_X
AC
97
_3
DN
AC
97
_S
PD
IF_
OU
T
AC
97
_3
DP
AC
97
_A
FIL
T1
AC
97
_A
FIL
T2
AC
97
_A
FIL
T3
AC
97
_S
YN
C
AC
97
_V
RE
FO
UT
AC
97
_S
DA
TA
_IN
AC
97_
SD
AT
A_O
UT
AC
97
_H
P_
OU
T_C
AC
97
_B
ITC
LK
AC
97
_E
AP
D
AC
97_
RE
SE
T#A
C9
7_
LIN
EIN
_R
AC
97
_L
INE
OU
T_L
AC
97_
AO
UT
_L
AC
97
_V
RE
F
AC
97
_P
IN4
8A
C9
7_
PIN
47
AC
97_X
TL_
OU
T
AC
97
_3
DF
LT
AC
97
_A
IN_
R
AC
97
_L
INE
OU
T_
RA
C9
7_
AO
UT
_RA
C9
7_
AIN
_L
AC
97
_H
P_O
UT
_L
AC
97
_H
P_
OU
T_R
AC
97_E
XT
_CLK
AC
97_X
TL_
IN
AC
97
_L
INE
IN_
L
GN
D
GN
DG
ND
A_
AU
D
GN
DA
_A
C
VD
D3
V3
_A
C9
7
GN
DA
_A
C
GN
DA
_A
C
VD
DA
5V
0_
AC
97
GN
DA
_A
C
GN
DA
_A
C
VC
C5
V0
VD
DA
5V
0_
AC
97
VD
DA
5V
0_
AC
97
GN
DA
_A
C
GN
DA
_A
C
GN
D
GN
DA
_A
C
GN
DA
_A
C
VD
D3
V3
_A
C9
7V
CC
3V
3
GN
D
GN
DA
_A
CG
ND
GN
DA
_A
C
GN
DA
_A
C
GN
DA
_A
C
GN
D
AC
97
_B
ITC
LK2
AC
97_
SD
AT
A_O
UT
2
AC
97
_S
YN
C2
AC
97_E
XT
_CLK
2A
C9
7_R
ES
ET
#2
AC
97
_E
AP
D2
VG
A_
RD
02
VG
A_
RD
12
VG
A_
GR
02
VG
A_
GR
12
VG
A_B
L02
VG
A_
HS
YN
C2
VG
A_B
L12
VG
A_
VS
YN
C2
AC
97
_S
DA
TA
_IN
2
:te
eh
S:t c
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
visi
on
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
stra
ße
119
A-4
232
Hag
enbe
rgo
fP
age
Hp
e_
min
i LE
C2
10_A
udio
_VG
A
csam
R0
1
Tu
esd
ay,
De
cem
be
r 1
4,
20
04
14
:11
:30
Mon
day,
Sep
tem
ber 0
4, 2
006
17
:15
:09
1210
Aud
io C
odec
VG
A I
nter
face
Offp
age
Headphone / Line-out
LINE-IN
Locate under CODEC
use 60 mil wide trace between
digital and analog GND planes
47n0
(AD1881)
PB-Free Part:
LM4549BVHX
10u0
(VT1612A)
100n
(VT1612A)
1u00
(AD1881)
1u00
(AD1881)
100n
(AD1881)
1n00
(CS4299)
10n0
(CS4299)
C0805
C0805
C0603
30
60
C3
06
0C
30
60
C
<---
<---
--->
--->
--->
PLL --->
LOCATE SEPERATE ANALOG POWER AND ANALOG GROUND
PLANES DIRECTLY ON TOP OF ONE ANOTHER WITHOUT
OVERLAPPING DIGITAL POWER OR GROUND PLANES. A SINGLE
ZERO OHM RESISTOR SHOULD LINK THE DIGITAL AND ANALOG
GROUND PLANES AS CLOSE TO THE CODEC AS POSSIBLE.
270p
(VT1612A)
270p
(VT1612A)
nb_10k0
(VT1612A)
Connect ANALOG GND to
GND on Plane
realized in CAMTASTIC
1u00 (CS4299)
3u30 (LM4480)
10u0 (VT1612A)
C0603
C0603
C1206
270p
(VT1612A)
R1
025
nb
_0R
00
R1
02
4n
b_
0R00
R1
023
nb
_0R
00
1u00
C1
017
FB
100
4B
LM
21P
G33
1SN
1D1
2
C1
02
8
33p0
nb_1
n00
C1
024
R1
02
71M
00
12
nb_1
00n
C1
02
210
0nC
10
12
R1
018
27
0R
R1
00
84
7k0
+
C1
002
1u00
12
LC
100
4N
FE
31
PT
222Z
1E9
21
3
22n0
C1
011
R1
012
27
0R
FB
100
3B
LM
21P
G33
1SN
1D1
2
C1
02
9
33p0
LC
100
2N
FE
31
PT
222Z
1E9
21
3
R1
021
33
R0
10u0
C1
013
1n00
C1
010
1n00
C1
008
nb_1
n00
C1
026
+
C1
003
1u00
12
R1
00
94
7k0
R1
022
nb
_0R
00
R1
013
27
0R
+
C1
001
1u00
12
100p
C1
007
TP
1001
LC
100
1N
FE
31
PT
222Z
1E9
21
3
100n
C1
019
TP
1002
1u00
C1
015
FB
100
5B
LM
21P
G33
1SN
1D1
2
R1
007
47
k010
0pC
10
06
TP
1003
NF
_R
NF
_L
Shi
eld
X17
A
ST
-423
5-3/
3-N
5L
1L
4L
2L
1
R1
01
42
70
R
R1
010
27
0R
100n
C1
01
6
FB
100
1B
LM18
PG
600S
N1
12
R1
019
10
k0
100n
C1
014
1n00
C1
004
R1
026
0R
00
12
+
C1
005
1u00
12
R1
015
27
0R
FB
100
6B
LM
21P
G33
1SN
1D1
2
FB
100
2B
LM18
PG
600S
N1
12
nb_1
n00
C1
02
5
R1
003
1k0
0
X19
CO
N_
DS
UB
_1
5F
7 2 8 3 9 410 516
11
12
13
14
15
R1
020
nb
_0R
00
nb_1
0u0
C1
023
nb_2
2n0
C1
021
R1
028
0R
0
Q10
01nb
_24.
576M
Hz
12
R1
002
0R
00
100n
C1
01
8
ANALOG
DIGITAL INTERFACE
POWER
CLOCK
U1
00
1
AC
'97
CO
DE
C
LIN
E_IN
_L
23
LIN
E_IN
_R
24
CD
_L
18
CD
_G
ND
19
CD
_R
20
MIC
121
MIC
222
VID
EO
_L
16
AU
X_R
15
PC
_B
EE
P12
AU
X_L
14
VID
EO
_R
17
LIN
E_O
UT
_R
36
XT
L_IN
2
XT
L_O
UT
3
PH
ON
E13
LIN
E_O
UT
_L
35
SD
AT
A_O
UT
5
DV
DD
29
DV
DD
11
AV
DD
25
AV
SS
26
DV
SS
14
DV
SS
27
BIT
_C
LK
6
SY
NC
10
RE
SE
T11
SD
AT
A_IN
8
HP
_O
UT
_L
39
HP
_O
UT
_R
41
MO
NO
_O
UT
37
VR
EF
OU
T28
RE
FF
LT
27
3D
P34
3D
N33
ID0
45
ID1
46
EA
PD
/NC
47
AF
ILT
1/N
C29
AF
ILT
2/N
C30
AF
ILT
3/N
C31
3D
FLT
/NC
32
NC
/AV
DD
38
HP
_O
UT
_C
/NC
40
AV
SS
/NC
42
NC
43
HP
P/N
C44
SP
DIF
/NC
48
R1
016
27
0R
R1
006
1k0
0
R1
004
47
k0
nb_1
00n
C1
020
NF
_R
NF
_L
Shi
eld
X17
B
ST
-423
5-3/
3-N
5U
1U
4U
3L
4
R1
01
12
70
R
R1
01
72
70
R
R1
005
0R
00
nb_1
u00
C1
02
7
1n00
C1
009
LC
10
03N
FE
31
PT
222Z
1E9
21
3
45
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 18. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
PW
_T1B
_GA
TE
PW
_SW
2_L
PW
_VO
S2
PW
_SW
2
PW
_BO
OS
T2
PW
_T2B
_GA
TE
PW
_T1A
_GA
TE
PW
_T2A
_GA
TE
VC
C_
KL
DP
W_B
OO
ST
1P
W_S
W1
VO
S1
PW
_SW
1_L
GN
DP
VC
C3
V3
VC
C5
V0
VC
C5
V0
GN
D_
PW
R
VC
C5
V0
GN
DG
ND
GN
D_
PW
RG
ND
_P
WR
GN
D
GN
D
GN
D_
PW
R
GN
D_
PW
RG
ND
_P
WR
GN
D
GN
D_
PW
R
GN
D_
PW
RGN
D_
PW
R
GN
D_
PW
R
GN
D_
PW
R
GN
D
GN
D
GN
D_
PW
R
GN
D_
PW
R
GN
D_
PW
R
GN
D
GN
D_
PW
R
GN
DP
VC
C5
V0
GN
D
GN
DG
ND
GN
DG
ND
GN
D
VC
C1
V2
VC
C2
V5
VC
C1V
2_T
VC
C3V
3_T
VC
C2V
5_T
:te
eh
S:tc
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
visi
on
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
stra
ße
119
A-4
232
Hag
enbe
rgo
fP
age
Hp
e_
min
i LE
C2
11
_P
ow
erS
uppl
y
csam
R0
1
Fri
da
y, S
ep
tem
be
r 1
0,
20
04
09
:11
:59
Mo
nd
ay,
Se
pte
mb
er
04
, 2
00
61
7:1
4:0
7
1211
3.3V
(1A
) /
1.2V
(2A
) D
C/D
C-C
onve
rter
Co
nn
ect
AN
AL
OG
GN
D t
oG
ND
on
Pla
ne
Offp
age
C7
34
3H
10V
20V
C7343
LE
SR
40
20V
C7343
Dri
ll
ma
x 1
A
1%1%
3.3
V
GN
D
1.2
V
3.3
V P
G
1% 1%
LE
SR
40
ma
x 2
A
10V
10V
C7
34
3H
Pla
ce th
e pa
rts
C11
03, C
1105
and
C11
24
as c
lose
as
poss
ible
to th
e pi
ns o
f the
U11
01
ext
ra A
NA
LO
G G
ND
pla
ne
con
ne
cte
d w
ith 6
Via
s to
GN
D o
n p
lan
e
2.5V
/2.6
V (
2A)
2.5
V
%1%1
1%
ma
x 2
.4A
2.5
V P
G
Mis
cella
ne
ou
s
Set the jumper to 1-2 for 2.5V and to 3-2 for 2.6V
(This is important for the DDR SDRAM module)
10u0
C1
12
9
R1
11
93
9k0
1 2
L110
1
33u0
+C
11
11
220u
100n
C1
11
6
nb_1
0n0
C1
11
3
Pla
ceH
old
erP
H1
103
21
R1
10
34
k70
12
X20
KL
D-0
202-
A
OU
TS
IDE
1
OP
EN
ER
2
CE
NT
ER
3
+C
11
0647
u0
DR
ILL
11
01
DR
ILL
Pla
ceH
old
erP
H1
101
21
D1
10
610
MQ
040N
12
R1
11
50
R0
331
2
100n
C1
102
TP
1102
TE
ST
PO
INT
1
L110
3
10u0
R1
11
10
R0
51
2
D1
103
10M
Q04
0N
12
LD
110
2L
ED
gre
en
10u0
C1
10
1
SI6
96
6D
QT
1101
A4
1 23
220p
C1
11
8
optional
Pad
1102
Art
Nr0
52
81
LD
110
1L
ED
gre
en
D1
104
MB
R05
40LT
1
1 2
nb_1
0n0
C1
12
5
R1
114
33
0R
12
+C
11
30
220u
optional
Pad
1101
Art
Nr0
52
81
optional
Pad
1105
Art
Nr0
52
81
R1
107
15K
012
4p70
C1
132
D1
101
MB
R05
40LT
1
1 2
SI6
96
6D
QT
1102
A4
1 23
Pla
ceH
old
erP
H1
102
21
R1
10
815
K0
12
100n
C1
124
SI6
96
6D
QT
1101
B5
8 76
R1
112
47K
0
12
D1
102
10M
Q04
0N
12
optional
Pad
1104
Art
Nr0
52
81
100n
C1
121
R1
11
61
0R
01
2
33p0
C1
12
2D
11
0510
MQ
040N
12
+C
11
0747
u0
S
DG
T11
03S
i34
45D
V3
4 1256
optional
Pad
1103
Art
Nr0
52
81
1u00
C1
134
R1
113
15K
0
12
TP
1104
TE
ST
PO
INT
1
R1
11
742
K2
1 2
10u0
C1
11
0
10u0
C1
13
1
L110
2
100u
0
33p0
C1
123
100n
C1
10
3
optional
A11
01Ju
mp
er
X21
HD
R3
123
R1
11
05
R1
0
12
R1
10
20
R0
25
12
TP
1103
TE
ST
PO
INT
1
R1
10
55
R1
0
12
100n
C1
120
U1
10
2
TP
S64
203D
BV
T
EN
1
GN
D2
FB
3
SW
6
VIN
5
ISE
NS
E4
optional
Labe
l01
LAB
EL
100n
C1
105
10u0
C1
104
U1
10
1
LTC
1628
-SS
OP
28
VIN
24
BO
OS
T1
25
SW
126
TG
127
BG
123
Ext
_V
cc22
INT
Vcc
21
FR
EQ
SE
T5
SE
NS
E1-
3
Vos1
4
BO
OS
T2
18
TG
216
SW
217
BG
219
SE
NS
E2+
14
SE
NS
E2-
13
Vos2
12
SE
NS
E1+
2F
LT
CP
L28
FC
B7
3V
3O
ut
10
ST
BY
MD
6
RU
N/S
S1
1
RU
N/S
S2
15
ITH
18
ITH
211
SG
ND
9
PG
ND
20
+C
11
3310
0u
DR
ILL
11
04
DR
ILL
1n00
C1
12
7
R1
104
5K10
1 2
10u0
C1
115
TP
1101
TE
ST
PO
INT
1
R1
106
10K
0
1 2
10u0
C1
11
4
180p
C1
10
9
10n0
C1
11
9
R1
118
36
k0
1 2
1n00
C1
12
6
DR
ILL
11
03
DR
ILL
220p
C1
117
DR
ILL
11
02
DR
ILL
SI6
96
6D
QT
1102
B5
8 76
1n00
C1
11
2
180p
C1
12
8
1n00
C1
10
8
R1
12
01
00
R
12
46
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Appendix B. Board Version 2 SchematicsFigure 19.
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
:te
eh
S:tc
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
vis
ion
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
stra
ße
119
A-4
232
Hag
enbe
rgo
fP
age
weivr
evO
_1
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L in i
m_
ep
H cs
am
R0
1
Mo
nd
ay,
Se
pte
mb
er
13
, 2
00
41
2:5
6:2
2
We
dn
esd
ay,
Ju
ly 1
6,
20
08
08
:43
:15
121
Gleichmann Electronics
Hpe_mini_LEC2 V2.0
Copying of this document, and giving it to others and the use or communication of the contents thereof, are
forbidden without express authority. Offenders are liable to the payment of damages. All rights are reserved
in the event of the grant of a patent or the registration of a utility model or design.
Copyright © Gleichmann Electronics Research (Austria) GmbH & Co KG 2005, All Rights Reserved
05-05-2006
VERSION
REVISIONS
DATE
CHANGE DESCRIPTION
1.0
AUTHOR
CSAM
SHEET
PROJECT OVERVIEW
1/12
PAGE LOCATOR
PAGE DESCRIPTION
new release
...
...
REVISIONS
VERSION
DATE
CHANGE DESCRIPTION
...
AUTHOR
...
FPGA I/O & POWER
2/12
3/12
FPGA CONFIGURATION
4/12
MEMORY
HUMAN INTERFACE
5/12
6/12
CLOCK & RESET
USB & RS232
7/12
8/12
ETHERNET
9/12
EXPANSION CONNECTOR & SATA
AUDIO & VGA
10/12
11/12
POWER SUPPLY
12/12
DESIGN NOTES
position of U0601 must be changed away from
the DDR
test adapter added (X23)
19-07-2006
1.1
CSAM
04-09-2006
1.2
final version
CSAM
15-07-2008
2.0
MZEI
small changes: e.g. additional Reset
47
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 20. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
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21
ME
MO
RY
_A
17
ME
MO
RY
_A
19
ME
MO
RY
_A
18
ME
MO
RY
_A
20
ME
MO
RY
_A
7
ME
MO
RY
_A
4M
EM
OR
Y_
A1
ME
MO
RY
_A
3
ME
MO
RY
_A
0
ME
MO
RY
_A
8
ME
MO
RY
_D
Q2
6
ME
MO
RY
_D
Q2
4
ME
MO
RY
_D
Q1
9
ME
MO
RY
_D
Q2
1
ME
MO
RY
_D
Q1
5M
EM
OR
Y_
DQ
16
ME
MO
RY
_D
Q2
3
ME
MO
RY
_D
Q2
8
ME
MO
RY
_D
Q2
7
ME
MO
RY
_D
Q1
1
ME
MO
RY
_D
Q1
2
ME
MO
RY
_D
Q1
7
ME
MO
RY
_D
Q1
8
ME
MO
RY
_D
Q2
2
ME
MO
RY
_D
Q1
0
ME
MO
RY
_D
Q3
1M
EM
OR
Y_
DQ
29
ME
MO
RY
_D
Q2
5
ME
MO
RY
_D
Q3
0
ME
MO
RY
_W
E#
ME
MO
RY
_D
Q1
4M
EM
OR
Y_
DQ
13
ME
MO
RY
_D
Q2
0
ME
MO
RY
_O
E#
SR
AM
_C
E#
SR
AM
_BE
1#
SR
AM
_BE
0#
XR
ES
FL
AS
H_
RY
/BY
#_
B
FL
AS
H_
BY
TE
#
FL
AS
H_
RY
/BY
#_
A
FL
AS
H_
CE
#
SR
AM
_BE
3#
SR
AM
_BE
2#
FL
AS
H_
RE
SE
T#
BB
3V
3_
IO0
BB
3V
3_
IO1
BB
3V
3_
IO2
BB
3V
3_
IO3
BB
3V
3_
IO1
2B
B3
V3
_IO
13
BB
3V
3_
IO1
4
BB
3V
3_
IO1
5
BB
3V
3_
IO1
6
BB
3V
3_
IO1
7
BB
3V
3_
IO1
8
BB
3V
3_
IO1
9
BB
3V
3_
IO2
0
BB
3V
3_
IO2
1
BB
3V
3_
IO4
BB
3V
3_
IO5
BB
3V
3_
IO6
BB
3V
3_
CLK
0-
BB
3V
3_
IO7
BB
3V
3_
IO8
BB
3V
3_
IO9
BB
3V
3_
IO1
0
BB
3V
3_
IO1
1
DA
C_
DIG
MA
CH
XO
_IO
7
MA
CH
XO
_IO
8
MA
CH
XO
_IO
9
MA
CH
XO
_IO
10
MA
CH
XO
_IO
11
MA
CH
XO
_IO
12
MA
CH
XO
_IO
13
MA
CH
XO
_IO
14
MA
CH
XO
_IO
15
MA
CH
XO
_C
LK1
BB
3V
3_
CLK
0+
AC
97
_B
ITC
LK
TS
T_C
OL1
TS
T_R
OW
3
TS
T_R
OW
0T
ST
_RO
W1
TS
T_R
OW
2
TS
T_C
OL2
TS
T_C
OL0
TS
T_S
TE
P
DS
W0
DS
W1
DS
W2
DS
W3
SE
G_
C#
SE
G_
DP
#S
EG
_G
#
SE
G_
D#
SE
G_
CA
0#
SE
G_
CA
1#
SE
G_B
#
SE
G_
F#
SE
G_A
#
SE
G_E
#
LC
D_
RW
LC
D_
RE
GS
EL
LC
D_
EN
AB
LE
RS
_C
TS
_LV
TT
LR
S_
RX
D_L
VT
TL
RS
_R
TS
_LV
TT
LR
S_T
XD
_LV
TT
L
ET
H_T
XE
R
ET
H_
RX
DV
ET
H_
CR
S
ET
H_
CO
L
ET
H_
MD
C
ET
H_
MD
IO
ET
H_
MD
INT
R#
ET
H_T
XC
LKE
TH
_R
XC
LK
ET
H_T
XD
3
ET
H_
TX
D1
ET
H_T
XE
N
ET
H_T
XD
2
ET
H_
RX
ER
ET
H_
RX
D2
ET
H_
RX
D0
ET
H_
RX
D1
ET
H_
RX
D3
ET
H_
TX
D0
LE
D0
#
LE
D2
#
US
B_
GP
IO2
0
DD
R_
DQ
5
DD
R_
DQ
4D
DR
_D
Q3
DD
R_
DQ
2
DD
R_
BA
0D
DR
_B
A1
DD
R_
DM
1
DD
R_
DQ
8
DD
R_
DQ
S1
DD
R_
DQ
9
DD
R_
DQ
10
DD
R_
DQ
11
SA
TA
_X2D
1-S
AT
A_X
2D1+
SA
TA
_X1D
0+
SA
TA
_X1D
1+S
AT
A_X
1D1-
SA
TA
_X1D
0-
DD
R_
DQ
16
DD
R_
DM
3
DD
R_
DQ
27
DD
R_
DQ
26
SA
TA
_X2D
0+S
AT
A_X
2D0-
EX
PC
ON
_IO
17
EX
PC
ON
_IO
39
EX
PC
ON
_IO
40
EX
PC
ON
_IO
41
EX
PC
ON
_IO
42
EX
PC
ON
_IO
43
EX
PC
ON
_IO
44
EX
PC
ON
_IO
45
CA
RD
SE
L#
MA
CH
XO
_C
LK1
DA
C_
DIG
DA
C_
AN
AL
OG
AD
C+
AD
C-
AD
C+
AD
CS
AD
CS
AD
C-
AC
97
_S
DA
TA
_OU
T
AC
97
_S
YN
CA
C9
7_
SD
AT
A_
INA
C9
7_E
XT
_CLK
AC
97
_R
ES
ET
#
AC
97
_E
AP
D
AC
97
_B
ITC
LK
VC
C2
V5
GN
D
VC
C3
V3
GN
D
GN
DG
ND
GN
D
VC
C1
V2
GN
D
GN
D
VC
C1
V2
GN
D
GN
DV
CC
3V
3
VC
C3
V3
GN
D
GN
D
VC
C3
V3
GN
D
VC
C3
V3
GN
D
VC
C3
V3
GN
D
VC
C2
V5
GN
D
VC
C2
V5
GN
D
GN
D
GN
D
VC
C3
V3
GN
D
VC
C3
V3
GN
D
GN
DG
ND
_D
AC
GN
D_
DA
C
GN
D_
AD
C
GN
DG
ND
_A
DC
VC
C1
V2
DS
W0
5D
SW
15
DS
W2
5D
SW
35
TS
T_R
OW
05
TS
T_R
OW
15
TS
T_R
OW
25
LE
D0
#5
TS
T_R
OW
35
LE
D2
#5
LE
D1
#5
LE
D3
#5
LE
D5
#5
LE
D4
#5
LE
D6
#5
SE
G_
CA
0#5
LE
D7
#5
SE
G_B
#5
SE
G_
CA
1#5
SE
G_
C#
5
SE
G_E
#5
SE
G_
F#
5S
EG
_G#
5
SE
G_A
#5
SE
G_
DP
#5
TS
T_C
OL0
5S
EG
_D
#5
TS
T_C
OL1
5
TS
T_S
TE
P5
TS
T_C
OL2
5
LC
D_
RE
GS
EL
5L
CD
_R
W5
LC
D_
EN
AB
LE
5 RS
_C
TS
_LV
TT
L7
RS
_R
XD
_LV
TT
L7
RS
_TX
D_L
VT
TL
7R
S_
RT
S_L
VT
TL
7
US
B_
GP
IO[2
8:0
]7
US
B_
PW
EN
07
US
B_
OC
0#
7U
SB
_P
WE
N1
7U
SB
_O
C1
#7
US
B_
PW
EN
27
US
B_
OC
2#
7
CA
RD
SE
L#
9
VG
A_
RD
010
VG
A_
RD
110
VG
A_
GR
010
VG
A_
GR
110
VG
A_B
L010
VG
A_
HS
YN
C10
VG
A_B
L110
VG
A_
VS
YN
C10
ET
H_T
XE
R8
ET
H_
TX
D3
8E
TH
_T
XD
28
ET
H_
TX
D1
8E
TH
_T
XD
08
ET
H_T
XE
N8
ET
H_T
XC
LK8
ET
H_
RX
ER
8E
TH
_R
XD
38
ET
H_
RX
D2
8E
TH
_R
XD
18
ET
H_
RX
D0
8
ET
H_
RX
CLK
8E
TH
_R
XD
V8
ET
H_
CR
S8
ET
H_
CO
L8
ET
H_
MD
INT
R#
8
ET
H_
MD
C8
ET
H_
MD
IO8
HP
E_
RE
SO
UT
#6
,7,8
,9C
LK
_F
PG
A6
EX
PC
ON
_C
LK
IN9
EX
PC
ON
_C
LK
OU
T9
I2C
_S
DA
16
I2C
_S
CL
16 F
LA
SH
_C
E#
4
SR
AM
_C
E#
4
ME
MO
RY
_O
E#
4M
EM
OR
Y_
WE
#4
FL
AS
H_
WP
#/A
CC
4
ME
MO
RY
_A
[22
:0]
4M
EM
OR
Y_
DQ
[31
:0]
4
FL
AS
H_
BY
TE
#4
FL
AS
H_
RY
/BY
#_
A4
FL
AS
H_
RY
/BY
#_
B4
SR
AM
_BE
0#4
SR
AM
_BE
1#4
SR
AM
_BE
2#4
SR
AM
_BE
3#4
FL
AS
H_
RE
SE
T#
4
HP
E_
RE
SE
T#
3,6 E
XP
CO
N_
IO[4
5:0
]9
US
B_
MIS
O7
US
B_
SS
I#7
US
B_
SC
K7
US
B_
MO
SI
7U
SB
_TX
D7
DD
R_
CK
E0
4D
DR
_B
A0
4D
DR
_B
A1
4
DD
R_
VR
EF
4
DD
R_
WE
#4
DD
R_
RA
S#
4D
DR
_C
AS
#4
DD
R_
S0
#4
DD
R_
S1
#4
DD
R_
DQ
[31
:0]
4
DD
R_
A[1
3:0
]4
DD
R_
CK
0+
4D
DR
_C
K0
-4
DD
R_
DQ
S[3
:0]
4
DD
R_
DM
[3:0
]4
DD
R_
CK
1+
4
US
B_
RX
D7
US
B_
RT
S7
US
B_
CT
S7
MA
CH
XO
_IO
[15
:0]
3M
AC
HX
O_
CLK
03
DD
R_
CK
E1
4D
DR
_C
K1
-4
SA
TA
_X1D
1+9
SA
TA
_X1D
1-9
SA
TA
_X2D
0+9
SA
TA
_X2D
0-9
SA
TA
_X1D
0+9
SA
TA
_X1D
0-9
SA
TA
_X2D
1+9
SA
TA
_X2D
1-9
BB
3V
3_
CLK
0-9
BB
3V
3_
CLK
0+9
BB
3V
3_
IO[2
1:0
]3
,9
MA
CH
XO
_C
LK1
3
AC
97
_S
DA
TA
_OU
T10
AC
97
_S
YN
C10
AC
97
_S
DA
TA
_IN
10A
C9
7_E
XT
_CLK
10A
C9
7_
RE
SE
T#
10
AC
97
_E
AP
D10
AC
97
_B
ITC
LK
10
:te
eh
S:tc
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
vis
ion
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
stra
ße
119
A-4
232
Hag
enbe
rgo
fP
age
AG
PF
_2
02
CE
L in i
m_
ep
H cs
am
R0
1
Sa
turd
ay,
Ap
ril 2
9,
20
06
10
:35
:32
Tu
esd
ay,
Ju
ly 1
5,
20
08
10
:27
:40
122
Latt
ice
EC
P2-
50 F
PG
AO
ffpag
e
Hum
an In
terf
ace
RS
232
US
B
Eth
erne
t
Exp
ansi
on C
onne
ctor
s an
d P
roto
typi
ng A
rea
Aud
io C
odec
VG
A
Clo
ck /
Res
et
Mem
ory
Mac
hXO
1%
DIFF
LVDS
LVDS
LVDS
LVDS
DA
C
AD
C
LVDS
LVDS
0,1%
0,1%
Sternpunkt an X1
Sternpunkt an X2
1
23
04
Place pins 0..4 near the balls of the FPGA.
These pins must also be accessible for
measurements instruments.
R0
20
5
33
k2
12
100n
C0
20
7
100n
C0
23
0
100n
C0
20
1
100n
C0
21
0
100n
C0
22
1
nb_
4p7
0C
02
51
+C
02
38
4u70
1 2
1n0
0C
02
44
100n
C0
21
1
100n
C0
21
6
100n
C0
23
1
+C
02
42
4u7
0
1 2
nbC
02
48
100n
C0
22
5
R0
20
4
10
k0
12
optional
A02
01J
um
pe
r
100n
C0
20
2
100n
C0
21
5
100n
C0
23
7
4p70
C0
25
0
100n
C0
21
7
1n00
C0
23
9
POWER SUPPLY
U0
20
1F
EC
P2
-50
-672
BG
A
GN
DN
12
GN
DN
10
GN
DM
14
GN
DM
13
GN
DL3
GN
DL24
GN
DL17
GN
DL16
GN
DL11
GN
DL10
GN
DK
17
GN
DK
16
GN
DK
14
GN
DK
13
GN
DK
11
GN
DK
10
GN
DJ6
GN
DJ2
1G
ND
J14
GN
DJ1
3G
ND
F9
GN
DF
3G
ND
F24
GN
DF
18
GN
DC
6G
ND
C21
GN
DC
16
GN
DC
11
GN
DB
26
GN
DB
1G
ND
AF
25
GN
DA
F2
GN
DA
E26
GN
DA
E1
GN
DA
D6
GN
DA
D21
GN
DA
D16
GN
DA
D11
GN
DA
A9
GN
DA
A3
GN
DA
A24
GN
DA
A18
GN
DA
25
GN
DA
2V
CC
L12
VC
CL13
VC
CL14
VC
CL15
VC
CM
11
VC
CM
12
VC
CM
15
VC
CM
16
VC
CN
11
VC
CN
16
VC
CP
11
VC
CP
16
VC
CR
11
VC
CR
12
VC
CR
15
VC
CR
16
VC
CT
12
VC
CT
13
VC
CT
14
VC
CT
15
VC
CIO
0D
11
VC
CIO
0D
6
VC
CIO
0G
9
VC
CIO
0J1
2
VC
CIO
0K
12
VC
CIO
1D
16
VC
CIO
1D
21
VC
CIO
1G
18
VC
CIO
1J1
5
VC
CIO
1K
15
VC
CIO
2F
23
VC
CIO
2J2
0
VC
CIO
2L23
VC
CIO
2M
17
VC
CIO
2M
18
VC
CIO
3A
A23
VC
CIO
3R
17
VC
CIO
3R
18
VC
CIO
3T
23
VC
CIO
3V
20
VC
CIO
4A
C16
VC
CIO
4A
C21
VC
CIO
4U
15
VC
CIO
4V
15
VC
CIO
4Y
18
VC
CIO
5A
C11
VC
CIO
5A
C6
VC
CIO
5U
12
VC
CIO
5V
12
VC
CIO
5Y
9
VC
CIO
6A
A4
VC
CIO
6R
10
VC
CIO
6R
9
VC
CIO
6T
4
VC
CIO
6V
7
VC
CIO
7F
4
VC
CIO
7J7
VC
CIO
7L4
VC
CIO
7M
10
VC
CIO
7M
9
VC
CIO
8A
E25
VC
CIO
8V
18
GN
DN
13
GN
DN
14
GN
DN
15
GN
DN
17
GN
DP
10
GN
DP
12
GN
DP
13
GN
DP
14
GN
DP
15
GN
DP
17
GN
DR
13
GN
DR
14
GN
DT
10
GN
DT
11
GN
DT
16
GN
DT
17
GN
DT
24
GN
DT
3
GN
DU
10
GN
DU
11
GN
DU
13
GN
DU
14
GN
DU
16
GN
DU
17
GN
DV
13
GN
DV
14
GN
DV
21
GN
DV
6
7
KN
AB
6 K
NA
BU
02
01
D
EC
P2
-50
-672
BG
A
PL46A
/PC
LK
T6_0
M4
VR
EF
2_7/P
L2A
D2
PL46B
/PC
LK
C6_0
M5
PL47A
/VR
EF
2_6
N7
PL47B
/VR
EF
1_6
P9
PL49A
N5
PL48A
N3
PL49B
P7
PL48B
N4
PL51B
P6
PL51A
P8
PL50B
T2
PL50A
/LD
QS
50
T1
PL52B
P4
PL52A
P5
PL53B
V1
PL53A
U1
PL60A
/LLM
0_G
DLLT
_IN
_A
Y1
PL58B
R7
PL55A
R4
PL60B
/LLM
0_G
DLLC
_IN
_A
AA
2
PL57B
R5
PL57A
T6
PL61B
/LLM
0_G
DLLC
_F
B_D
T7
PL58A
/LD
QS
58
R6
PL59B
Y2
PL59A
W1
PL54A
P3
PL56B
W2
PL56A
V2
PL55B
U2
PL61A
/LLM
0_G
DLLT
_F
B_A
T5
PL54B
R3
PL67A
/LD
QS
67
W3
PL65A
V4
PL66A
Y3
PL64A
/LLM
0_G
PLLT
_F
B_A
V3
PL63A
/LLM
0_G
PLLT
_IN
_A
U3
PL63B
/LLM
0_G
PLLC
_IN
_A
U4
PL70B
U6
PL66B
Y4
PL69A
U8
PL68B
AB
1
PL64B
/LLM
0_G
PLLC
_F
B_A
U5
PL65B
V5
PL71A
W6
PL70A
V8
PL67B
W4
PL68A
AA
1
PL71B
W5
PL72A
AC
1
PL72B
AD
1
PL73A
Y6
PL73B
Y5
PL74A
AE
2
PL74B
AD
2
PL75A
/LD
QS
75
AB
3
PL75B
AB
2
PL76A
W7
PL76B
W8
PL77A
Y7
PL77B
Y8
PL78A
AC
2
PL78B
AD
3
VR
EF
1_7/P
L2B
D1
PL5A
F6
PL5B
F5
PL6A
E4
PL6B
E3
PL7A
E2
PL7B
E1
PL8B
H5
LD
QS
8/P
L8A
H6
PL9A
F2
PL9B
F1
PL10A
H8
PL11A
G4
PL10B
J9
PL11B
G3
PL14B
H4
PL12A
H7
LD
QS
16/P
L16A
J3
PL17A
H1
PL14A
H3
PL12B
J8
PL19B
J2
PL13A
G2
PL15A
J5
PL16B
K4
PL18A
K6
PL18B
K7
PL19A
J1
PL17B
H2
PL15B
J4
PL13B
G1
PL39B
K5
LD
QS
41/P
L41A
P1
PL37A
N1
PL23B
K2
LU
M0_S
PLLT
_IN
_A
/PL25A
L1
PL24B
L2
LU
M0_S
PLLC
_F
B_A
/PL26B
N2
LD
QS
24/P
L24A
K1
PL39A
L6
LU
M0_S
PLLC
_IN
_A
/PL25B
M2
PL38A
L8
LU
M0_S
PLLT
_F
B_A
/PL26A
M1
PL40B
L5
PL40A
L7
PL23A
K3
PL38B
K8
PL42B
N8
PL43A
R1
PC
LK
T7_0/P
L44A
M7
PL42A
M6
PL41B
P2
PC
LK
C7_0/P
L44B
N9
PL43B
R2
PL69B
U7
100n
C0
22
6
100n
C0
21
2
+C
02
43
4u7
0
1 2
100n
C0
20
8
100n
C0
23
4+
C0
24
04
u70
1 2
100n
C0
21
8
100n
C0
22
2
100n
C0
23
2
R0
20
10
R0
0
1 2
5 K
NA
B4
K
NA
BU
02
01
C
EC
P2
-50
-672
BG
A
PB
82A
/VR
EF
2_4
Y21
VR
EF
2_5/P
B2A
AE
3
PB
82B
/VR
EF
1_4
AB
23
PB
81A
Y20
PB
81B
AB
22
PB
80A
AF
24
PB
78A
/BD
QS
78
AB
21
PB
79B
AA
21
PB
80B
AE
24
PB
79A
W19
PB
78B
AC
22
PB
77B
AC
20
PB
77A
AB
20
PB
49A
/PC
LK
T4_0
AD
15
PB
49B
/PC
LK
C4_0
AC
15
PB
50A
AE
13
PB
50B
AF
13
PB
51A
/BD
QS
51
AB
17
PB
51B
Y15
PB
52A
AE
14
PB
52B
AF
14
PB
57B
AB
18
PB
54A
AC
17
PB
54B
AB
16
PB
57A
Y16
PB
55B
AF
15
PB
53A
AA
16
PB
56B
AF
16
PB
55A
AE
15
PB
56A
AE
16
PB
58B
AD
18
PB
60B
AE
17
PB
59B
AD
19
PB
58A
AD
17
PB
62A
AF
17
PB
61B
AE
19
PB
61A
AB
19
PB
59A
AC
18
PB
60A
/BD
QS
60
AC
19
PB
62B
AE
18
PB
63A
W16
PB
63B
AA
17
PB
64A
AF
18
PB
64B
AF
19
PB
65A
AA
19
PB
65B
W17
PB
66A
Y19
PB
66B
Y17
PB
67A
AF
20
PB
67B
AE
20
PB
68A
AA
20
PB
68B
W18
PB
69A
/BD
QS
69
AD
20
PB
70A
AF
21
PB
69B
AE
21
PB
70B
AF
22
PB
74A
AE
22
PB
74B
AD
22
PB
75A
AF
23
PB
75B
AE
23
PB
76A
AD
23
PB
76B
AC
23
VR
EF
1_5/P
B2B
AF
3
PB
3A
AC
4
PB
3B
AD
4
PB
4B
AF
4
PB
5B
W9
PB
5A
V9
PB
4A
AE
4
BD
QS
6/P
B6A
AA
6
PB
7B
AD
5
PB
6B
AB
6
PB
7A
AC
5
PB
9A
AE
5
PB
9B
AF
5
PB
8B
AB
7P
B8A
AA
7
BD
QS
24/P
B24A
AE
6
PB
26A
AB
9
PB
26B
AD
9
PB
21A
W11
PB
24B
AF
6
PB
23B
AB
10
PB
10B
AD
7
PB
23A
AB
8
PB
20B
Y10
PB
22B
AD
8
PB
20A
W10
PB
21B
AA
10
PB
25A
AA
11
PB
25B
AC
9
PB
10A
AC
7
PB
22A
AC
8
PB
28B
AF
7
BD
QS
33/P
B33A
AC
13
PB
32A
AD
12
PB
29A
AC
10
PB
30A
AA
12
PB
32B
AC
12
PB
34B
AC
14
PB
28A
AE
7
PB
34A
AD
13
PB
33B
AA
13
PB
31A
AB
12
PB
29B
AD
10
PB
27B
AB
11
PB
27A
Y11
PB
30B
W12
PB
31B
Y12
PB
35A
AE
8
PB
37A
AE
9
PB
36A
AB
15
PB
37B
AF
9
PB
36B
Y13
PB
38A
W13
PB
35B
AF
8
PB
38B
AA
14
PB
39A
AE
10
PB
39B
AF
10
PB
40A
W14
PB
40B
AB
13
PB
41A
Y14
PB
41B
AB
14
BD
QS
42/P
B42A
AE
11
PB
43A
AD
14
PB
43B
AA
15
PC
LK
T5_0/P
B44A
AE
12
PC
LK
C5_0/P
B44B
AF
12
PB
42B
AF
11
PB
53B
W15
3n30
C0
24
6
X22
12
100n
C0
23
5
100n
C0
22
3
100n
C0
23
3
100n
C0
22
7
100n
C0
21
3
R0
20
210
K0
12
100n
C0
22
8
3
KN
AB
2
KN
AB
U0
20
1B
EC
P2
-50
-672
BG
A
PR
2A
/VR
EF
1_2
F21
PC
LK
T3_0/P
R46A
L25
PR
2B
/VR
EF
2_2
E22
PR
5A
H20
PR
6B
D23
PR
5B
G21
PR
6A
C23
PR
8A
/RD
QS
8G
22
PR
7B
B24
PR
7A
C24
PR
9B
D24
PR
8B
H21
PR
9A
B25
PR
12B
D26
PR
14A
G23
PR
15B
J22
PR
11A
E24
PR
14B
G24
PR
10A
C25
PR
13A
J19
PR
12A
C26
PR
10B
D25
PR
11B
F22
PR
15A
H22
PR
13B
K19
PR
17A
L19
PR
17B
K20
PR
18A
F25
PR
16A
/RD
QS
16
E25
PR
16B
E26
PR
23B
H24
PR
18B
F26
PR
19A
G25
PR
23A
H23
PR
19B
G26
PR
24B
H26
PR
25A
/RU
M0_S
PLLT
_IN
_A
K23
PR
26A
/RU
M0_S
PLLT
_F
B_A
J25
PR
24A
/RD
QS
24
H25
PR
25B
/RU
M0_S
PLLC
_IN
_A
J23
PR
37B
K24
PR
38A
M21
PR
26B
/RU
M0_S
PLLC
_F
B_A
J26
PR
38B
K21
PR
37A
J24
PC
LK
C3_0/P
R46B
L26
VR
EF
1_3/P
R47A
N21
VR
EF
2_3/P
R47B
N18
PR
48A
M25
PR
49A
N20
PR
48B
M26
PR
49B
N19
PR
53A
P19
PR
52A
P22
PR
52B
P23
RD
QS
50/P
R50A
N25
PR
51A
R21
PR
50B
N26
PR
53B
P21
PR
51B
N22
PR
54B
P20
PR
54A
R19
PR
55B
R24
PR
56A
P25
PR
57B
R22
PR
57A
T21
PR
56B
P26
PR
55A
R23
RLM
0_G
DLLC
_IN
_A
/PR
60A
T26
RLM
0_G
DLLT
_F
B_A
/PR
61A
U20
RD
QS
58/P
R58A
R25
RLM
0_G
DLLC
_F
B_A
/PR
61B
T19
RLM
0_G
DLLC
_IN
_A
/PR
60B
T25
PR
58B
R26
PR
59A
T22
PR
59B
T20
RLM
0_G
PLLT
_IN
_A
/PR
63A
U25
PR
65A
U26
RLM
0_G
PLLC
_F
B_A
/PR
64B
U22
PR
65B
V26
PR
66A
V25
RLM
0_G
PLLC
_IN
_A
/PR
63B
U24
PR
66B
V24
RLM
0_G
PLLT
_F
B_A
/PR
64A
U23
PR
39A
M22
PR
40A
M19
PR
40B
M20
PR
41A
/RD
QS
41
K25
PR
41B
K26
PR
42A
N23
PR
42B
M24
PR
43A
K22
PR
43B
L21
PR
44A
/PC
LK
T2_0
M23
PR
44B
/PC
LK
C2_0
N24
RD
QS
67/P
R67A
W26
PR
67B
W25
PR
68A
U19
PR
68B
U21
PR
69A
Y26
PR
69B
AA
26
PR
70A
V23
PR
70B
W24
PR
39B
L22
1n0
0C
02
45
100n
C0
23
6
100n
C0
21
9
FB
02
01
BL
M1
8B
D6
01S
N1
12
100n
C0
22
4
100n
C0
20
6
1n0
0C
02
41
100n
C0
22
9
R0
20
3
10
k0
12
nbC
02
49
nbC
02
47
1 K
NA
B0
KN
AB
U0
20
1A
EC
P2
-50
-672
BG
A
PT
37A
B8
PT
36B
E11
PT
36A
C9
PT
35B
A7
PT
35A
B7
PT
34B
F12
PT
34A
D10
PT
33B
H11
PT
33A
G11
PT
32B
A6
PT
32A
B6
PT
31B
D8
PT
31A
C8
PT
30B
F11
PT
30A
E10
PT
28B
G10
PT
29A
D9
PT
29B
E9
PT
28A
H10
PT
27B
A5
PT
27A
B5
PT
26B
C7
PT
26A
D7
PT
25B
E8
PT
25A
F10
PT
24B
F8
PT
24A
H9
PT
23B
C5
PT
23A
D5
PT
22B
B4
PT
10B
C4
PT
10A
C3
PT
9B
A4
PT
9A
A3
PT
8B
B3
PT
8A
B2
PT
7B
D4
PT
7A
D3
PT
6B
C2
PT
6A
C1
PT
5B
G8
PT
5A
G7
PT
4B
E7
PT
4A
F7
PT
3B
E6
PT
3A
E5
PT
2B
/VR
EF
2_0
G6
PT
2A
/VR
EF
1_0
G5
PT
71A
C19
PT
71B
E19
PT
70A
B20
PT
70B
B21
PT
69A
B19
PT
69B
D19
PT
68A
E18
PT
68B
G17
PT
67A
F17
PT
67B
G19
PT
66A
A19
PT
66B
A20
PT
65A
D18
PT
65B
E17
PT
64A
A18
PT
64B
B18
PT
63A
G16
PT
63B
E16
PT
62A
H18
PT
62B
F16
PT
61A
B17
PT
61B
A17
PT
60A
B16
PT
59B
C17
PT
58B
E15
PT
57B
A16
PT
56B
D15
PT
55B
A14
PT
54B
C15
PT
53B
A13
PT
52B
H17
PT
51B
D13
PT
50B
G14
PT
49B
A12
PC
LK
C1_0/P
T48B
F14
PT
60B
C18
PT
59A
D17
PT
58A
G15
PT
57A
B15
PT
56A
F15
PT
55A
B14
PT
54A
A15
PT
53A
B13
PT
52A
H15
PT
51A
C14
PT
50A
E14
PT
49A
B12
PC
LK
T1_0/P
T48A
D14
PT
37B
A8
PT
38A
G12
PT
39A
B9
PT
39B
A9
PT
40A
H12
PT
40B
G13
PT
41A
C10
PT
41B
C12
PT
42A
B10
PT
42B
A10
PT
43A
F13
PT
43B
D12
PT
44A
E13
PT
44B
C13
PT
45A
B11
PT
45B
A11
PT
46A
/PC
LK
T0_0
H13
PT
46B
/PC
LK
C0_0
H14
PT
74A
A21
PT
74B
A22
PT
75A
D20
PT
75B
C20
PT
76A
B23
PT
76B
B22
PT
77A
E20
PT
77B
C22
PT
78A
F19
PT
78B
E21
PT
79A
A23
PT
79B
A24
PT
80A
H19
PT
80B
F20
PT
81A
J18
PT
81B
G20
VR
EF
1_1/P
T82A
D22
VR
EF
2_1/P
T82B
E23
XR
ES
H16
PT
38B
E12
100n
C0
22
0
X2 HD
R2
12
100n
C0
21
4
X1
12
48
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 21.
54
32
1
D C B A
JTA
G_
DO
NE
SIS
PI
CC
LK
CS
SP
IN
CF
G2
CF
G1
CF
G0
JTA
G_
INIT
PR
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RA
M#
MA
CH
XO
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[15
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GP
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GP
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GP
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GP
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CF
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MA
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XO
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1M
AC
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O_
IO2
MA
CH
XO
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3
MA
CH
XO
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4M
AC
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O_
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GP
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XD
0G
P_T
XD
0
GP
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XD
1G
P_T
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1
GP
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PT
GP
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6G
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R7
GP
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8
GP
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D3
GP
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4
GP
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5G
P_
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GP
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7G
P_
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GP
_D
9
GP
_D
10
GP
_T1
GP
_T2
GP
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GP
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TL3
GP
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TL2
GP
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TL1
GP
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TL0
GP
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DY
0G
P_
RD
Y1
GP
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DY
2G
P_
RD
Y3
GP
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DY
4G
P_
RD
Y5
GP
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TL5
GP
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TL4
GP
_D
11
GP
_D
12
GP
_D
13
GP
_D
15
GP
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14
GP
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DR
0G
P_
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R1
GP
_A
DR
2
GP
_A
DR
3
GP
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4G
P_
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R5
GP
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LOE
GP
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GP
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GP
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GP
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KT
EN
D
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B_
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K_
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CL
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AG
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ON
E
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INIT
MA
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MA
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OM
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HX
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CK
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EC
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CL
K_
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GP
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CL
K
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XO
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LK0
CL
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EX
PC
ON
_IO
[45
:0]
HP
E_
RE
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T#
US
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SB
CF
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R_
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B_
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SB
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LK1
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CP
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ALL
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7
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MA
CH
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10
MA
CH
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11
MA
CH
XO
_IO
12
MA
CH
XO
_IO
13
MA
CH
XO
_IO
14
MA
CH
XO
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15
MA
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LK1
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CL
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AG
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I
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RE
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T#
BB
3V
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1
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]
HP
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RE
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VC
C3
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GN
D
VC
C3
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VC
C3
V3
VC
C3
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F
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DA
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ON
F
GN
D
GN
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FG
ND
P
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C3
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GN
D
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VC
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V3
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D
GN
D
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C3
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VC
C3
V3
VC
C3
V3
VC
C3
V3
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D
VC
C3
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GN
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GN
D
VC
C3
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GN
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VC
C3
V3
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C3
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C3
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VC
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GN
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ND
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D
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D
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GN
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ND
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D
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C3
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V5
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VC
C5
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VC
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C3
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GN
D
MA
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XO
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[15
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2
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LK0
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CL
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6
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[45
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2,9
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:
Cre
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Res
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9,
20
06
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Ju
ly 1
6,
20
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7:4
3
123
La
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CP
2-5
0 F
PG
A (
Co
nfig
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Offp
age
M25P16-VMF6P 16Mb
Place the 4k7 resistors
close to their clock
line to keep the stub
length as short as
possible.
US
B-J
TA
G P
rogr
amm
er C
onne
ctor
USB Peripheral
for Configuration
JTAG Connector
for Configuration
CCLK
0 1
CFG2
0Reserved
Mode
1
INIT#
00
1
0
DONE
10
SPI Normal
1
000
SPI Fast
Drain
PROGRAM#
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am
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N
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PS
0
Co
nfig
ura
tion
Se
ttin
gs
Source
Reserved
SOT-23
CFG0
1Reserved
0 0SPIm Fast
Gate
CFG1
DOUT
SPIFAST#
Pull-Down
Pull-Up
X
Pull-Down
Pull-Up
X XSlave Serial
10
XReserved
1 11
0X
00
TSALL
Te
st A
da
pte
r
SP
I F
lash
for
Co
nfig
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ion
rev 1.1
TP
0305
RJ0
30
40
R0
0
1 2
10
0n
C0
31
3
1n00
C0
30
1
R0
30
82
70
R
12
10
0n
C0
32
0
RJ0
30
3nb
_1
0K
0
1 2
10
0n
C0
31
9
5n60
C0
32
6
T03
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SS
13
8/S
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U0
30
1
CY
7C
68
01
3A
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P1
00
VC
C1
VC
C33
VC
C38
VC
C49
VC
C53
VC
C66
VC
C78
VC
C85
VC
C20
GN
D2
GN
D21
GN
D39
GN
D48
GN
D50
GN
D65
GN
D75
GN
D94
GN
D99
AV
CC
16
AG
ND
19
AG
ND
12
AV
CC
9
PA
0/IN
T0
67
PA
1/IN
T1
68
PA
2/S
LO
E69
PA
3/W
U2
70
PA
4/F
IFO
AD
R0
71
PA
5/F
IFO
AD
R1
72
PA
6/P
KT
EN
D73
PA
7/F
LA
GD
/SLC
S74
PB
0/F
D0
34
PB
1/F
D1
35
PB
2/F
D2
36
PB
3/F
D3
37
PB
4/F
D4
44
PB
5/F
D5
45
PB
6/F
D6
46
PB
7/F
D7
47
PD
0/F
D8
80
PD
1/F
D9
81
PD
2/F
D10
82
PD
3/F
D11
83
PD
4/F
D12
95
PD
5/F
D13
96
PD
6/F
D14
97
PD
7/F
D15
98
PC
0/G
PIF
AD
R0
57
PC
1/G
PIF
AD
R1
58
PC
2/G
PIF
AD
R2
59
PC
3/G
PIF
AD
R3
60
PC
4/G
PIF
AD
R4
61
PC
5/G
PIF
AD
R5
62
PC
6/G
PIF
AD
R6
63
PC
7/G
PIF
AD
R7
64
PE
0/T
0O
UT
86
PE
1/T
1O
UT
87
PE
2/T
2O
UT
88
PE
3/R
XD
0O
UT
89
PE
4/R
XD
1O
UT
90
PE
5/IN
T6
91
PE
6/T
2E
X92
PE
7/G
PIF
AD
R8
93
RD
Y0/S
LR
D3
RD
Y1/S
LW
R4
RD
Y2
5
RD
Y3
6
RD
Y4
7
RD
Y5
8
XT
ALIN
11
XT
ALO
UT
10
RE
SE
T77
NC
13
NC
14
NC
15
RE
SE
RV
ED
27
DP
LU
S17
DM
INU
S18
CT
L0/F
LA
GA
54
CT
L1/F
LA
GB
55
CT
L2/F
LA
GC
56
CT
L3
51
CT
L4
52
CT
L5
76
INT
422
INT
584
T0
23
T1
24
T2
25
WA
KE
UP
79
RX
D0
41
TX
D0
40
RX
D1
43
TX
D1
42
SC
L29
SD
A30
BK
PT
28
CLK
OU
T100
IFC
LK
26
RD
31
WR
32
RJ0
30
20
R0
0
1 2
10
0n
C0
31
6
100n
C0
30
2
R0
31
410
K0
1 2
R0
31
810
0K
1 2
10
0n
C0
30
91n
00C
03
15
SW
030
3B
3F
S-1
012
13
24
Q0
301
24M
Hz 1
2
RJ0
30
8n
b_
0R
00
1 2
10
0n
C0
30
4
12
p0C
03
40
RJ0
31
010
K0
1 2
+C
03
24
4u70
1 2
+C
03
07
2u2
0
1 2
10
0n
C0
31
11
00
nC
03
21
10
0n
C0
30
8
X23
Te
stC
on
tact
TV
i0
TV
i1
TV
i2
TV
i3
TV
o0
TV
o1
TV
o2
TV
o3
TP
0T
P1
TP
2T
P3
TP
4T
P5
TP
6T
P7
TP
8T
P9
TP
10
TP
11
TP
12
TP
13
TP
14
TP
15
TP
16
GN
D
10
0n
C0
31
81
00
nC
03
22
RJ0
30
1nb
_1
0K
0
1 2
12p0
C0
33
9
TP
0307
SW
030
2
CA
S-1
20A
A1
B3
C2
X3 US
B P
eri
phe
ral
VC
C1
DA
TA
-2
DA
TA
+3
GN
D4
SH
IELD
5
SH
IELD
6
10
0n
C0
31
0
FB
03
02
BL
M1
8P
G60
0SN
11
2
R0
30
14
k70
1 2
RJ0
30
5nb
_1
0K
0
1 2
TP
0303
R0
30
52
70
R
12
R0
31
710
K0
1 2
1n0
0C
03
23
LD
03
03
LE
D y
ello
w
X4 CO
N1
01 2 3 4 5 6 7 8 9 10
RJ0
30
60
R0
0
1 2
TP
0310
U0
30
5
M25
P16
CLK
16
DI
15
NC
14
GN
D10
WP
9
NC
13
NC
12
NC
11
HO
LD
1
VC
C2
NC
3
NC
4
NC
5
NC
6
CS
7
Q8
R0
31
610
K0
1 2
10
0n
C0
31
2
R0
30
74
k70
1 2
100n
C0
31
4
R0
30
410
K0
1 2
BANK 0/0,1
BANK 1/2,3
BANK 2/4,5
BANK 3/6,7
U0
30
2
MA
CH
XO
-64
0/1
20
0-1
32
csB
GA
PL2A
B1
PL2B
/PL3C
C1
PL3A
/PL3D
C3
PL3B
/PL4B
D1
PL3D
/PL4C
D3
PL5A
/PL6A
E2
VC
CIO
1/V
CC
IO3
L12
(GS
RN
) P
L5B
/PL6B
E3
PB
5D
/PB
7C
N8
PB
5B
/PB
7B
(P
CLK
T)
M7
PB
5A
/PB
6F
N7
SLE
EP
NN
12
PB
6A
/PB
7D
P8
PB
6B
/PB
7F
(P
CLK
T)
M8
PB
4F
/PB
6A
M6
PB
4E
/PB
5C
N6
VC
CP
6
PB
3B
M4
PB
3C
/PB
4A
N4
GN
DF
1
VC
CIO
3/V
CC
IO7
D2
PL9B
/PL12A
K2
PB
2C
M3
PB
2D
N3
PL7C
/PL10B
H1
PL8A
/PL11B
J1
PL9A
/PL11D
J3
VC
CIO
1/V
CC
IO2
E12
VC
CIO
3/V
CC
IO6
K3
PL5D
/PL6D
F2
PL6B
/PL7C
F3
PL7A
/PL8D
G3
PL7B
/PL10A
H2
PR
3C
/PR
4A
D12
PR
4D
/PR
6A
F12
PR
4C
/PR
5B
E13
PR
2B
/PR
3C
C13
VC
CIO
0/V
CC
IO1
B11
PR
2A
/PR
2A
A14
PT
9C
/PT
10F
B12
PT
5B
/PT
6F
(P
CLK
T)
C8
PT
5A
/PT
6D
B7
PT
6B
/PT
7D
(P
CLK
T)
A8
PT
6A
/PT
7B
B8
PT
4D
/PT
5D
A6
PT
4C
/PT
5C
B6
GN
DP
9
PT
3D
/PT
4B
A5
VC
CA
UX
P7
VC
CH
3
PT
3B
/PT
3D
A4
VC
CIO
0/V
CC
IO0
C5
VC
CIO
2/V
CC
IO4
M10
PT
2F
/PT
3C
C4
PT
2D
/PT
3B
A3
PT
2C
/PT
2B
A2
PT
2B
/PT
3A
B3
PT
2A
A1
PR
11A
/PR
15A
M12
PR
10B
/PR
14B
M13
PR
8B
/PR
11B
K12
PR
8A
/PR
11A
J13
PR
10A
/PR
14A
L14
PR
7C
/PR
10B
J12
PR
7B
/PR
10A
H14
PR
7A
/PR
9B
H13
PR
6B
/PR
8A
G14
VC
CIO
2/V
CC
IO5
N2
PR
8D
/PR
12B
K14
PR
5D
/PR
6C
F14
PR
5C
/PR
6B
F13
PR
8C
/PR
12A
K13
PR
6D
/PR
9A
H12
PR
4B
/PR
5A
E14
PR
6C
/PR
8B
G13
PR
3D
/PR
4B
D14
VC
CG
12
VC
CC
7
GN
DJ1
4G
ND
C9
GN
DIO
0/G
ND
IO1
A10
GN
DIO
0/G
ND
IO0
B4
GN
DIO
1/G
ND
IO3
L13
GN
DIO
1/G
ND
IO2
D13
GN
DIO
2/G
ND
IO5
P2
GN
DIO
2/G
ND
IO4
N11
GN
DIO
3/G
ND
IO7
E1
GN
DIO
3/G
ND
IO6
L2
PL2C
/PL2B
B2
PL2D
/PL4A
C2
PL6C
/PL7D
G1
PL6D
/PL8C
G2
(TS
ALL)
PL8C
/PL11C
J2
PL9C
/PL12B
K1
PL10B
/PL14B
L3
PL10A
/PL14A
L1
PL11A
/PL15A
M1
PL11B
/PL16A
N1
PL11C
/PL15B
M2
PL11D
/PL16B
P1
PB
3D
/PB
4B
P5
PB
7A
/PB
9A
N9
PB
7B
/PB
9B
M9
PB
7E
/PB
9C
N10
PB
7F
/PB
9D
P10
PB
8C
/PB
10A
P11
PB
8D
/PB
10B
M11
PB
9C
/PB
10C
P12
PB
9D
/PB
11C
P13
PB
9F
/PB
11D
P14
TM
SP
3
TC
KP
4
TD
ON
5
TD
IM
5
PT
3E
/PT
5A
B5
PT
3F
/PT
5B
C6
PT
7B
/PT
9B
B9
PT
7E
/PT
9E
C10
PT
7F
/PT
9F
B10
PT
8C
/PT
10C
C11
PT
7A
/PT
9A
A9
PT
9A
/PT
10D
A11
PT
9B
/PT
11A
C12
PT
9D
/PT
11C
B13
PT
9F
/PT
11D
A13
PT
9E
/PT
11B
A12
PR
2C
/PR
2B
B14
PR
2D
/PR
3D
C14
PR
11B
/PR
16A
N13
PR
11C
/PR
15B
M14
PR
11D
/PR
16B
N14
VC
CA
UX
A7
TP
0302
LD
03
02
LE
D r
ed
R0
30
34
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03
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13
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12
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30
710
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0309
TP
0308
BANK 8
AUX & PLL POWERBANK 9
U0
20
1E
EC
P2
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BG
A
CS
N/P
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AC
25
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1N
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24
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22
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26
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26
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26
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25
TC
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5
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24
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12
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9nb
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0
1 2
TP
0311
T03
02B
SS
13
8/S
OT
49
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 22. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
ME
MO
RY
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ME
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Series Resistors
Parallel Termination Resistors
- Place C0401 as close as possible to the PVIN
pin
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pin
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each end of the VTT island. (C04??, C04??)
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 23. 5 5
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51
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 24. 5 5
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LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 25. 5 5
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ep
tem
be
r 2
4,
20
04
12
:34
:50
Tu
esd
ay,
Ju
ly 1
5,
20
08
10
:27
:40
127
Offp
age
RS
23
2 I
nte
rfa
ce
US
B C
ontr
olle
r
GPIO30
GPIO31
Boot Configuration Interface
Host Port Interface (HPI)
High-Speed Serial (HSS)
Serial Peripheral Interface (SPI)
I2C EEPROM (Standalone Mode)
00 1 0
10 11
SDA
SCL
1500mA
330 Ohm @ 100 MHz
USB OTG
USB HOST
USB HOST
USB HOST
C0
70
71
u00
10
0n
C0
70
1
EXT MEMORY
EXT MEMORY CONTROL
GPIO
USB PORTS
CHARGE PUMP
RESET / CLOCK
POWER
U0
70
2
CY
7C
67
30
0_
TQ
FP
10
0
A1
1
A2
2
A4
7A
33
A6
17
A5
8
A8
24
A9
25
A7
20
A10
27
A11
30
A12
31
A13
32
A14
33
A15/C
LK
SE
L38
A16
97
A17
95
A18
96
D0
83
A0/B
EL
99
D1
82
D2
81
D3
80
D4
79
D5
78
D6
77
D7
76
D8/M
ISO
74
D9/S
SI
73
D10/S
CK
72
D11/M
OS
I71
D12/T
XD
70
D13/R
XD
69
D14/R
TS
68
D15/C
TS
67
BE
H98
WR
64
RD
62
ME
MS
EL
34
RO
MS
EL
35
RA
MS
EL
36
GP
IO0/D
094
GP
IO1/D
193
GP
IO2/D
292
GP
IO3/D
391
GP
IO4/D
490
GP
IO8/M
ISO
/D8
66
GP
IO7/D
786
GP
IO6/D
687
GP
IO9/S
SI/D
965
GP
IO5/D
589
GP
IO10/S
CK
/D10
61
GP
IO11/M
OS
I/D11
60
GP
IO12/D
12
59
GP
IO13/D
13
58
GP
IO14/D
14
57
GP
IO15/S
SI/D
15
56
GP
IO16/T
XD
/I_A
055
GP
IO17/R
XD
/I_A
154
GP
IO18/R
TS
/I_A
253
GP
IO19/C
S0/H
_A
052
GP
IO20/C
S1/H
_A
150
GP
IO21/n
CS
49
GP
IO22/W
R/IO
W48
GP
IO23/R
D/IO
R47
GP
IO24/IN
T/IO
RD
Y46
GP
IO25
45
GP
IO26/C
TS
/PW
M3
44
GP
IO27/R
X43
GP
IO28/T
X42
GP
IO29/O
TG
ID41
GP
IO30/S
CL
40
GP
IO31/S
DA
39
VC
C88
VC
C63
VC
C37
GN
D100
GN
D75
GN
D51
GN
D26
DM
1A
22
DP
1A
23
DP
1B
19
DM
1B
18
DM
2B
4D
P2A
10
DM
2A
9
DP
2B
5
AV
CC
21
AG
ND
6
XT
ALIN
29
XT
ALO
UT
28
RE
SE
T85
RE
SE
RV
ED
84
BO
OS
TV
CC
16
VS
WIT
CH
14
BO
OS
TG
ND
15
OT
GV
BU
S11
CS
WIT
CH
A13
CS
WIT
CH
B12
R0
70
410
K0
1 2
X11
B
US
B_
Typ
eA
/Ho
st
VC
C1B
DA
TA
-2B
DA
TA
+3B
GN
D4B
SH
IELD
15
SH
IELD
16
Q0
701
CR
YS
TA
L_
12
MH
z
12
RJ0
70
1nb
_1
0K
0
1 2
10u0
C0
71
710
0nC
07
19
nb_
10
0n
C0
72
7
RJ0
70
40
R0
0
1 2
R0
70
510
K0
1 2
100n
C0
70
3
10
0n
C0
71
4
D0
70
1B
AT
54S
3
12
FB
07
04
BL
M1
8P
G60
0SN
11
2
R0
70
10
R0
01
2
FB
07
05
BL
M2
1P
G3
31
SN
1D
1 2
X11
C
US
B_
Typ
eA
/Ho
st
VC
C1C
DA
TA
-2C
DA
TA
+3C
GN
D4C
X9 CO
N_
DS
UB
_9
M
162738495
+C
07
13
10
0u
U0
70
4
SP
25
26
-1E
N
EN
A1
FLG
A2
FLG
B3
EN
B4
OU
TB
5
GN
D6
IN7
OU
TA
8
C0
71
522
p0
10
0n
C0
71
1
10
0n
C0
70
5
10
0n
C0
70
9
FB
07
03
BL
M2
1P
G3
31
SN
1D
12
R0
70
347
K0
12
C0
71
622
p0
100n
C0
72
1
R0
70
710
K0
1 2
100n
C0
70
4
+C
07
10
10
0u
10
u0C
07
02
100n
C0
72
0
R0
70
615
K0
1 2
C0
72
64
u70
R0
70
20
R0
01
2
+C
07
08
10
0u
U0
70
1
MA
X32
32/T
SS
OP
C1+
1
C1-
3
C2+
4
C2-
5
V+
2
V-
6
T1IN
11
T2IN
10
R1IN
13
R2IN
8
T1O
UT
14
T2O
UT
7
R1O
UT
12
R2O
UT
9
VC
C16
GN
D15
C0
71
21
u00
RJ0
70
3nb
_1
0K0
1 2
U0
70
3
SP
25
26
-1E
N
EN
A1
FLG
A2
FLG
B3
EN
B4
OU
TB
5
GN
D6
IN7
OU
TA
8
10
0n
C0
72
4
FB
07
02
BL
M2
1P
G3
31
SN
1D
12
X10
US
B m
iniA
B 4
40
47
9-1
VB
US
1
D-
2
D+
3
ID4
GN
D5
SH
16
SH
27
SH
38
SH
49
R0
70
8nb
_1M
00
12
10
0n
C0
70
6
FB
07
01
BL
M2
1P
G3
31
SN
1D
12
C0
72
51
00
n
X11
A
US
B_
Typ
eA
/Ho
st
VC
C1A
DA
TA
-2A
DA
TA
+3A
GN
D4A
SH
IELD
13
SH
IELD
14
1n00
C0
72
310
0nC
07
22
100n
C0
71
8
RJ0
70
20
R0
0
1 2
53
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 26. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
EX
PC
ON
_IO
1E
XP
CO
N_I
O3
EX
PC
ON
_IO
5E
XP
CO
N_I
O7
EX
PC
ON
_IO
9E
XP
CO
N_I
O11
EX
PC
ON
_IO
13E
XP
CO
N_I
O15
EX
PC
ON
_IO
20
EX
PC
ON
_IO
23
EX
PC
ON
_IO
26
EX
PC
ON
_IO
0E
XP
CO
N_I
O2
EX
PC
ON
_IO
4E
XP
CO
N_I
O6
EX
PC
ON
_IO
8E
XP
CO
N_I
O10
EX
PC
ON
_IO
12E
XP
CO
N_I
O14
EX
PC
ON
_IO
16E
XP
CO
N_I
O17
EX
PC
ON
_IO
18E
XP
CO
N_I
O19
EX
PC
ON
_IO
21E
XP
CO
N_I
O22
EX
PC
ON
_IO
24E
XP
CO
N_I
O25
EX
PC
ON
_IO
27E
XP
CO
N_I
O28
HP
E_
RE
SO
UT
#
CA
RD
SE
L#
CA
RD
SE
L#
EX
PC
ON
_C
LK
INE
XP
CO
N_C
LKO
UT
EX
PC
ON
_OS
C
HP
E_
RE
SO
UT
#
BB
3V
3_
IO[2
1:0
]
BB
3V
3_
IO[2
1:0
]
EX
PC
ON
_3V
3
EX
PC
ON
_IO
[45
:0]
BB
3V3_
CLK
0+B
B3
V3_
CLK
0-
EX
PC
ON
_IO
39E
XP
CO
N_I
O37
EX
PC
ON
_IO
35E
XP
CO
N_I
O33
EX
PC
ON
_IO
31E
XP
CO
N_I
O29
EX
PC
ON
_IO
30E
XP
CO
N_I
O32
EX
PC
ON
_IO
34E
XP
CO
N_I
O36
EX
PC
ON
_IO
38
EX
PC
ON
_2V
5
EX
PC
ON
_OS
CE
XP
CO
N_
CL
KIN
EX
PC
ON
_CLK
OU
T
EX
PC
ON
_3V
3
EX
PC
ON
_IO
40E
XP
CO
N_I
O41
EX
PC
ON
_IO
42E
XP
CO
N_I
O43
EX
PC
ON
_IO
44E
XP
CO
N_I
O45
BB
3V
3_IO
3
BB
3V
3_IO
2
BB
3V
3_IO
1
BB
3V
3_IO
0
BB
3V
3_IO
4
EX
PC
ON
_2V
5
BB
3V
3_IO
5
BB
3V
3_IO
6
BB
3V
3_IO
7
BB
3V
3_IO
8
BB
3V
3_IO
9
BB
3V
3_IO
10
BB
3V
3_IO
11
BB
3V
3_IO
12
BB
3V
3_
IO[2
1:0
]
BB
3V
3_IO
13
BB
3V
3_IO
14
BB
3V
3_IO
15
BB
3V
3_IO
16
BB
3V
3_IO
17
BB
3V
3_IO
18
BB
3V
3_IO
19
BB
3V
3_IO
20
BB
3V
3_IO
21
BB
3V
3_C
LK0-
BB
3V3_
CLK
0+
SA
TA
_XT
2D0+
SA
TA
_XT
2D0-
SA
TA
_XT
1D0-
SA
TA
_XT
1D0+
SA
TA
_XT
1D1-
SA
TA
_XT
1D1+
SA
TA
_XT
2D1-
SA
TA
_XT
2D1+
SA
TA
_X1D
1+S
AT
A_X
1D1-
SA
TA
_X2D
0+S
AT
A_X
2D0-
SA
TA
_X1D
0+S
AT
A_X
1D0-
SA
TA
_X2D
1+S
AT
A_X
2D1-
SA
TA
_X2D
1+S
AT
A_X
2D1-
SA
TA
_XT
2D0-
SA
TA
_XT
2D0+
SA
TA
_X2D
0+S
AT
A_X
2D0-
SA
TA
_XT
1D1-
SA
TA
_XT
1D1+
SA
TA
_XT
1D0+
SA
TA
_XT
1D0-
SA
TA
_X1D
0-S
AT
A_X
1D0+
SA
TA
_X1D
1+S
AT
A_X
1D1-
SA
TA
_XT
2D1-
SA
TA
_XT
2D1+
VC
C3
V3
GN
DG
ND
VC
C3
V3
GN
D
VC
C2
V5
GN
D
GN
D
VC
C3
V3
VC
C5
V0
GN
DG
ND
_H
S
GN
D_
HS
CA
RD
SE
L#
2
EX
PC
ON
_C
LK
IN2
EX
PC
ON
_CLK
OU
T2
EX
PC
ON
_O
SC
6
HP
E_
RE
SO
UT
#2
,6,7
,8
BB
3V
3_
IO[2
1:0
]2
EX
PC
ON
_IO
[45
:0]
2
BB
3V3_
CLK
0+2
BB
3V
3_C
LK0-
2
SA
TA
_X1D
1+2
SA
TA
_X1D
1-2
SA
TA
_X2D
0+2
SA
TA
_X2D
0-2
SA
TA
_X1D
0+2
SA
TA
_X1D
0-2
SA
TA
_X2D
1+2
SA
TA
_X2D
1-2
:te
eh
S:t c
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
visi
on
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
stra
ße
119
A-4
232
Hag
enbe
rgo
fP
age
Hp
e_
min
i LE
C2
09
_E
xpC
on
_P
roto
Are
a
csam
R0
1
Tu
esd
ay,
De
cem
be
r 1
4,
20
04
14
:28
:58
Mon
day,
Sep
tem
ber 0
4, 2
006
17
:15
:10
129
Offp
age
Exp
ansi
on C
onne
ctor
Pro
toty
ping
Are
a (R
M2.
54)
of F
PG
A
Pin 2 removed for coding
of expansion board
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Place the 0402-resistors of the LVDS termination
as close as possible to the FPGA.
LVDS
DIFF
Sternpunkt X16
SA
TA
-Con
nect
or
TP
0910
4
TP
0935
TP
0996
TP
0912
TP
0963
TP
0912
4
TP
0954
TP
0911
7
TP
0944
TP
0908
TP
0910
6
R0
907
0R
00
12
TP
0936
TP
0921
TP
0964
TP
0986
TP
0912
5
R0
901
0R
00
1 2
TP
0957
TP
0911
5
R0
909
nb
_10
0R
12
TP
0946
TP
0910
7
TP
0913
5
TP
0926
TP
0965
TP
0985
TP
0912
6
TP
0955
TP
0920
TP
0911
6
R0
914
0R
00
12
TP
0947
TP
0910
8
TP
0909
TP
0975
TP
0913
6
TP
0925
TP
0966
TP
0912
9
R0
915
nb
_10
0R
12
TP
0934
TP
0956
TP
0911
8
TP
0948
TP
0976
TP
0998
TP
0913
7
TP
0969
TP
0922
TP
0912
7
R0
913
0R
00
12
TP
0958
TP
0903
TP
0911
9
TP
0938
TP
0977
TP
0913
3
TP
0910
TP
0913
8
R0
910
0R
00
12
TP
0967
TP
0912
8
TP
0901
TP
0959
TP
0987
TP
0912
0
TP
0937
TP
0923
TP
0978
TP
0914
1
R0
911
0R
00
12
TP
0968
TP
0913
0
TP
0927
TP
0960
TP
0904
TP
0988
TP
0911
0
R0
916
0R
00
12
TP
0981
TP
0911
TP
0913
9
TP
0970
X13
HD
R4
0
12
34
56
78
910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TP
0924
TP
0913
1
X15
CO
N_
SA
TA
GN
D1
A+
2
A-
3
GN
D4
B-
5
B+
6
GN
D7
TP
0928
TP
0950
TP
0912
1
TP
0915
TP
0989
TP
0979
TP
0914
0
TP
0971
TP
0999
TP
0913
2
TP
0929
TP
0949
R0
908
0R
00
12
TP
0990
R0
904
10K
0
1 2
TP
0980
TP
0914
TP
0914
2
X14
HD
R4
0
12
34
56
78
910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TP
0939
TP
0972
TP
0916
TP
0910
0
TP
0905
TP
0912
2
TP
0930
TP
0993
TP
0982
TP
0914
3
TP
0940
TP
0962
R0
912
nb
_10
0R
12
TP
0910
9
TP
0910
1
TP
0933
TP
0913
X16
CO
N_
SA
TA
GN
D1
A+
2
A-
3
GN
D4
B-
5
B+
6
GN
D7
TP
0991
TP
0917
TP
0983
TP
0902
TP
0911
1
TP
0914
4
TP
0941
TP
0961
TP
0910
2T
P09
06
TP
0931
TP
0992
TP
0984
TP
0951
R0
905
0R
00
12
TP
0911
2
TP
0913
4
TP
0942
TP
0910
5
TP
0918
R0
90
20
R0
0
1 2
TP
0932
TP
0994
TP
0952
TP
0974
TP
0997
TP
0911
3
TP
0945
TP
0910
3T
P09
07
TP
0995
R0
906
nb
_10
0R
12
TP
0912
3
TP
0953
TP
0919
TP
0973
TP
0911
4
TP
0943
54
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 27. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
EX
PC
ON
_IO
1E
XP
CO
N_
IO3
EX
PC
ON
_IO
5E
XP
CO
N_
IO7
EX
PC
ON
_IO
9E
XP
CO
N_
IO1
1E
XP
CO
N_
IO1
3E
XP
CO
N_
IO1
5
EX
PC
ON
_IO
20
EX
PC
ON
_IO
23
EX
PC
ON
_IO
26
EX
PC
ON
_IO
0E
XP
CO
N_
IO2
EX
PC
ON
_IO
4E
XP
CO
N_
IO6
EX
PC
ON
_IO
8E
XP
CO
N_
IO1
0E
XP
CO
N_
IO1
2E
XP
CO
N_
IO1
4
EX
PC
ON
_IO
16
EX
PC
ON
_IO
17
EX
PC
ON
_IO
18
EX
PC
ON
_IO
19
EX
PC
ON
_IO
21
EX
PC
ON
_IO
22
EX
PC
ON
_IO
24
EX
PC
ON
_IO
25
EX
PC
ON
_IO
27
EX
PC
ON
_IO
28
HP
E_
RE
SO
UT
#
CA
RD
SE
L#
CA
RD
SE
L#
EX
PC
ON
_C
LK
INE
XP
CO
N_
CL
KO
UT
EX
PC
ON
_O
SC
HP
E_
RE
SO
UT
#
BB
3V
3_
IO[2
1:0
]
BB
3V
3_
IO[2
1:0
]
EX
PC
ON
_3V
3
EX
PC
ON
_IO
[45
:0]
BB
3V
3_
CLK
0+B
B3
V3
_C
LK0-
EX
PC
ON
_IO
39
EX
PC
ON
_IO
37
EX
PC
ON
_IO
35
EX
PC
ON
_IO
33
EX
PC
ON
_IO
31
EX
PC
ON
_IO
29
EX
PC
ON
_IO
30
EX
PC
ON
_IO
32
EX
PC
ON
_IO
34
EX
PC
ON
_IO
36
EX
PC
ON
_IO
38
EX
PC
ON
_2V
5
EX
PC
ON
_O
SC
EX
PC
ON
_C
LK
INE
XP
CO
N_
CL
KO
UT
EX
PC
ON
_3V
3
EX
PC
ON
_IO
40
EX
PC
ON
_IO
41
EX
PC
ON
_IO
42
EX
PC
ON
_IO
43
EX
PC
ON
_IO
44
EX
PC
ON
_IO
45
BB
3V
3_
IO3
BB
3V
3_
IO2
BB
3V
3_
IO1
BB
3V
3_
IO0
BB
3V
3_
IO4
EX
PC
ON
_2V
5
BB
3V
3_
IO5
BB
3V
3_
IO6
BB
3V
3_
IO7
BB
3V
3_
IO8
BB
3V
3_
IO9
BB
3V
3_
IO1
0
BB
3V
3_
IO1
1
BB
3V
3_
IO1
2
BB
3V
3_
IO[2
1:0
]
BB
3V
3_
IO1
3
BB
3V
3_
IO1
4
BB
3V
3_
IO1
5
BB
3V
3_
IO1
6
BB
3V
3_
IO1
7
BB
3V
3_
IO1
8
BB
3V
3_
IO1
9
BB
3V
3_
IO2
0
BB
3V
3_
IO2
1
BB
3V
3_
CLK
0-
BB
3V
3_
CLK
0+
SA
TA
_XT
2D0+
SA
TA
_XT
2D0-
SA
TA
_XT
1D0-
SA
TA
_XT
1D0+
SA
TA
_XT
1D1-
SA
TA
_XT
1D1+
SA
TA
_XT
2D1-
SA
TA
_XT
2D1+
SA
TA
_X1D
1+S
AT
A_X
1D1-
SA
TA
_X2D
0+S
AT
A_X
2D0-
SA
TA
_X1D
0+S
AT
A_X
1D0-
SA
TA
_X2D
1+S
AT
A_X
2D1-
SA
TA
_X2D
1+S
AT
A_X
2D1-
SA
TA
_XT
2D0-
SA
TA
_XT
2D0+
SA
TA
_X2D
0+S
AT
A_X
2D0-
SA
TA
_XT
1D1-
SA
TA
_XT
1D1+
SA
TA
_XT
1D0+
SA
TA
_XT
1D0-
SA
TA
_X1D
0-S
AT
A_X
1D0+
SA
TA
_X1D
1+S
AT
A_X
1D1-
SA
TA
_XT
2D1-
SA
TA
_XT
2D1+
VC
C3
V3
GN
DG
ND
VC
C3
V3
GN
D
VC
C2
V5
GN
D
GN
D
VC
C3
V3
VC
C5
V0
GN
DG
ND
_H
S
GN
D_
HS
CA
RD
SE
L#
2
EX
PC
ON
_C
LK
IN2
EX
PC
ON
_C
LK
OU
T2
EX
PC
ON
_O
SC
6
HP
E_
RE
SO
UT
#2
,6,7
,8
BB
3V
3_
IO[2
1:0
]2
,3
EX
PC
ON
_IO
[45
:0]
2
BB
3V
3_C
LK0+
2B
B3
V3
_C
LK0-
2
SA
TA
_X1D
1+2
SA
TA
_X1D
1-2
SA
TA
_X2D
0+2
SA
TA
_X2D
0-2
SA
TA
_X1D
0+2
SA
TA
_X1D
0-2
SA
TA
_X2D
1+2
SA
TA
_X2D
1-2
:te
eh
S:tc
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
vis
ion
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
stra
ße
119
A-4
232
Hag
enbe
rgo
fP
age
aer
Aot
orP
_no
CpxE
_9
02
CE
L ini
m_
ep
H cs
am
R0
1
Tu
esd
ay,
De
cem
be
r 1
4,
20
04
14
:28
:58
Tu
esd
ay,
Ju
ly 1
5,
20
08
10
:27
:40
129
Offp
age
Exp
an
sio
n C
onne
ctor
Pro
toty
pin
g A
rea
(R
M2
.54
) of
FP
GA
Pin 2 removed for coding
of expansion board
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Place the 0402-resistors of the LVDS termination
as close as possible to the FPGA.
LVDS
DIFF
Sternpunkt X16
SA
TA
-Co
nn
ect
or
TP
0910
4
TP
0935
TP
0996
TP
0912
TP
0963
TP
0912
4
TP
0954
TP
0911
7
TP
0944
TP
0908
TP
0910
6
R0
90
70
R0
01
2
TP
0936
TP
0921
TP
0964
TP
0986
TP
0912
5
R0
90
10
R0
0
1 2
TP
0957
TP
0911
5
R0
90
9n
b_
10
0R
12
TP
0946
TP
0910
7
TP
0913
5
TP
0926
TP
0965
TP
0985
TP
0912
6
TP
0955
TP
0920
TP
0911
6
R0
91
40
R0
01
2
TP
0947
TP
0910
8
TP
0909
TP
0975
TP
0913
6
TP
0925
TP
0966
TP
0912
9
R0
91
5n
b_
10
0R
12
TP
0934
TP
0956
TP
0911
8
TP
0948
TP
0976
TP
0998
TP
0913
7
TP
0969
TP
0922
TP
0912
7
R0
91
30
R0
01
2
TP
0958
TP
0903
TP
0911
9
TP
0938
TP
0977
TP
0913
3
TP
0910
TP
0913
8
R0
91
00
R0
01
2
TP
0967
TP
0912
8
TP
0901
TP
0959
TP
0987
TP
0912
0
TP
0937
TP
0923
TP
0978
TP
0914
1
R0
91
10
R0
01
2
TP
0968
TP
0913
0
TP
0927
TP
0960
TP
0904
TP
0988
TP
0911
0
R0
91
60
R0
01
2
TP
0981
TP
0911
TP
0913
9
TP
0970
X13
HD
R4
0
12
34
56
78
910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TP
0924
TP
0913
1
X15
CO
N_
SA
TA
GN
D1
A+
2
A-
3
GN
D4
B-
5
B+
6
GN
D7
TP
0928
TP
0950
TP
0912
1
TP
0915
TP
0989
TP
0979
TP
0914
0
TP
0971
TP
0999
TP
0913
2
TP
0929
TP
0949
R0
90
80
R0
01
2
TP
0990
R0
90
410
K0
1 2
TP
0980
TP
0914
TP
0914
2
X14
HD
R4
0
12
34
56
78
910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TP
0939
TP
0972
TP
0916
TP
0910
0
TP
0905
TP
0912
2
TP
0930
TP
0993
TP
0982
TP
0914
3
TP
0940
TP
0962
R0
91
2n
b_
10
0R
12
TP
0910
9
TP
0910
1
TP
0933
TP
0913
X16
CO
N_
SA
TA
GN
D1
A+
2
A-
3
GN
D4
B-
5
B+
6
GN
D7
TP
0991
TP
0917
TP
0983
TP
0902
TP
0911
1
TP
0914
4
TP
0941
TP
0961
TP
0910
2T
P09
06
TP
0931
TP
0992
TP
0984
TP
0951
R0
90
50
R0
01
2
TP
0911
2
TP
0913
4
TP
0942
TP
0910
5
TP
0918
R0
90
20
R0
01 2
TP
0932
TP
0994
TP
0952
TP
0974
TP
0997
TP
0911
3
TP
0945
TP
0910
3T
P09
07
TP
0995
R0
90
6n
b_
10
0R
12
TP
0912
3
TP
0953
TP
0919
TP
0973
TP
0911
4
TP
0943
55
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 28. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
AC
97
_B
ITC
LK
AC
97
_S
DA
TA
_OU
T
AC
97
_S
YN
CA
C9
7_
SD
AT
A_
IN
AC
97
_EX
T_C
LKA
C9
7_
RE
SE
T#
AC
97
_E
AP
D
VG
A_
RD
0
VG
A_
GR
0
VG
A_B
L0
VG
A_
RD
1
VG
A_
GR
1
VG
A_B
L1
VG
A_
VS
YN
C
VG
A_
RD
0V
GA
_R
D1
VG
A_
GR
0
VG
A_B
L0V
GA
_G
R1
VG
A_
HS
YN
CV
GA
_BL1
VG
A_
VS
YN
C
VG
A_
HS
YN
C
VG
A_
RD
_X
VG
A_G
R_X
VG
A_B
L_X
AC
97
_3
DN
AC
97
_S
PD
IF_
OU
T
AC
97
_3
DP
AC
97
_A
FIL
T1
AC
97
_A
FIL
T2
AC
97
_A
FIL
T3
AC
97
_S
YN
C
AC
97
_V
RE
FO
UT
AC
97
_S
DA
TA
_IN
AC
97
_S
DA
TA
_OU
T
AC
97
_H
P_
OU
T_
C
AC
97
_B
ITC
LK
AC
97
_E
AP
D
AC
97
_R
ES
ET
#AC
97
_L
INE
IN_
RA
C9
7_
LIN
EO
UT
_L
AC
97
_A
OU
T_L
AC
97
_V
RE
F
AC
97
_P
IN4
8A
C9
7_
PIN
47
AC
97_
XT
L_O
UT
AC
97
_3
DF
LT
AC
97
_A
IN_
R
AC
97
_L
INE
OU
T_
RA
C9
7_
AO
UT
_R
AC
97
_A
IN_
L
AC
97
_H
P_
OU
T_
L
AC
97
_H
P_
OU
T_
R
AC
97
_EX
T_C
LK
AC
97
_X
TL
_IN
AC
97
_L
INE
IN_
L
GN
D
GN
DG
ND
A_
AU
D
GN
DA
_A
C
VD
D3
V3
_A
C9
7
GN
DA
_A
C
GN
DA
_A
C
VD
DA
5V
0_
AC
97G
ND
A_
AC
GN
DA
_A
C
VC
C5
V0
VD
DA
5V
0_
AC
97
VD
DA
5V
0_
AC
97
GN
DA
_A
C
GN
DA
_A
C
GN
D
GN
DA
_A
C
GN
DA
_A
C
VD
D3
V3
_A
C9
7V
CC
3V
3
GN
D
GN
DA
_A
CG
ND
GN
DA
_A
C
GN
DA
_A
C
GN
DA
_A
C
GN
D
AC
97
_B
ITC
LK
2A
C9
7_
SD
AT
A_O
UT
2
AC
97
_S
YN
C2
AC
97
_EX
T_C
LK2
AC
97
_R
ES
ET
#2
AC
97
_E
AP
D2
VG
A_
RD
02
VG
A_
RD
12
VG
A_
GR
02
VG
A_
GR
12
VG
A_B
L02
VG
A_
HS
YN
C2
VG
A_B
L12
VG
A_
VS
YN
C2
AC
97
_S
DA
TA
_IN
2
:te
eh
S:tc
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
vis
ion
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
stra
ße
119
A-4
232
Hag
enbe
rgo
fP
age
AG
V_oid u
A_
01
2C
EL i
nim
_e
pH c
sa
mR
01
Tu
esd
ay,
De
cem
be
r 1
4,
20
04
14
:11
:30
We
dn
esd
ay,
Ju
ly 1
6,
20
08
09
:47
:58
1210
Au
dio
Co
de
c
VG
A I
nter
face
Offp
age
Headphone / Line-out
LINE-IN
Locate under CODEC
use 60 mil wide trace between
digital and analog GND planes
47n0
(AD1881)
PB-Free Part:
LM4549BVHX
10u0
(VT1612A)
100n
(VT1612A)
1u00
(AD1881)
1u00
(AD1881)
100n
(AD1881)
1n00
(CS4299)
10n0
(CS4299)
C0805
C0805
C0603
C0603
C0603
C0603
<---
<---
--->
--->
--->
PLL --->
LOCATE SEPERATE ANALOG POWER AND ANALOG GROUND
PLANES DIRECTLY ON TOP OF ONE ANOTHER WITHOUT
OVERLAPPING DIGITAL POWER OR GROUND PLANES. A SINGLE
ZERO OHM RESISTOR SHOULD LINK THE DIGITAL AND ANALOG
GROUND PLANES AS CLOSE TO THE CODEC AS POSSIBLE.
270p
(VT1612A)
270p
(VT1612A)
nb_10k0
(VT1612A)
Connect ANALOG GND to
GND on Plane
realized in CAMTASTIC
1u00 (CS4299)
3u30 (LM4480)
10u0 (VT1612A)
C0603
C0603
C1206
270p
(VT1612A)
R1
02
5n
b_0
R0
0
R1
02
4n
b_
0R
00
R1
02
3n
b_0
R0
0
1u0
0C
10
17
FB
10
04
BL
M2
1P
G3
31S
N1D
12
nb_
1n0
0C
10
24
C1
02
8
33p0
nb_
10
0n
C1
02
2
R1
02
71M
0012
10
0n
C1
01
2
LC
10
04
NF
E3
1P
T2
22
Z1
E9
21
3
+
C1
00
2
1u00
12
R1
00
84
7k0
R1
01
82
70
R
22
n0C
10
11
R1
01
22
70
R
FB
10
03
BL
M2
1P
G3
31S
N1D
12
LC
10
02
NF
E3
1P
T2
22
Z1
E9
21
3
C1
02
9
33p0
R1
02
13
3R
0
10u0
C1
01
3
1n0
0C
10
10
1n0
0C
10
08
nb_
1n0
0C
10
26
R1
00
94
7k0
+
C1
00
3
1u00
12
R1
02
2n
b_0
R0
0
+
C1
00
1
1u00
12
R1
01
32
70
R
10
0p
C1
00
7
TP
1001
LC
10
01
NF
E3
1P
T2
22
Z1E
92
1
3
10
0n
C1
01
9
TP
1002
1u0
0C
10
15
R1
00
74
7k0
FB
10
05
BL
M2
1P
G3
31
SN
1D1
2
10
0p
C1
00
6
NF
_R
NF
_L
Shi
eld
X17
A
ST
-42
35
-3/3
-N
5L
1L
4L
2L
1
TP
1003
R1
01
42
70
R
R1
01
02
70
R
10
0n
C1
01
6
FB
10
01
BL
M1
8P
G60
0SN
11
2
R1
01
91
0k0
10
0n
C1
01
4
1n0
0C
10
04
R1
02
6
0R
00
12
+
C1
00
5
1u00
12
R1
01
52
70
R
FB
10
06
BL
M2
1P
G3
31
SN
1D1
2
nb_
1n0
0C
10
25
FB
10
02
BL
M1
8P
G60
0SN
11
2
R1
00
31
k00
nb_
10
u0C
10
23
R1
02
0n
b_0
R0
0
X19
CO
N_
DS
UB
_1
5F
7 2 8 3 9 410 516
11
12
13
14
15
nb_
22
n0C
10
21
R1
02
80
R0
Q1
001
nb_
24
.57
6M
Hz
12
R1
00
20
R0
0
10
0n
C1
01
8
ANALOG
DIGITAL INTERFACE
POWER
CLOCK
U1
00
1
AC
'97
CO
DE
C
LIN
E_IN
_L
23
LIN
E_IN
_R
24
CD
_L
18
CD
_G
ND
19
CD
_R
20
MIC
121
MIC
222
VID
EO
_L
16
AU
X_R
15
PC
_B
EE
P12
AU
X_L
14
VID
EO
_R
17
LIN
E_O
UT
_R
36
XT
L_IN
2
XT
L_O
UT
3
PH
ON
E13
LIN
E_O
UT
_L
35
SD
AT
A_O
UT
5
DV
DD
29
DV
DD
11
AV
DD
25
AV
SS
26
DV
SS
14
DV
SS
27
BIT
_C
LK
6
SY
NC
10
RE
SE
T11
SD
AT
A_IN
8
HP
_O
UT
_L
39
HP
_O
UT
_R
41
MO
NO
_O
UT
37
VR
EF
OU
T28
RE
FF
LT
27
3D
P34
3D
N33
ID0
45
ID1
46
EA
PD
/NC
47
AF
ILT
1/N
C29
AF
ILT
2/N
C30
AF
ILT
3/N
C31
3D
FLT
/NC
32
NC
/AV
DD
38
HP
_O
UT
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/NC
40
AV
SS
/NC
42
NC
43
HP
P/N
C44
SP
DIF
/NC
48
R1
00
61
k00
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01
62
70
R
R1
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44
7k0
nb_
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NF
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NF
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eld
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35
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27
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10
03
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T2
22
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21
3
1n0
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10
09
56
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 29. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
PW
_T1B
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TE
PW
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eh
S:t c
ejor
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tho
rs:
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ichm
ann
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ctro
nics
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vis
ion
:
Cre
ate
d:
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st m
od
ifie
d:
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h (A
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& C
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20
04
09
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Tu
esd
ay,
Ju
ly 1
5,
20
08
10
:27
:40
1211
3.3
V (
1A
) /
1.2
V (
2A
) D
C/D
C-C
on
vert
er
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nn
ect
AN
AL
OG
GN
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oG
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on
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ne
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age
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20V
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ll
ma
x 1
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1%
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34
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Pla
ce th
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rts
C11
03, C
1105
and
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as c
lose
as
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ible
to th
e pi
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f the
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ext
ra A
NA
LO
G G
ND
pla
neco
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ect
ed
with
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on
pla
ne
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)
2.5
V
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ma
x 2
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2.5
V P
G
Mis
cella
ne
ou
s
Set the jumper to 1-2 for 2.5V and to 3-2 for 2.6V
(This is important for the DDR SDRAM module)
10
u0C
11
29
L110
1
33
u0
R1
11
93
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1 2
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11
11
22
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6
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11
13
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er
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11
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21
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TS
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1
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EN
ER
2
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NT
ER
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lace
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lde
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10
1
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ILL
11
01
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ILL
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11
06
47
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R1
11
50
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33
12
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10
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12
10
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10
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TP
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INT
1
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10
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11
10
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11
02
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ree
n
22
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11
8
SI6
96
6D
QT
1101
A4
1 23
optional
Pa
d11
02A
rtN
r05
28
1
LD
11
01
LE
D g
ree
n
nb_
10
n0C
11
25
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10
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LT1
1 2
R1
11
43
30
R
12
+C
11
30
22
0u
R1
10
715
K0
12
optional
Pad
1105
Art
Nr0
52
81
optional
Pa
d11
01A
rtN
r05
28
1
4p7
0C
11
32
Pla
ceH
old
er
PH
11
02
21
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96
6D
QT
1102
A4
1 23
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10
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0540
LT1
1 2
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10
815
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12
10
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C1
12
4
D1
10
2
10
MQ
040N
12
R1
11
247
K0
12
SI6
96
6D
QT
1101
B5
8 76
100n
C1
12
1
optional
Pad
1104
Art
Nr0
52
81
R1
11
61
0R
01
2
33p0
C1
12
2
+C
11
07
47u0
D1
10
51
0M
Q04
0N
12
S
DG
T11
03S
i34
45
DV
3
4 1256
optional
Pa
d11
03A
rtN
r05
28
1
1u00
C1
13
4
R1
11
315
K0
12
TP
1104
TE
ST
PO
INT
1
10
u0C
11
10
R1
11
742
K2
1 2
10
u0C
11
31
optional
A11
01J
um
pe
r
10
0n
C1
10
3
33
p0C
11
23
L110
2
10
0u0
X21
HD
R3
123
R1
11
05
R1
0
12
TP
1103
TE
ST
PO
INT
1
R1
10
20
R0
25
12
R1
10
55
R1
0
12
10
0n
C1
12
0
U1
10
2
TP
S64
203D
BV
T
EN
1
GN
D2
FB
3
SW
6
VIN
5
ISE
NS
E4
10
0n
C1
10
5
optional
La
bel0
1LA
BE
L
10
u0C
11
04
+C
11
33
10
0u
U1
10
1
LT
C1
62
8-S
SO
P28
VIN
24
BO
OS
T1
25
SW
126
TG
127
BG
123
Ext
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cc22
INT
Vcc
21
FR
EQ
SE
T5
SE
NS
E1-
3
Vos1
4
BO
OS
T2
18
TG
216
SW
217
BG
219
SE
NS
E2+
14
SE
NS
E2-
13
Vos2
12
SE
NS
E1+
2F
LT
CP
L28
FC
B7
3V
3O
ut
10
ST
BY
MD
6
RU
N/S
S1
1
RU
N/S
S2
15
ITH
18
ITH
211
SG
ND
9
PG
ND
20
DR
ILL
11
04
DR
ILL
1n00
C1
12
7
R1
10
45K
10
1 2
10
u0C
11
15
R1
10
610
K0
1 2
TP
1101
TE
ST
PO
INT
1
10
u0C
11
14
180p
C1
10
9
10
n0C
11
19
R1
11
83
6k0
1 2
1n00
C1
12
6
22
0p
C1
11
7
DR
ILL
11
03
DR
ILL
1n00
C1
11
2
SI6
96
6D
QT
1102
B5
8 76
DR
ILL
11
02
DR
ILL
1n00
C1
10
8
180p
C1
12
8
R1
12
01
00
R
12
57
LatticeMico32/DSP Development BoardLattice Semiconductor for LatticeECP2 User’s Guide
Figure 30. 5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
:te
eh
S:tc
ejor
P Au
tho
rs:
Gle
ichm
ann
Ele
ctro
nics
Re
vis
ion
:
Cre
ate
d:
La
st m
od
ifie
d:
IFW
:
Res
earc
h (A
ustri
a) G
mbH
& C
o K
GH
aupt
stra
ße
119
A-4
232
Hag
enbe
rgo
fP
age
set
oN
ng is
eD
_2
12
CE
L ini
m_
ep
H cs
am
R0
1
Fri
da
y, S
ep
tem
be
r 2
4,
20
04
12
:39
:35
Tu
esd
ay,
Ju
ly 1
5,
20
08
10
:27
:40
1212
General routing requirements:
Netclasses:
Clocks: max. 120mm, daisy chain routing
Differential: routing as differential signals, length matching +/- 20 mils
Memory: Signals: max 150mm, length matching +/- 10mm
length max. 100mm, route as daisy chain
Recommended