Lecture 0: Introduction - Harvey Mudd Collegepages.hmc.edu/harris/class/e158/04/lect0.pdf · CMOS...

Introduction toCMOS VLSI

Design

Lecture 0: Introduction

David Harris

Harvey Mudd CollegeSpring 2004

0: Introduction Slide 2CMOS VLSI Design

Administriviaq Name Tentsq Syllabus

– About the Instructor– Office Hours & Lab Assistant Hours– Labs, Problem Sets, and Project– Grading– Collaboration

q Textbookq Cross-cultural Chip Design

0: Introduction Slide 3CMOS VLSI Design

Introductionq Integrated circuits: many transistors on one chip.q Very Large Scale Integration (VLSI): very manyq Complementary Metal Oxide Semiconductor

– Fast, cheap, low power transistorsq Today: How to build your own simple CMOS chip

– CMOS transistors– Building logic gates from transistors– Transistor layout and fabrication

q Rest of the course: How to build a good CMOS chip

0: Introduction Slide 4CMOS VLSI Design

Silicon Latticeq Transistors are built on a silicon substrateq Silicon is a Group IV materialq Forms crystal lattice with bonds to four neighbors

Si SiSi

Si SiSi

Si SiSi

0: Introduction Slide 5CMOS VLSI Design

Dopantsq Silicon is a semiconductorq Pure silicon has no free carriers and conducts poorlyq Adding dopants increases the conductivityq Group V: extra electron (n-type)q Group III: missing electron, called hole (p-type)

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-

0: Introduction Slide 6CMOS VLSI Design

p-n Junctionsq A junction between p-type and n-type semiconductor

forms a diode.q Current flows only in one direction

p-type n-type

anode cathode

0: Introduction Slide 7CMOS VLSI Design

nMOS Transistorq Four terminals: gate, source, drain, bodyq Gate – oxide – body stack looks like a capacitor

– Gate and body are conductors– SiO2 (oxide) is a very good insulator– Called metal – oxide – semiconductor (MOS)

capacitor– Even though gate is

no longer made of metal

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

0: Introduction Slide 8CMOS VLSI Design

nMOS Operationq Body is commonly tied to ground (0 V)q When the gate is at a low voltage:

– P-type body is at low voltage– Source-body and drain-body diodes are OFF– No current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S

0: Introduction Slide 9CMOS VLSI Design

nMOS Operation Cont.q When the gate is at a high voltage:

– Positive charge on gate of MOS capacitor– Negative charge attracted to body– Inverts a channel under gate to n-type– Now current can flow through n-type silicon from

source through channel to drain, transistor is ON

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S

0: Introduction Slide 10CMOS VLSI Design

pMOS Transistorq Similar, but doping and voltages reversed

– Body tied to high voltage (VDD)– Gate low: transistor ON– Gate high: transistor OFF– Bubble indicates inverted behavior

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+

0: Introduction Slide 11CMOS VLSI Design

Power Supply Voltageq GND = 0 Vq In 1980’s, VDD = 5Vq VDD has decreased in modern processes

– High VDD would damage modern tiny transistors– Lower VDD saves power

q VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

0: Introduction Slide 12CMOS VLSI Design

Transistors as Switchesq We can view MOS transistors as electrically

controlled switchesq Voltage at gate controls path from source to drain

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFF ON

ON OFF

0: Introduction Slide 13CMOS VLSI Design

CMOS Inverter

1

0

YA VDD

A Y

GNDA Y

0: Introduction Slide 14CMOS VLSI Design

CMOS Inverter

01

0

YA VDD

A=1 Y=0

GND

ON

OFF

A Y

0: Introduction Slide 15CMOS VLSI Design

CMOS Inverter

01

10

YA VDD

A=0 Y=1

GND

OFF

ON

A Y

0: Introduction Slide 16CMOS VLSI Design

CMOS NAND Gate

1

1

0

0

A

1

0

1

0

YB

A

B

Y

0: Introduction Slide 17CMOS VLSI Design

CMOS NAND Gate

1

1

0

0

A

1

0

1

10

YB

A=0

B=0

Y=1OFF

ON ON

OFF

0: Introduction Slide 18CMOS VLSI Design

CMOS NAND Gate

1

1

0

0

A

11

0

1

10

YB

A=0

B=1

Y=1OFF

OFF ON

ON

0: Introduction Slide 19CMOS VLSI Design

CMOS NAND Gate

1

1

0

0

A

11

10

1

10

YB

A=1

B=0

Y=1ON

ON OFF

OFF

0: Introduction Slide 20CMOS VLSI Design

CMOS NAND Gate

1

1

0

0

A

11

10

01

10

YB

A=1

B=1

Y=0ON

OFF OFF

ON

0: Introduction Slide 21CMOS VLSI Design

CMOS NOR Gate

1

1

0

0

A

01

00

01

10

YB

A

BY

0: Introduction Slide 22CMOS VLSI Design

3-input NAND Gateq Y pulls low if ALL inputs are 1q Y pulls high if ANY input is 0

0: Introduction Slide 23CMOS VLSI Design

3-input NAND Gateq Y pulls low if ALL inputs are 1q Y pulls high if ANY input is 0

A

B

Y

C

0: Introduction Slide 24CMOS VLSI Design

CMOS Fabricationq CMOS transistors are fabricated on silicon waferq Lithography process similar to printing pressq On each step, different materials are deposited or

etchedq Easiest to understand by viewing both top and

cross-section of wafer in a simplified manufacturing process

0: Introduction Slide 25CMOS VLSI Design

Inverter Cross-sectionq Typically use p-type substrate for nMOS transistorsq Requires n-well for body of pMOS transistors

n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor

0: Introduction Slide 26CMOS VLSI Design

Well and Substrate Tapsq Substrate must be tied to GND and n-well to VDD

q Metal to lightly-doped semiconductor forms poor connection called Shottky Diode

q Use heavily doped well and substrate contacts / taps

n+

p substrate

p+

n well

A

YGND VDD

n+p+

substrate tap well tap

n+ p+

0: Introduction Slide 27CMOS VLSI Design

Inverter Mask Setq Transistors and wires are defined by masksq Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tapnMOS transistor pMOS transistor

0: Introduction Slide 28CMOS VLSI Design

Detailed Mask Viewsq Six masks

– n-well– Polysilicon– n+ diffusion– p+ diffusion– Contact– Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

0: Introduction Slide 29CMOS VLSI Design

Fabrication Stepsq Start with blank waferq Build inverter from the bottom upq First step will be to form the n-well

– Cover wafer with protective layer of SiO2 (oxide)– Remove layer where n-well should be built– Implant or diffuse n dopants into exposed wafer– Strip off SiO2

p substrate

0: Introduction Slide 30CMOS VLSI Design

Oxidationq Grow SiO2 on top of Si wafer

– 900 – 1200 C with H2O or O2 in oxidation furnace

p substrate

SiO2

0: Introduction Slide 31CMOS VLSI Design

Photoresistq Spin on photoresist

– Photoresist is a light-sensitive organic polymer– Softens where exposed to light

p substrate

SiO2

Photoresist

0: Introduction Slide 32CMOS VLSI Design

Lithographyq Expose photoresist through n-well maskq Strip off exposed photoresist

p substrate

SiO2

Photoresist

0: Introduction Slide 33CMOS VLSI Design

Etchq Etch oxide with hydrofluoric acid (HF)

– Seeps through skin and eats bone; nasty stuff!!!q Only attacks oxide where resist has been exposed

p substrate

SiO2

Photoresist

0: Introduction Slide 34CMOS VLSI Design

Strip Photoresistq Strip off remaining photoresist

– Use mixture of acids called piranah etchq Necessary so resist doesn’t melt in next step

p substrate

SiO2

0: Introduction Slide 35CMOS VLSI Design

n-wellq n-well is formed with diffusion or ion implantationq Diffusion

– Place wafer in furnace with arsenic gas– Heat until As atoms diffuse into exposed Si

q Ion Implanatation– Blast wafer with beam of As ions– Ions blocked by SiO2, only enter exposed Si

n well

SiO2

0: Introduction Slide 36CMOS VLSI Design

Strip Oxideq Strip off the remaining oxide using HFq Back to bare wafer with n-wellq Subsequent steps involve similar series of steps

p substraten well

0: Introduction Slide 37CMOS VLSI Design

Polysiliconq Deposit very thin layer of gate oxide

– < 20 Å (6-7 atomic layers)q Chemical Vapor Deposition (CVD) of silicon layer

– Place wafer in furnace with Silane gas (SiH4)– Forms many small crystals called polysilicon– Heavily doped to be good conductor

Thin gate oxidePolysilicon

p substraten well

0: Introduction Slide 38CMOS VLSI Design

Polysilicon Patterningq Use same lithography process to pattern polysilicon

Polysilicon

p substrate

Thin gate oxidePolysilicon

n well

0: Introduction Slide 39CMOS VLSI Design

Self-Aligned Processq Use oxide and masking to expose where n+ dopants

should be diffused or implantedq N-diffusion forms nMOS source, drain, and n-well

contact

p substraten well

0: Introduction Slide 40CMOS VLSI Design

N-diffusionq Pattern oxide and form n+ regionsq Self-aligned process where gate blocks diffusionq Polysilicon is better than metal for self-aligned gates

because it doesn’t melt during later processing

p substraten well

n+ Diffusion

0: Introduction Slide 41CMOS VLSI Design

N-diffusion cont.q Historically dopants were diffusedq Usually ion implantation todayq But regions are still called diffusion

n wellp substrate

n+n+ n+

0: Introduction Slide 42CMOS VLSI Design

N-diffusion cont.q Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+

0: Introduction Slide 43CMOS VLSI Design

P-Diffusionq Similar set of steps form p+ diffusion regions for

pMOS source and drain and substrate contact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+

0: Introduction Slide 44CMOS VLSI Design

Contactsq Now we need to wire together the devicesq Cover chip with thick field oxideq Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact

0: Introduction Slide 45CMOS VLSI Design

Metalizationq Sputter on aluminum over whole waferq Pattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal

0: Introduction Slide 46CMOS VLSI Design

Layoutq Chips are specified with set of masksq Minimum dimensions of masks determine transistor

size (and hence speed, cost, and power)q Feature size f = distance between source and drain

– Set by minimum width of polysiliconq Feature size improves 30% every 3 years or soq Normalize for feature size when describing design

rulesq Express rules in terms of λ = f/2

– E.g. λ = 0.3 µm in 0.6 µm process

0: Introduction Slide 47CMOS VLSI Design

Simplified Design Rulesq Conservative rules to get you started

0: Introduction Slide 48CMOS VLSI Design

Inverter Layoutq Transistor dimensions specified as Width / Length

– Minimum size is 4λ / 2λ, sometimes called 1 unit– In f = 0.6 µm process, this is 1.2 µm wide, 0.6 µm

long

0: Introduction Slide 49CMOS VLSI Design

Summaryq MOS Transistors are stack of gate, oxide, siliconq Can be viewed as electrically controlled switchesq Build logic gates out of switchesq Draw masks to specify layout of transistors

q Now you know everything necessary to start designing schematics and layout for a simple chip!