Lecture 10: Sequential Circuitsengrclasses.pitt.edu/.../2008/Lectures/lect10_081021.pdf · 2015. 8....

Introduction toCMOS VLSI

Design

Lecture 10: Sequential Circuits

David Harris

Harvey Mudd CollegeSpring 2004

10: Sequential Circuits Slide 2CMOS VLSI Design

OutlineFloorplanningSequencingSequencing Element DesignMax and Min-DelayClock SkewTime BorrowingTwo-Phase Clocking

Project StrategyProposal– Specifies inputs, outputs, relation between them

Floorplan– Begins with block diagram– Annotate dimensions and location of each block– Requires detailed paper design

Schematic– Make paper design simulate correctly

Layout– Physical design, DRC, NCC, ERC

FloorplanHow do you estimate block areas?– Begin with block diagram– Each block has

• Inputs• Outputs• Function (draw schematic)• Type: array, datapath, random logic

Estimation depends on type of logic

MIPS Floorplan

datapath2700 λ x 1050 λ

(2.8 Mλ2)

alucontrol200 λ x 100 λ

(20 kλ2)

zipper 2700 λ x 250 λ

2700 λ

1690 λ

wiring channel: 30 tracks = 240 λ

mips(4.6 Mλ2)

bitslice 2700 λ x 100 λ

control1500 λ x 400 λ

(0.6 Mλ2)

3500 λ

5000λ

5000 λ

10 I/O pads

Area EstimationArrays:– Layout basic cell– Calculate core area from # of cells– Allow area for decoders, column circuitry

Datapaths– Sketch slice plan– Count area of cells from cell library– Ensure wiring is possible

Random logic– Compare complexity do a design you have done

MIPS Slice Plan

writedriver

dualsram

dualsrambit0

srampullup

readmux

fulladder

register fileramslice

ALUadrmux

IR3...0 writem

srcB srcA aluout

zerodetect

memdatawritedata

pcimmediate

aluout

aluresult

srcBsrcAbitlines

44 24 93 93 93 93 93 44 24 52 48 48 48 48 16 86 93 93 93 9344 24 4424131 131 13139 39 39 39 160

Typical Layout DensitiesTypical numbers of high-quality layoutDerate by 2 for class projects to allow routing and some sloppy layout.Allocate space for big wiring channels

100 λ2 / bitROM100 λ2 / bitDRAM1000 λ2 / bitSRAM

250 – 750 λ2 / transistorOr 6 WL + 360 λ2 / transistor

Datapath1000-1500 λ2 / transistorRandom logic (2 metal layers)AreaElement

SequencingCombinational logic– output depends on current inputs

Sequential logic– output depends on current and previous inputs– Requires separating previous, current, future– Called state or tokens– Ex: FSM, pipeline

in out

clk clk clk

PipelineFinite State Machine

Sequencing Cont.If tokens moved through pipeline at constant speed, no sequencing elements would be necessaryEx: fiber-optic cable– Light pulses (tokens) are sent down cable– Next pulse sent before first reaches end of cable– No need for hardware to separate pulses– But dispersion sets min time between pulses

This is called wave pipelining in circuitsIn most circuits, dispersion is high– Delay fast tokens so they don’t catch slow ones.

Sequencing OverheadUse flip-flops to delay fast tokens so they move through exactly one stage each cycle.Inevitably adds some delay to the slow tokensMakes circuit slower than just the logic delay– Called sequencing overhead

Some people call this clocking overhead– But it applies to asynchronous circuits too– Inevitable side effect of maintaining sequence

Sequencing ElementsLatch: Level sensitive– a.k.a. transparent latch, D latch

Flip-flop: edge triggered– A.k.a. master-slave flip-flop, D flip-flop, D register

Timing Diagrams– Transparent– Opaque– Edge-trigger

D Flop

clk clk

Q (latch)

Q (flop)

Sequencing ElementsLatch: Level sensitive– a.k.a. transparent latch, D latch

Flip-flop: edge triggered– A.k.a. master-slave flip-flop, D flip-flop, D register

Timing Diagrams– Transparent– Opaque– Edge-trigger

D Flop

clk clk

Q (latch)

Q (flop)

Latch DesignPass Transistor LatchPros++

Cons––––––

Latch DesignPass Transistor LatchPros+ Tiny+ Low clock load

Cons– Vt drop– nonrestoring– backdriving– output noise sensitivity– dynamic– diffusion input

Used in 1970’s

Latch DesignTransmission gate+- D Q

Latch DesignTransmission gate+ No Vt drop- Requires inverted clock D Q

Latch DesignInverting buffer+++ Fixes either

••

Latch DesignInverting buffer+ Restoring+ No backdriving+ Fixes either

• Output noise sensitivity• Or diffusion input

– Inverted output

Latch DesignTristate feedback+–

Latch DesignTristate feedback+ Static– Backdriving risk

Static latches are now essential

Latch DesignBuffered input++

Latch DesignBuffered input+ Fixes diffusion input+ Noninverting

Latch DesignBuffered output+

Latch DesignBuffered output+ No backdriving

Widely used in standard cells+ Very robust (most important)- Rather large- Rather slow (1.5 – 2 FO4 delays)- High clock loading

Latch DesignDatapath latch+-

Latch DesignDatapath latch+ Smaller, faster- unbuffered input

Flip-Flop DesignFlip-flop is built as pair of back-to-back latches

EnableEnable: ignore clock when en = 0– Mux: increase latch D-Q delay– Clock Gating: increase en setup time, skew

Symbol Multiplexer Design Clock Gating Design

ResetForce output low when reset assertedSynchronous vs. asynchronous

Dreset

Synchronous R

synchronous Reset

bol FlopD Q

reset reset

Set / ResetSet forces output high when enabled

Flip-flop with asynchronous set and reset

set reset

Sequencing MethodsFlip-flops2-Phase LatchesPulsed Latches

Flip-FlopsFl

clk clk

φp φp

φ1 φ1φ2

2-Phase Transparent Latches

Pulsed Latches

Combinational Logic

CombinationalLogic

Combinational Logic

tnonoverlap tnonoverlap

Half-Cycle 1 Half-Cycle 1

Timing Diagrams

tpdCombinational

LogicA Y

clk clk

tsetup thold

tsetup tholdtpcq

tpdqtcdqLatch/Flop Hold Timethold

Latch/Flop Setup Timetsetup

Latch D-Q Cont. Delaytpcq

Latch D-Q Prop Delaytpdq

Latch/Flop Clk-Q Cont. Delaytccq

Latch/Flop Clk-Q Prop Delaytpcq

Logic Cont. Delaytcd

Logic Prop. Delaytpd

Contamination and Propagation Delays

Max-Delay: Flip-Flops

clk clk

Combinational Logic

tsetuptpcq

( )sequencing overhead

pd ct T≤ −1442443

Max-Delay: Flip-Flops

clk clk

Combinational Logic

tsetuptpcq

( )setup

sequencing overhead

pd c pcqt T t t≤ − +14243

Max Delay: 2-Phase Latches

φ1 φ1φ2

CombinationalLogic 1

Q2 Q3D1 D2 D3

( )1 2

sequencing overhead

pd pd pd ct t t T= + ≤ −1442443

Max Delay: 2-Phase Latches

φ1 φ1φ2

Q2 Q3D1 D2 D3

( )1 2

sequencing overhead

2pd pd pd c pdqt t t T t= + ≤ −123

Max Delay: Pulsed Latches

Q1 Q2D1 D2

φp φp

Combinational LogicL1 L2

(a) tpw > tsetup

(b) tpw < tsetup

tpd tsetup

( )sequencing overhead

max pd ct T≤ −14444244443

Max Delay: Pulsed Latches

Q1 Q2D1 D2

φp φp

Combinational LogicL1 L2

(a) tpw > tsetup

(b) tpw < tsetup

tpd tsetup

( )setup

sequencing overhead

max ,pd c pdq pcq pwt T t t t t≤ − + −14444244443

Min-Delay: Flip-Flops

cdt ≥ CL

Min-Delay: Flip-Flops

holdcd ccqt t t≥ − CL

Min-Delay: 2-Phase Latches

1, 2 cd cdt t ≥CL

tnonoverlap

Hold time reduced by nonoverlap

Paradox: hold applies twice each cycle, vs. only once for flops.

But a flop is made of two latches!

Min-Delay: 2-Phase Latches

1, 2 hold nonoverlapcd cd ccqt t t t t≥ − −CL

tnonoverlap

Hold time reduced by nonoverlap

Paradox: hold applies twice each cycle, vs. only once for flops.

But a flop is made of two latches!

Min-Delay: Pulsed Latches

cdt ≥ CL

φp tpw

Hold time increased by pulse width

Min-Delay: Pulsed Latches

holdcd ccq pwt t t t≥ − +CL

φp tpw

Hold time increased by pulse width

Time BorrowingIn a flop-based system:– Data launches on one rising edge– Must setup before next rising edge– If it arrives late, system fails– If it arrives early, time is wasted– Flops have hard edges

In a latch-based system– Data can pass through latch while transparent– Long cycle of logic can borrow time into next– As long as each loop completes in one cycle

Time Borrowing Example

Combinational Logic CombinationalLogic

Borrowing time acrosshalf-cycle boundary

Borrowing time acrosspipeline stage boundary

(b) Latc

hCombinational Logic Combinational

Loops may borrow time internally but must complete within the cycle

φ1 φ1

How Much Borrowing?

φ1 φ2

Combinational Logic 1Q2D1 D2

Tc/2 Nominal Half-Cycle 1 Delay

tborrow

tnonoverlap

tsetup

( )borrow setup nonoverlap2cTt t t≤ − +

2-Phase Latches

borrow setuppwt t t≤ −

Pulsed Latches

Clock SkewWe have assumed zero clock skewClocks really have uncertainty in arrival time– Decreases maximum propagation delay– Increases minimum contamination delay– Decreases time borrowing

Skew: Flip-Flops

clk clk

Combinational Logic

tsetup

( )setup skew

sequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t

≤ − + +

≥ − +

144424443

Skew: Latches

φ1 φ1φ2

Q2 Q3D1 D2 D3

sequencing overhead

1 2 hold nonoverlap skew

borrow setup nonoverlap skew

pd c pdq

cd cd ccq

t t t t t t

Tt t t t

≤ −

≥ − − +

≤ − + +

2-Phase Latches

setup skew

sequencing overhead

hold skew

borrow setup skew

max ,pd c pdq pcq pw

cd pw ccq

t T t t t t t

t t t t t

t t t t

≤ − + − +

≥ + − +

≤ − +

1444442444443

Pulsed Latches

Two-Phase ClockingIf setup times are violated, reduce clock speedIf hold times are violated, chip fails at any speedIn this class, working chips are most important– No tools to analyze clock skew

An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap timesCall these clocks φ1, φ2 (ph1, ph2)

Safe Flip-FlopIn class, use flip-flop with nonoverlapping clocks– Very slow – nonoverlap adds to setup time– But no hold times

In industry, use a better timing analyzer– Add buffers to slow signals if hold time is at risk

φ1φ1

SummaryFlip-Flops:– Very easy to use, supported by all tools

2-Phase Transparent Latches:– Lots of skew tolerance and time borrowing

Pulsed Latches:– Fast, some skew tol & borrow, hold time risk

Lecture 10: Sequential Circuitsengrclasses.pitt.edu/.../2008/Lectures/lect10_081021.pdf · 2015. 8....

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