Lecture #21 - Introduction to and Analysis of Sequential...

ECE 331 – Digital System Design

Introduction to and Analysis ofSequential Logic Circuits

(Lecture #21)

The slides included herein were taken from the materials accompanying

Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,

and were used with permission from Cengage Learning.

Spring 2011 ECE 331 - Digital System Design 2

Combinational vs. Sequential

● Combinational Logic Circuit

– Output is a function only of the present inputs.

– Does not have state information.

– Does not require memory.

● Sequential Logic Circuit (aka. Finite State Machine)

– Output is a function of the present state.

– Has state information

– Requires memory.

– Uses Flip-Flops to implement memory.

Spring 2011 ECE 331 - Digital System Design 3

Synchronous vs. Asynchronous

● Synchronous Sequential Logic Circuit

– Clocked

– All Flip-Flops use the same clock and change state on the same triggering edge.

● Asynchronous Sequential Logic Circuit

– No clock

– Can change state at any instance in time.

– Faster but more complex than synchronous sequential circuits.

Spring 2011 ECE 331 - Digital System Design 4

Sequential Circuits: General Model

● Memory

– Stores state information

– Realized using Flip-Flops

● Combinational Logic

– Implements Flip-Flop input functions and output functions

– Realized using logic gates, a ROM or a PLA

Spring 2011 ECE 331 - Digital System Design 5

Sequential Circuits: Models

● Moore Machine

– Outputs are a function of the present state.

– Outputs are independent of the inputs.

– State diagram includes an output value for each state.

● Mealy Machine

– Outputs are a function of the present state and the present input.

– State diagram includes an input and output value for each transition (between states).

Spring 2011 ECE 331 - Digital System Design 6

Sequential Circuits: Models

Spring 2011 ECE 331 - Digital System Design 7

Sequential Circuits: Mealy Model

output

Present state

Next state

Spring 2011 ECE 331 - Digital System Design 8

Sequential Circuits: Moore Model

Presentstate

output

Next state

Spring 2011 ECE 331 - Digital System Design 9

Sequential Circuits: State Diagram

State

Output

Input

Moore Machine

Each node in the graphrepresents a state in the

sequential circuit.

Spring 2011 ECE 331 - Digital System Design 10

Sequential Circuits: State Diagram

Mealy Machine

Each node in the graph

represents a state in the

sequential circuit.

Input

State

Output

Spring 2011 ECE 331 - Digital System Design 11

Sequential Circuit Analysis

Spring 2011 ECE 331 - Digital System Design 12

Analysis: Signal Tracing

1.Assume an initial state for the sequential circuit.

All Flip-Flops reset to 0 (unless otherwise stated).

2.Determine the sequential circuit output and the flip-flop inputs for the first input value in the sequence.

3.Determine the next state of each Flip-Flop

After the next active clock edge.

4.Determine the sequential circuit output and the flip-flop inputs for the next value in the sequence.

5.Repeat steps 3 & 4.

Spring 2011 ECE 331 - Digital System Design 13

Example: Moore Machine

input

Flip-Flop inputs

output

State = AB

Spring 2011 ECE 331 - Digital System Design 14

Example: Moore Machine

0 1 1 0 1

Spring 2011 ECE 331 - Digital System Design 15

Example: Mealy Machine

Spring 2011 ECE 331 - Digital System Design 16

Example: Mealy Machine

Spring 2011 ECE 331 - Digital System Design 17

Analysis: State Tables and Graphs

Although constructing timing charts is satisfactory for small

circuits and short input sequences, the construction of state

tables and graphs provides a more systematic approach

which is useful for the analysis of larger circuits and which

leads to a general synthesis procedure for sequential

circuits.

The state table specifies the next state and output of a

sequential circuit in terms of its present state and input.

Spring 2011 ECE 331 - Digital System Design 18

Analysis Procedure

1. Determine the Flip-Flop input equations

2. Determine the Sequential Circuit output equations

3. Derive the Next State equation for each Flip-Flop

Using the corresponding input equation

And the Flip-Flop characteristic equation

4. Plot the Next State K-map for each Flip-Flop

5. Construct the State Table (aka. Transition Table)

Assign a state label to each binary state assignment

6. Draw the corresponding state diagram (aka. state graph)

Spring 2011 ECE 331 - Digital System Design 19

Example:

Analyze a sequential circuit using D Flip-Flops

Spring 2011 ECE 331 - Digital System Design 20

Example: Analysis (D FF)

Derive the State Table for the following Sequential Logic Circuit:

Spring 2011 ECE 331 - Digital System Design 21

Example: Analysis (D FF)

The flip-flop input equations are:

DA = X xor B' DB = X or A

Z = A xor B

The next-state equations for the flip-flops are:

A+ = DA = X xor B' B+ = DB = X or A

The sequential circuit output equation is:

Spring 2011 ECE 331 - Digital System Design 22

Example: Analysis (D FF)

The corresponding next-state (K-) maps are:

Spring 2011 ECE 331 - Digital System Design 23

Example: Analysis (D FF)

The state table, or transition table, is then:

A+ B+

A B X = 0 X = 1 Z

0 0 1 0 0 1 0

0 1 0 0 1 1 1

1 1 0 1 1 1 0

1 0 1 1 0 1 1

Present Next State

State X = 0 X = 1 Output

S0 S3 S1 0

S1 S0 S2 1

S2 S1 S2 0

S3 S2 S1 1

Spring 2011 ECE 331 - Digital System Design 24

Example: Analysis (D FF)

The state diagram can then be drawn from the state table:

Spring 2011 ECE 331 - Digital System Design 25

Example:

Analyze a sequential circuit using JK Flip-Flops

Spring 2011 ECE 331 - Digital System Design 26

Example: Analysis (JK FF)

Derive the State Table for the following Sequential Logic Circuit:

Spring 2011 ECE 331 - Digital System Design 27

Example: Analysis (JK FF)

The flip-flop input equations are:

The next-state equations for the flip-flops are:

The sequential circuit output equation is:

JA = X.B JB = X

KA = X KB = X.A

Z = X.B' + X.A + X'.A'.B

A+ = JA.A' + KA'.A B+ = JB.B' + KB'.B

A+ = X.B.A' + X.A B+ = X.B' + X.A.B

Spring 2011 ECE 331 - Digital System Design 28

Example: Analysis (JK FF)

The corresponding next-state (K-) maps are

Spring 2011 ECE 331 - Digital System Design 29

Example: Analysis (JK FF)

The state table, and transition table, is then:

Spring 2011 ECE 331 - Digital System Design 30

Example: Analysis (JK FF)

The state diagram can then be drawn from the state table:

Spring 2011 ECE 331 - Digital System Design 31

Example:

Analyze a serial adder

Spring 2011 ECE 331 - Digital System Design 32

Example: Serial Adder

The serial adder adds two n-bit binary numbers.

(serial) inputs

(serial) output

presentstate

next state

Spring 2011 ECE 331 - Digital System Design 33

Example: Serial Adder

Truth Table for the Full Adder:

Spring 2011 ECE 331 - Digital System Design 34

Example: Serial Adder

The state table, or transition table, is then:

Ci+1 Sum

Ci XY = 00 XY = 01 XY = 10 XY = 11 XY = 00 XY = 01 XY = 10 XY = 11

0 0 0 0 1 0 1 1 0

1 0 1 1 1 1 0 0 1

Present Next State Output

State XY = 00 XY = 01 XY = 10 XY = 11 XY = 00 XY = 01 XY = 10 XY = 11

S0 S0 S0 S0 S1 0 1 1 0

S1 S0 S1 S1 S1 1 0 0 1

Spring 2011 ECE 331 - Digital System Design 35

Example: Serial Adder

State Graph for the Serial Adder:

What type of state machine is this?

Spring 2011 ECE 331 - Digital System Design 36

Example: Serial Adder

Timing Diagram for the Serial Adder:

Spring 2011 ECE 331 - Digital System Design 37

Example:

Analyze a state machine with multiple inputs.

Spring 2011 ECE 331 - Digital System Design 38

Example: Multiple Inputs

State Table for a state machine with multiple inputs:

Spring 2011 ECE 331 - Digital System Design 39

Example: Multiple Inputs

State Graph for a state machine with multiple inputs:

How many paths leave each state?

What type of statemachine is this?

Spring 2011 ECE 331 - Digital System Design 40

Questions?