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Introduction toCMOS VLSI
Design
Lecture 8: Combinational Circuits
David Harris
Harvey Mudd CollegeSpring 2004
8: Combinational Circuits Slide 2CMOS VLSI Design
Outlineq Bubble Pushingq Compound Gatesq Logical Effort Exampleq Input Orderingq Asymmetric Gatesq Skewed Gatesq Best P/N ratio
8: Combinational Circuits Slide 3CMOS VLSI Design
Example 1module mux(input s, d0, d1,
output y);
assign y = s ? d1 : d0;endmodule
1) Sketch a design using AND, OR, and NOT gates.
8: Combinational Circuits Slide 5CMOS VLSI Design
Example 22) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.
8: Combinational Circuits Slide 8CMOS VLSI Design
Example 33) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
8: Combinational Circuits Slide 10CMOS VLSI Design
Compound Gatesq Logical Effort of compound gates
ABCD
Y
ABC Y
A
BC
C
A B
A
B
C
D
A
C
B
D
2
21
4
44
2
2 2
2
4
4 4
4
gA = 6/3
gB = 6/3
gC = 5/3
p = 7/3
gA =
gB =
gC =
p =
gD =
YA
A Y
gA = 3/3
p = 3/3
2
1YY
unit inverter AOI21 AOI22
A
C
DE Y
B
Y
B C
A
D
E
A
B
C
D E
gA =
gB =
gC =
gD =
2
2 2
22
6
6
6 6
3
p =
gE =
Complex AOI
Y A B C= +i Y A B C D= +i i ( )Y A B C D E= + +i iY A=
8: Combinational Circuits Slide 12CMOS VLSI Design
Example 4q The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs.
8: Combinational Circuits Slide 14CMOS VLSI Design
NAND Solution
Y
D0S
D1S
8: Combinational Circuits Slide 16CMOS VLSI Design
Compound Solution
Y
D0SD1S
8: Combinational Circuits Slide 18CMOS VLSI Design
Example 5q Annotate your designs with transistor sizes that
achieve this delay.
YY
8: Combinational Circuits Slide 20CMOS VLSI Design
Input Orderq Our parasitic delay model was too simple
Calculate parasitic delay for Y falling If A arrives latest? If B arrives latest?
6C
2C2
2
22
B
Ax
Y
8: Combinational Circuits Slide 22CMOS VLSI Design
Inner & Outer Inputsq Outer input is closest to rail (B)q Inner input is closest to output (A)
q If input arrival time is known Connect latest input to inner terminal
2
2
22
B
A
Y
8: Combinational Circuits Slide 23CMOS VLSI Design
Asymmetric Gatesq Asymmetric gates favor one input over anotherq Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same
q gA =q gB = q gtotal = gA + gB = q Asymmetric gate approaches g = 1 on critical inputq But total logical effort goes up
Areset
Y
4/3
2
reset
AY
8: Combinational Circuits Slide 25CMOS VLSI Design
Symmetric Gatesq Inputs can be made perfectly symmetric
A
B
Y2
1
1
2
1
1
8: Combinational Circuits Slide 26CMOS VLSI Design
Skewed Gatesq Skewed gates favor one edge over anotherq Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor
q Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. gu = gd =
1/2
2A Y
1
2A Y
1/2
1A Y
HI-skewinverter
unskewed inverter(equal rise resistance)
unskewed inverter(equal fall resistance)
8: Combinational Circuits Slide 28CMOS VLSI Design
HI- and LO-Skewq Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.
q Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nMOS) LO-skew gates favor falling output (small pMOS)
q Logical effort is smaller for favored directionq But larger for the other direction
8: Combinational Circuits Slide 29CMOS VLSI Design
Catalog of Skewed Gates
1/2
2A Y
Inverter
B
AY
B
A
NAND2 NOR2
HI-skew
LO-skew1
1A Y
B
AY
B
A
gu = 5/6gd = 5/3gavg = 5/4
gu = 4/3gd = 2/3gavg = 1
gu =gd =gavg =
gu =gd =gavg =
gu =gd =gavg =
gu =gd =gavg =
Y
Y
1
2A Y
2
2
22
B
AY
B
A
11
4
4
unskewedgu = 1gd = 1gavg = 1
gu = 4/3gd = 4/3gavg = 4/3
gu = 5/3gd = 5/3gavg = 5/3
Y
8: Combinational Circuits Slide 32CMOS VLSI Design
Asymmetric Skewq Combine asymmetric and skewed gates
Downsize noncritical transistor on unimportant input
Reduces parasitic delay for critical input
Areset
Y
4
4/3
21
reset
AY
8: Combinational Circuits Slide 33CMOS VLSI Design
Best P/N Ratioq We have selected P/N ratio for unit rise and fall
resistance ( = 2-3 for an inverter).q Alternative: choose ratio for least average delayq Ex: inverter
Delay driving identical inverter tpdf = tpdr = tpd = Differentiate tpd w.r.t. P Least delay for P =
1
PA
8: Combinational Circuits Slide 35CMOS VLSI Design
P/N Ratiosq In general, best P/N ratio is sqrt of equal delay ratio.
Only improves average delay slightly for inverters But significantly decreases area and power
Inverter NAND2 NOR2
1
1.414A Y
2
2
22
B
AY
B
A
11
2
2
fastestP/N ratio gu =
gd =gavg =
gu =gd =gavg =
gu =gd =gavg =
Y
8: Combinational Circuits Slide 37CMOS VLSI Design
Observationsq For speed:
NAND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving input
q For area and power: Many simple stages vs. fewer high fan-in stages
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