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CSE CSE 533533: : Advanced Advanced Computer ArchitectureComputer Architecturess
PipeliningPipeliningInstructor: Gürhan Küçük
Yeditepe University
Lecture notes based on notes by Mark D. Hill and John P. ShenUpdated by Mikko Lipasti
© Hill, Shen, Lipasti2
PipeliningPipelining
Forecast– Big Picture– Datapath– Control– Data Hazards
StallsForwarding
– Control Hazards– Exceptions
© Hill, Shen, Lipasti3
MotivationMotivation
Single cycle implementation– CPI = 1– Cycle = imem + RFrd + ALU + dmem +
RFwr + muxes + control– E.g. 500+250+500+500+250+0+0 = 2000ps– Time/program = N x 2ns
Instructions CyclesProgram Instruction
TimeCycle
(code size N)
X X
(CPI) (cycle time)
© Hill, Shen, Lipasti4
Idea!Idea!We use 500 MHz clock with 2ns cycle timeBut, we can reduce cycle time and divide the task into several stages so we can speed things up– i.e. 0.5ns cycle time => 2 GHz clock
© Hill, Shen, Lipasti5
MulticycleMulticycle
Multicycle implementation:
i+4Fi+3
MXDFi+2XDFi+1
WMXDFi
13
12
11
10
987654321Cycle:Instr:
© Hill, Shen, Lipasti6
ButBut……
Multicycle implementation– CPI = 3, 4, 5– Cycle = max(memory, RF, ALU, mux, control)– =max(500,250,500) = 500ps– Time/prog = N x 4 x 500 = N x 2000ps = N x 2ns
Would like:– CPI = 1 + overhead from hazards (later)– Cycle = 500ps + overhead– In practice, ~3x improvement
© Hill, Shen, Lipasti7
Big PictureBig Picture
Instruction latency = 5 cyclesInstruction throughput = 1/5 instr/cycleCPI = 5 cycles per instructionInstead– Pipelining: process instructions like a lunch
buffet– ALL microprocessors use it
E.g. Pentium-IV, Athlon, Power4
© Hill, Shen, Lipasti8
Big PictureBig Picture
Instruction Latency = 5 cycles (same)Instruction throughput = 1 instr/cycleCPI = 1 cycle per instructionCPI = cycle between instruction completion = 1
© Hill, Shen, Lipasti9
Ideal PipeliningIdeal Pipelining
Bandwidth increases linearly with pipeline depthLatency increases by latch delays
GateDelay
Comb. Logicn Gate Delay
GateDelayL Gate
DelayL
L GateDelayL Gate
DelayL
L BW = ~(1/n)
n--2n--2
n--3n--3
n--3
BW = ~(2/n)
BW = ~(3/n)
© Hill, Shen, Lipasti10
Ideal PipeliningIdeal Pipelining
WMXDFi+4WMXDFi+3
WMXDFi+2WMXDFi+1
WMXDFi
13
12
11
10
987654321Cycle:Instr:
© Hill, Shen, Lipasti11
Pipelining IdealismsPipelining Idealisms
Uniform subcomputations– Can pipeline into stages with equal delay
Identical computations– Can fill pipeline with identical work
Independent computations– No relationships between work units
Are these practical?– No, but can get close enough to get significant
speedup
© Hill, Shen, Lipasti12
ComplicationsComplications
Datapath– Five (or more) instructions in flight
Control– Must correspond to multiple instructions
Instructions may have – data and control flow dependences (coming up!)– i.e. units of work are not independent
One may have to stall and wait for another
© Hill, Shen, Lipasti13
An ExampleAn ExampleConsider an unpipelined machine. Assume that it has 20 ns clock and that it uses
cycles for execution frequencyALU 2 30%Branch 5 20%Memory 7 50%
Suppose that due to clock skew and setup, pipelining the machine adds 2 ns overhead to the clock. Ignoring any latency impact, how much speedup in the instruction execution rate will we gain from a pipeline?
© Hill, Shen, Lipasti14
DatapathDatapath (Fig. 6.11)(Fig. 6.11)
© Hill, Shen, Lipasti15
MIPS MIPS Datapath Datapath Without PipeliningWithout Pipelining
What Is What Is PipeliningPipelining
© Hill, Shen, Lipasti16
Pipelined Pipelined DatapathDatapathStart with single-cycle datapathPipelined execution– Assume each instruction has its own datapath– But each instruction uses a different part in every
cycle– Multiplex all on to one datapath– Latches separate cycles (like multicycle)
Ignore hazards for now– Data– Control Instruction�
memory
Address
4
32
0
Add Add�result
Shift�left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M�u�x
0
1
Add
PC
0Write�data
M�u�x
1Registers
Read�data 1
Read�data 2
Read�register 1
Read�register 2
16Sign�
extend
Write�register
Write�data
Read�data
1
ALU�result
M�u�x
ALUZero
ID/EX
Data�memory
Address
© Hill, Shen, Lipasti17
Pipelined Pipelined DatapathDatapath
Instruction�memory
Address
4
32
0
Add Add�result
Shift�left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M�u�x
0
1
Add
PC
0Write�data
M�u�x
1Registers
Read�data 1
Read�data 2
Read�register 1
Read�register 2
16Sign�
extend
Write�register
Write�data
Read�data
1
ALU�result
M�u�x
ALUZero
ID/EX
Data�memory
Address
© Hill, Shen, Lipasti18
The Basic Pipeline For MIPSThe Basic Pipeline For MIPS
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 6 Cycle 7Cycle 5
Instr.
Order
© Hill, Shen, Lipasti19
MIPS FunctionsMIPS FunctionsWhat Is What Is PipeliningPipelining
Instruction Fetch (IF):Send out the PC and fetch the instruction from memory into the instruction register (IR); increment the PC by 4 to address the next sequential instruction.IR holds the instruction that will be used in the next stage.NPC holds the value of the next PC.
Passed To Next StageIR Mem[PC]NPC PC + 4
Instruction�memory
Address
4
32
0
Add Add�result
Shift�left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M�u�x
0
1
Add
PC
0Write�data
M�u�x
1Registers
Read�data 1
Read�data 2
Read�register 1
Read�register 2
16Sign�
extend
Write�register
Write�data
Read�data
1
ALU�result
M�u�x
ALUZero
ID/EX
Data�memory
Address
© Hill, Shen, Lipasti20
Instruction�memory
Address
4
32
0
Add Add�result
Shift�left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M�u�x
0
1
Add
PC
0Write�data
M�u�x
1Registers
Read�data 1
Read�data 2
Read�register 1
Read�register 2
16Sign�
extend
Write�register
Write�data
Read�data
1
ALU�result
M�u�x
ALUZero
ID/EX
Data�memory
Address
MIPS FunctionsMIPS FunctionsWhat Is What Is PipeliningPipelining
Instruction Decode/Register Fetch Cycle (ID):Decode the instruction and access the register file to read the registers.The outputs of the general purpose registers are read into two temporary registers (A & B) for use in later clock cycles.We extend the sign of the lower 16 bits of the Instruction Register.
Passed To Next StageA Regs[IR6..10]
B Regs[IR11..15]
Imm ((IR16) ##IR16..31
© Hill, Shen, Lipasti21
MIPS FunctionsMIPS FunctionsWhat Is What Is PipeliningPipelining
Passed To Next StageIf Memory Reference:ALUOutput A + Imm
If Reg-Reg ALU Inst.:ALUOutput A func. B
If Reg-Imm ALU Inst.:ALUOutput A func. Imm
If Branch:ALUOutput NPC + Imm<<2Cond (A op 0)
Execute Address Calculation (EX):We perform an operation (for an ALU) or an address calculation (if it’s a load or a Branch).If an ALU, actually do the operation. If an address calculation, figure out how to obtain the address and stash away the location of that address for the next cycle.
Instruction�memory
Address
4
32
0
Add Add�result
Shift�left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M�u�x
0
1
Add
PC
0Write�data
M�u�x
1Registers
Read�data 1
Read�data 2
Read�register 1
Read�register 2
16Sign�
extend
Write�register
Write�data
Read�data
1
ALU�result
M�u�x
ALUZero
ID/EX
Data�memory
Address
© Hill, Shen, Lipasti22
MIPS FunctionsMIPS FunctionsWhat Is What Is PipeliningPipelining
Passed To Next StageIf LOAD Inst:LMD Mem[ALUOutput]
If STORE Inst:Mem[ALUOutput] B
If Branch Inst:if (Cond)
PC ALUOutputelse
PC NPCMEMORY ACCESS (MEM):If this is an ALU, do nothing.If a load or store, then access memory.If this is a branch, then update PC
Instruction�memory
Address
4
32
0
Add Add�result
Shift�left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M�u�x
0
1
Add
PC
0Write�data
M�u�x
1Registers
Read�data 1
Read�data 2
Read�register 1
Read�register 2
16Sign�
extend
Write�register
Write�data
Read�data
1
ALU�result
M�u�x
ALUZero
ID/EX
Data�memory
Address
© Hill, Shen, Lipasti23
MIPS FunctionsMIPS FunctionsWhat Is What Is PipeliningPipelining
Passed To Next StageIf Reg-Reg ALU:Regs[IR16..20] ALUOutput
If Reg-Imm ALU:Regs[IR11..15] ALUOutput
If LOAD Inst:Regs[IR11..15] LMD
WRITE BACK (WB):Update the registers from either the ALU or from the data loaded.
Instruction�memory
Address
4
32
0
Add Add�result
Shift�left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M�u�x
0
1
Add
PC
0Write�data
M�u�x
1Registers
Read�data 1
Read�data 2
Read�register 1
Read�register 2
16Sign�
extend
Write�register
Write�data
Read�data
1
ALU�result
M�u�x
ALUZero
ID/EX
Data�memory
Address
© Hill, Shen, Lipasti24
Things to NoticeThings to Notice
For some instructions no processing is done in certain stages:– Register-to-register instructions: No process in
MEM stage– STORE instructions: No process in WB stage
© Hill, Shen, Lipasti25
Things to Notice Things to Notice -- IIII
Instructions may read their operands only when they are in ID stageReason: ???
© Hill, Shen, Lipasti26
Things to Notice Things to Notice -- IIII
Instructions may read their operands only when they are in ID stageReason: Reduces read port requirements on the Register File– Complexity reduction– Power/Energy reduction
© Hill, Shen, Lipasti27
Things to Notice Things to Notice -- IIIIII
Instructions may write their results only when they are in WB stageReason: ???
© Hill, Shen, Lipasti28
Things to Notice Things to Notice -- IIIIII
Instructions may write their results only when they are in WB stageReason: Reduces write port requirements on the Register File– Complexity reduction– Power/Energy reduction
© Hill, Shen, Lipasti29
Pipeline HurdlesPipeline Hurdles
Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle– Structural hazards: HW cannot support this
combination of instructions (single person to fold and put clothes away)
– Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock)
– Control hazards: Pipelining of branches & other instructions that change the PC
– Common solution is to stall the pipeline until the hazard is resolved, inserting one or more “bubbles”in the pipeline
© Hill, Shen, Lipasti30
Pipeline HurdlesPipeline HurdlesDefinition : Conditions that lead to incorrect behavior if not fixed
Structural hazard – two different instructions use same h/w in same cycle
Data hazard – two different instructions use same storage – must appear as if the instructions execute in correct order
Control hazard– one instruction affects which instruction is next
ResolutionPipeline interlock logic detects hazards and fixes them simple solution: stall -increases CPI, decreases performance better solution: partial stall -some instruction stall, others proceed better to stall early than late
© Hill, Shen, Lipasti31
Structural HazardsStructural HazardsWhen two or more different instructions want to use same hardware resource in same cycle
e.g., MEM uses the same memory port as IF as shown in this slide.
Instr.
Order
Time (clock cycles)
Load
Instr 1
Instr 2
Instr 3
Instr 4
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 6 Cycle 7Cycle 5
Reg ALU DMemIfetch Reg
© Hill, Shen, Lipasti32
Structural HazardsStructural HazardsThis is another way of looking at the effect of a stall.I
nstr.
Order
Time (clock cycles)
Load
Instr 1
Instr 2
Stall
Instr 3
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 6 Cycle 7Cycle 5
Reg ALU DMemIfetch Reg
Bubble Bubble Bubble BubbleBubble
© Hill, Shen, Lipasti33
Structural HazardsStructural Hazards
This is another way to represent the stall we saw on the last few pages.
© Hill, Shen, Lipasti34
Structural HazardsStructural HazardsDealing with Structural Hazards
Stall – low cost, simple – Increases CPI – use for rare case since stalling has performance effect
Pipeline hardware resource – useful for multi-cycle resources – good performance – sometimes complex e.g., RAM
Replicate resource – good performance – increases cost (+ maybe interconnect delay) – useful for cheap or divisible resources
© Hill, Shen, Lipasti35
Structural HazardsStructural HazardsStructural hazards are reduced with these rules:
Each instruction uses a resource at most once Always use the resource in the same pipeline stage Use the resource for one cycle only
Many RISC ISA’a designed with this in mind Sometimes very complex to do this. For example, memory of necessity is used in
the IF and MEM stages.
Some common Structural Hazards:Memory - we’ve already mentioned this one.Floating point - Since many floating point instructions require many cycles, it’s easy for them to interfere with each other. Starting up more of one type of instruction than there are resources. For instance, the PA-8600 can support two ALU + two load/store instructions per cycle - that’s how much hardware it has available.
© Hill, Shen, Lipasti36
Structural HazardsStructural Hazards
We want to compare the performance of two machines. Which machine is faster?Machine A: Dual ported memory - so there are no memory stallsMachine B: Single ported memory, but its pipelined implementation has a 1.05 times faster clock rate
Assume:Ideal CPI = 1 for bothLoads are 40% of instructions executed
This is the example on Page 144.
© Hill, Shen, Lipasti37
Data HazardsData Hazards
These occur when at any time, there are instructions active thatneed to access the same data (memory or register) locations.
Where there’s real trouble is when we have:
instruction Ainstruction B
and B manipulates (reads or writes) data before A does. This violates the order of the instructions, since the architecture implies that A completes entirely before B is executed.
© Hill, Shen, Lipasti38
Data HazardsData HazardsRead After Write (RAW)
InstrJ tries to read operand before InstrI writes it
Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication.
Execution Order is:InstrIInstrJ
I: add r1,r2,r3J: sub r4,r1,r3
I Jr1
© Hill, Shen, Lipasti39
Data HazardsData HazardsWrite After Read (WAR)
InstrJ tries to write operand before InstrI reads i– Gets wrong operand
– Called an “anti-dependence” by compiler writers.This results from reuse of the name “r1”.
Can’t happen in MIPS 5 stage pipeline because:– All instructions take 5 stages, and– Reads are always in stage 2, and – Writes are always in stage 5
Execution Order is:InstrIInstrJ
I: sub r4,r1,r3 J: add r1,r2,r3K: mul r6,r1,r7
I Jr1
© Hill, Shen, Lipasti40
Data HazardsData HazardsWrite After Write (WAW)
InstrJ tries to write operand before InstrI writes it– Leaves wrong result ( InstrI not InstrJ )
Called an “output dependence” by compiler writersThis also results from the reuse of name “r1”.
Can’t happen in MIPS 5 stage pipeline because: – All instructions take 5 stages, and – Writes are always in stage 5
Will see WAR and WAW in later more complicated pipes
Execution Order is:InstrIInstrJ
I: sub r1,r4,r3 J: add r1,r2,r3K: mul r6,r1,r7
I Jr1
© Hill, Shen, Lipasti41
Data Flow GraphsData Flow GraphsI1 mul $15, $10, 4I2 addu $24, $6, $15I3 lw $25, 0($24)I4 mul $13, $24, $14I5 addu $14, $6, $13I6 lw $15, 0($14)
I1
I2
$15
I3
$24
I4
I5
I6
$13
$14
$15
$14
$24
© Hill, Shen, Lipasti42
Data HazardsData HazardsSimple Solution to RAW
• Hardware detects RAW and stalls • Assumes register written then read each cycle
+ low cost to implement, simple -- reduces IPC
• Try to minimize stalls
Minimizing RAW stalls
• Bypass/forward/short-circuit (We will use the word “forward”)• Use data before it is in the register
+ reduces/avoids stalls -- complex
• Crucial for common RAW hazards
© Hill, Shen, Lipasti43
Data HazardsData Hazards
The use of the result of the ADD instruction in the next three instructions causes a hazard, since the register is not written until after those instructions read it.
Instr.
Order
add r1,r2,r3
sub r4,r1,r3
and r6,r1,r7
or r8,r1,r9
xor r10,r1,r11
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Time (clock cycles)
IF ID/RF EX MEM WB
Figure 3.9
© Hill, Shen, Lipasti44
Data HazardsData HazardsForwarding To Avoid
Data Hazard
Forwarding is the concept of making data available to the input of the ALU for subsequent instructions, even though the generating instruction hasn’t gotten to WB in order to write the memory or registers.
Figure 3.10
Time (clock cycles)Inst
r.
Order
add r1,r2,r3
sub r4,r1,r3
and r6,r1,r7
or r8,r1,r9
xor r10,r1,r11
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
© Hill, Shen, Lipasti45
Data HazardsData Hazards
There are some instances where hazards occur, even with forwarding.
The data isn’t loaded until after the MEM stage.
Time (clock cycles)
Instr.
Order
lw r1, 0(r2)
sub r4,r1,r6
and r6,r1,r7
or r8,r1,r9
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Figure 3.12
© Hill, Shen, Lipasti46
Data HazardsData Hazards
There are some instances where hazards occur, even with forwarding.
The stall is necessary as shown here.
Figure 3.13
Time (clock cycles)
or r8,r1,r9
Instr.
Order
lw r1, 0(r2)
sub r4,r1,r6
and r6,r1,r7
Reg ALU DMemIfetch Reg
RegIfetch ALU DMem RegBubble
Ifetch ALU DMem RegBubble Reg
Ifetch
ALU DMemBubble Reg
© Hill, Shen, Lipasti47
Data HazardsData HazardsThis is another representation
of the stall.
WBMEMEXIDIFOR R8, R1, R9
WBMEMEXIDIFAND R6, R1, R7
WBMEMEXIDIFSUB R4, R1, R5
WBMEMEXIDIFLW R1, 0(R2)
IF
ID
EX
WBMEMEXIDIFstallOR R8, R1, R9
WBMEMEXIDstallAND R6, R1, R7
WBMEMEXstallIFSUB R4, R1, R5
WBMEMIDIFLW R1, 0(R2)
© Hill, Shen, Lipasti48
Data HazardsData HazardsInstruction scheduled by compiler - move instruction in order to reduce stall.
lw Rb, b -- code sequence for a = b+c before scheduling lw Rc, c Add Ra, Rb, Rc -- stall sw a, Ra lw Re, e -- code sequence for d = e+f before scheduling lw Rf, f sub Rd, Re, Rf -- stall sw d, Rd
Arrangement of code after scheduling.
lw Rb, b lw Rc, c lw Re, e Add Ra, Rb, Rclw Rf, f sw a, Ra sub Rd, Re, Rfsw d, Rd
Pipeline Scheduling
© Hill, Shen, Lipasti49
Data HazardsData Hazards Pipeline Scheduling
% loads stalling pipeline
0% 20% 40% 60% 80%
tex
spice
gcc
25%
14%
31%
65%
42%
54%
scheduled unscheduled
© Hill, Shen, Lipasti50
CControlontrol HazardsHazards
Control hazards can cause a greater performance loss for pipelines than do data hazards
A control hazard occurs when we need to find the destination of a branch, and can’t fetch any new instructions until we know that destination
© Hill, Shen, Lipasti51
Example (Example (quicksortquicksort/MIPS)/MIPS)# for (; (j < high) && (array[j] < array[low]) ; ++j );# $10 = j# $9 = high# $6 = array# $8 = low
bge done, $10, $9mul $15, $10, 4addu $24, $6, $15lw $25, 0($24)mul $13, $8, 4addu $14, $6, $13lw $15, 0($14)bge done, $25, $15
cont:addu $10, $10, 1. . .
done:addu $11, $11, -1
© Hill, Shen, Lipasti52
Control Hazard on BranchesControl Hazard on BranchesThree Stage StallThree Stage Stall
Control Hazards
10: beq r1,r3,36
14: and r2,r3,r5
18: or r6,r1,r7
22: add r8,r1,r9
36: xor r10,r1,r11
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
Reg ALU DMemIfetch Reg
© Hill, Shen, Lipasti53
Branch Stall ImpactBranch Stall ImpactIf CPI = 1, 30% branch, Stall 3 cycles => new CPI = 1.9!
(Whoa! How did we get that 1.9???)Two part solution to this dramatic increase:
– Determine branch taken or not sooner, AND– Compute taken branch address earlier
MIPS branch tests if register = 0 or ^ 0
MIPS Solution:– Move Zero test to ID/RF stage– Adder to calculate new PC in ID/RF stage
must be fast can't afford to subtract compares with 0 are simple Greater-than, Less-than test sign-bit, but not-equal must OR all bits more general compares need ALU
– 1 clock cycle penalty for branch versus 3
In the next chapter, we’ll look at ways to avoid the branch all together.
Control Hazards
© Hill, Shen, Lipasti54
Five Branch Hazard Five Branch Hazard AlternativesAlternatives
#1: Stall until branch direction is clear
#2: Predict Branch Not Taken– Execute successor instructions in sequence– “Squash” instructions in pipeline if branch actually taken– Advantage of late pipeline state update– 47% MIPS branches not taken on average– PC+4 already calculated, so use it to get next instruction
#3: Predict Branch Taken– 53% MIPS branches taken on average– But haven’t calculated branch target address in MIPS
MIPS still incurs 1 cycle branch penaltyOther machines: branch target known before outcome
Control Hazards
© Hill, Shen, Lipasti55
Control DependenceControl DependenceOne instruction affects which executes next– sw $4, 0($5)– bne $2, $3, loop– sub $6, $7, $8
WMXDFbneWMXDFsub
WMXDFsw
13
12
11
10
987654321Cycle:Instr:
© Hill, Shen, Lipasti56
Control Dependence Control Dependence -- StallStallDetect dependence and stall– sw $4, 0($5)– bne $2, $3, loop– sub $6, $7, $8
WMXDFbneWMXDFsub
WMXDFsw
13
12
11
10
987654321Cycle:Instr:
2-cycle bubble
© Hill, Shen, Lipasti57
Predict not takenPredict not takenDetect dependence and stall– sw $4, 0($5)– bne $2, $3, loop– sub $6, $7, $8
WMXDFbneWMXDFsub
WMXDFsw
13
12
11
10
987654321Cycle:Instr:
If loop is not taken
© Hill, Shen, Lipasti58
Control Dependence Control Dependence -- StallStallDetect dependence and stall– sw $4, 0($5)– bne $2, $3, loop– sub $6, $7, $8
WMXDFbneWMXDF--mul
WMXDFsw
13
12
11
10
987654321Cycle:Instr:
If loop is taken
SUB is flushed from the pipeline
© Hill, Shen, Lipasti59
Control Dependence Control Dependence -- StallStallDetect dependence and stall– sw $4, 0($5)– bne $2, $3, loop– sub $6, $7, $8
WMXDFbneWMXDFmul
WMXDFsw
13
12
11
10
987654321Cycle:Instr:
If loop is taken
2-cycle bubble
© Hill, Shen, Lipasti60
#4: Execute Both Paths
#5: Delayed Branch– Define branch to take place AFTER a following instruction
branch instructionsequential successor1sequential successor2........sequential successorn
branch target if taken
– 1 slot delay allows proper decision and branch target address in 5 stage pipeline
– MIPS uses this
Branch delay of length n
Control Hazards Five Branch Hazard Alternatives
© Hill, Shen, Lipasti61
Delayed BranchDelayed Branch
Where to get instructions to fill branch delay slot?– Before branch instruction– From the target address: only valuable when branch taken– From fall through: only valuable when branch not taken– Cancelling branches allow more slots to be filled
Compiler effectiveness for single branch delay slot:– Fills about 60% of branch delay slots– About 80% of instructions executed in branch delay slots useful in
computation– About 50% (60% x 80%) of slots usefully filled
Delayed Branch downside: 7-8 stage pipelines, multiple instructions issued per clock (superscalar)
Control Hazards
© Hill, Shen, Lipasti62
Evaluating Branch Evaluating Branch AlternativesAlternatives
Scheduling Branch CPI speedup v. Speedup v.scheme penalty unpipelined stall
Stall pipeline 3 1.42 3.5 1.0Predict taken 1 1.14 4.4 1.26Predict not taken 1 1.09 4.5 1.29Delayed branch 0.5 1.07 4.6 1.31
Conditional & Unconditional = 14%, 65% change PC
Control Hazards
Pipeline speedup = Pipeline depth1 +Branch frequency ×Branch penalty
© Hill, Shen, Lipasti63
Pipelining Introduction Pipelining Introduction SummarySummary
Just overlap tasks, and easy if tasks are independentSpeed Up Š Pipeline Depth; if ideal CPI is 1, then:
Hazards limit performance on computers:– Structural: need more HW resources– Data (RAW,WAR,WAW): need forwarding, compiler scheduling– Control: delayed branch, prediction
Speedup =Pipeline Depth
1 + Pipeline stall CPIX
Clock Cycle Unpipelined
Clock Cycle Pipelined
Control Hazards
© Hill, Shen, Lipasti64
Compiler Compiler ““StaticStatic””Prediction ofPrediction ofTaken/Untaken BranchesTaken/Untaken Branches
Freq
uenc
y of
Mis
pred
ictio
n
0%
10%
20%
30%
40%
50%
60%
70%
alvi
nn
com
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Mis
pred
ictio
n R
ate
0%
2%
4%
6%
8%
10%
12%
14%
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Always taken Taken backwardsNot Taken Forwards
Control HazardsThe compiler can program what it thinks the branch direction will be. Here are the results when it does so.
© Hill, Shen, Lipasti65
Compiler Compiler ““StaticStatic”” Prediction Prediction ofofTaken/Untaken BranchesTaken/Untaken Branches
Improves strategy for placing instructions in delay slot
Two strategies– Backward branch predict taken, forward branch not taken– Profile-based prediction: record branch behavior, predict branch based on
prior run
Control Hazards
© Hill, Shen, Lipasti66
Evaluating Static Branch Evaluating Static Branch Prediction StrategiesPrediction Strategies
Misprediction ignores frequency of branch“Instructions between mispredicted branches” is a better metric
Inst
ruct
ions
per
mis
pred
icte
d br
anch
1
10
100
1000
10000
100000
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Profile-based Direction-based
Control Hazards
© Hill, Shen, Lipasti67
Resolution of Pipeline HazardsResolution of Pipeline Hazards
Pipeline hazards– Potential violations of program dependences– Must ensure program dependences are not violated
Hazard resolution– Static: compiler/programmer guarantees correctness– Dynamic: hardware performs checks at runtime
Pipeline interlock– Hardware mechanism for dynamic hazard resolution– Must detect and enforce dependences at runtime
© Hill, Shen, Lipasti68
Pipelined Pipelined DatapathDatapath -- SummarySummary
Instruction flow– add and load– Write of registers– Pass register specifiers
Any info needed by a later stage gets passed down the pipeline– e.g. store value through EX
© Hill, Shen, Lipasti69
Pipelined Pipelined ControlControl
Control– Set by 5 different instructions– Divide and conquer: carry IR down the pipe
MIPS ISA requires the appearance of sequential execution– True of most general purpose ISAs
© Hill, Shen, Lipasti70
Pipelined ControlPipelined Control
IF and ID– None
EX– ALUop, ALUsrc, RegDst
MEM– Branch, MemRead, MemWrite
WB– MemtoReg, RegWrite
© Hill, Shen, Lipasti71
PC
Instruction�memory
Address
Inst
ruct
ion
Instruction�[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction�[15– 0]
0
0Registers
Write�register
Write�data
Read�data 1
Read�data 2
Read�register 1
Read�register 2
Sign�extend
M�u�x
1Write�data
Read�data M�
u�x
1
ALU�control
RegWrite
MemRead
Instruction�[15– 11]
6
IF/ID ID/EX EX/MEM MEM/WB
MemWrite
Address
Data�memory
PCSrc
Zero
Add Add�result
Shift�left 2
ALU�result
ALUZero
Add
0
1
M�u�x
0
1
M�u�x
© Hill, Shen, Lipasti72
Figure 6.29Figure 6.29
Control
EX
M
WB
M
WB
WB
IF/ID ID/EX EX/MEM MEM/WB
Instruction
© Hill, Shen, Lipasti73
Figure 6.30Figure 6.30
PC
Instruction�memory
Inst
ruct
ion
Add
Instruction�[20– 16]
Mem
toR
eg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction�[15– 0]
0
0
M�u�x
0
1
Add Add�result
RegistersWrite�register
Write�data
Read�data 1
Read�data 2
Read�register 1
Read�register 2
Sign�extend
M�u�x
1
ALU�result
Zero
Write�data
Read�data
M�u�x
1
ALU�control
Shift�left 2
Reg
Writ
e
MemRead
Control
ALU
Instruction�[15– 11]
6
EX
M
WB
M
WB
WBIF/ID
PCSrc
ID/EX
EX/MEM
MEM/WB
M�u�x
0
1
Mem
Writ
e
AddressData�
memory
Address
© Hill, Shen, Lipasti74
Pipelined ControlPipelined Control
Controlled by different instructionsDecode instructions and pass the signals down the pipeControl sequencing is embedded in the pipeline
© Hill, Shen, Lipasti75
PipeliningPipelining
Not too complex yet– Data hazards– Control hazards– Exceptions
© Hill, Shen, Lipasti76
Data HazardsData HazardsMust first detect hazards
ID/EX.WriteRegister = IF/ID.ReadRegister1
ID/EX.WriteRegister = IF/ID.ReadRegister2
EX/MEM.WriteRegister = IF/ID.ReadRegister1
EX/MEM.WriteRegister = IF/ID.ReadRegister2
MEM/WB.WriteRegister = IF/ID.ReadRegister1
MEM/WB.WriteRegister = IF/ID.ReadRegister2
© Hill, Shen, Lipasti77
Data HazardsData Hazards
Not all hazards because– WriteRegister not used (e.g. sw)– ReadRegister not used (e.g. addi, jump)– Do something only if necessary
© Hill, Shen, Lipasti78
Data HazardsData Hazards
Hazard Detection Unit– Several 5-bit (or 6-bit) comparators
Response? Stall pipeline– Instructions in IF and ID stay– IF/ID pipeline latch not updated– Send ‘nop’ down pipeline (called a bubble)– PCWrite, IF/IDWrite, and nop mux
dest src1 src2opcode
dest src1 src2opcode
C C
…
…
I1
I2
© Hill, Shen, Lipasti79
Data HazardsData Hazards
Detecting dependencies over memory locations– In a typical datapath, actual writes to the main
memory are serialized via write buffers
Write Buffers (FIFO)
Address Data to be written
Data fromCache
Writes to the Main Memory
© Hill, Shen, Lipasti80
Data HazardsData Hazards
Detecting dependencies over memory locations– When the effective address of a LOAD is
computed, it is compared with the effective addresses of all the writes in the Write Buffers
Write Buffers (FIFO)
Address Data to be written
Data fromCache
Writes to the Main Memory
The Effective Address of the LOAD
C
C
C
C
Wider Comparators(typically 32 bit)
© Hill, Shen, Lipasti81
Data HazardsData Hazards
A better response – forwarding– Also called bypassing
Comparators ensure register is read after it is writtenInstead of stalling until write occurs– Use mux to select forwarded value rather than
register value– Control mux with hazard detection logic
© Hill, Shen, Lipasti82
Write before Read RFWrite before Read RF
Register file design– 2-phase clocks common– Write RF on first phase– Read RF on second phase
Hence, same cycle:– Write $1– Read $1
No bypass needed– If read before write or DFF-based, need bypass
© Hill, Shen, Lipasti83
Control Flow HazardsControl Flow Hazards
Control flow instructions– branches, jumps, jals, returns– Can’t fetch until branch outcome known– Too late for next IF
© Hill, Shen, Lipasti84
Control Flow HazardsControl Flow Hazards
What to do?– Always stall– Easy to implement– Performs poorly– 1/6th instructions are branches, each branch
takes 3 cycles– CPI = 1 + 3 x 1/6 = 1.5 (lower bound)
© Hill, Shen, Lipasti85
Control Flow HazardsControl Flow Hazards
Predict branch not takenSend sequential instructions down pipelineKill instructions later if incorrectMust stop memory accesses and RF writes– Including loads (why?)
Late flush of instructions on misprediction– Complex– Global signal (wire delay)
© Hill, Shen, Lipasti86
Control Flow HazardsControl Flow Hazards
Even better but more complex– Predict taken– Predict both (eager execution)– Predict one or the other dynamically
Adapt to program branch patternsLots of chip real estate these days
– Pentium III, IV, Alpha 21264
Current research topic
© Hill, Shen, Lipasti87
Control Flow HazardsControl Flow Hazards
Another option: delayed branches (later in branch handling techniques!)– Always execute following instruction– “delay slot”– Put useful instruction there, otherwise ‘nop’
Losing popularity– Just a stopgap (one cycle, one instruction)– Superscalar processors (later)
Delay slot just gets in the way (special case)
© Hill, Shen, Lipasti88
Exceptions and PipeliningExceptions and Pipelining
add $1, $2, $3 overflowsA surprise branch– Earlier instructions flow to completion– Kill later instructions– Save PC in EPC, set PC to EX handler, etc.
© Hill, Shen, Lipasti89
ExceptionsExceptions
Even worse: in one cycle– I/O interrupt– User trap to OS (EX)– Illegal instruction (ID)– Arithmetic overflow– Hardware error– Etc.
Interrupt priorities must be supported
© Hill, Shen, Lipasti90
ReviewReview
Big PictureDatapathControl– Data hazards
StallsForwarding or bypassing
– Control flow hazardsBranch prediction
Exceptions
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