Let’s look at a normal lw instruction first…

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Let’s look at a normal lw instruction first…. address 1000 10 : lw $6,8($7) $6  Memory[8 + contents of $7]. PC value: 1000 10. address 1000 10 : lw $6,8($7) $6  Memory[8 + contents of $7]. PC value: 1000 10. This sequence of 1s and 0s. address 1000 10 : lw $6,8($7). - PowerPoint PPT Presentation

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1

Let’s look at a normal lw instruction first…

2

Register fileaddress content6 (00110) 910

7 (00111) 1000010

Opcode Source register

Destination register

Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)$6 Memory[8 + contents of $7]

PC value: 100010

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

3

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100010

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

This sequence of 1s and 0s

Opcode Source register

Destination register

Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)$6 Memory[8 + contents of $7]

4

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100010100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 1, State 0: Fetch load instruction

IR Memory(PC) || PC PC + 4

IR contains: 100011-00111-00110-0000000000001000

001

See control logic discussion00

5

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 2, State 1: Decode instructionA RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0])

00111

1000010

Load 1000010 into A register

6

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 2, State 1: Decode instructionA RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0])

00110

910

Load 910 into B register

7

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 2, State 1: Decode instructionA RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0])

Calculate address in case it is needed.(hardware is available, so use ASAP)

8

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 2, State 1: Decode instructionA RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0])

011

See control logic discussion

9

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 3, State 2 Calculate address

ALUOut A + SignExt(IR[15:0])

1000010

• ‘A’ register is: 1000010

• Immediate value is: 810 (0000 0000 0000 10002)• Immediate value is padded with leading 0s to get 2nd 32-bit number

0000 0000 0000 0000 0000 0000 0000 10002

810

10

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)

110

See control logic discussion

Cycle 3, State 2: Calculate addressALUOut A + SignExt(IR[15:0])

1000010

810

1000810

ALUOut contains address to send to memory

11

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 4, State 3: Get data from memory

MDR Memory[ALUOut]

• Address 1000810 sent to memory• Want to load 7010 into Memory Data Register

1000810

1000810

Data from memory is 7010

12

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 4, State 3: Get data from memory

MDR Memory[ALUOut]

1

Choose ALUOut to

get memory address

Put 7010 in MDR

13

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 5, State 4: Write data from memory to the register file

RF[IR(20:16)] MDR

7010

00110

14

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 5, State 4: Write data from memory to the register file

RF[IR(20:16)] MDR

0

1

610

610

7010

7010

15

Register fileaddress content6 (00110) 910 7010

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw $6,8($7)Cycle 5, State 4: Write data from memory to the register file

RF[IR(20:16)] MDR

0

1

610

610

7010

7010

16

Now, let’s revisit lw++

17

Recall…• lw++ would do the following…

– lw++ $6, 8($7)• $6 Memory[8 + content of $7] ||• $7 $7 + 4

• Why is this useful?– Assume we wanted to iterate through an array … we

might use the following sequence of instructions:• lw $t, 0($x)• addi $x, $x, 4

– The above 2 instruction sequence (requiring 9 CCs) could be replaced by a single instruction that takes 5 or 6 CCs

• Now, let’s talk about the hardware to make lw++ work!

18

Register fileaddress content6 (00110) 910

7 (00111) 1000010

Opcode Source register

Destination register

Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

111111 00111 00110 0000 0000 0000 1000

address 100010: lw++ $6,8($7)$6 Memory[8 + contents of $7]$7 $7 + 4

PC value: 100010

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode must change!(Assume 111111 is available.)

19

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100010

This sequence of 1s and 0s

Opcode Source register

Destination register

Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

111111 00111 00110 0000 0000 0000 1000

address 100010: lw++ $6,8($7)$6 Memory[8 + contents of $7]$7 $7 + 4

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

20

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100010100410

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw++ $6,8($7)Cycle 1, State 0: Fetch load instruction

IR Memory(PC) || PC PC + 4

IR contains: 111111-00111-00110-0000000000001000

001

See control logic discussion00

Same as normal lw

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

21

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw++ $6,8($7)Cycle 2, State 1: Decode instructionA RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0])

00111

1000010

Load 1000010 into A register

Same as normal lw

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

22

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw++ $6,8($7)Cycle 2, State 1: Decode instructionA RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0])

00110

910

Load 910 into B register

Same as normal lw

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

23

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw++ $6,8($7)Cycle 2, State 1: Decode instructionA RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0])

Calculate address in case it is needed.(hardware is available, so use ASAP)

Same as normal lw

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

24

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

address 100010: lw++ $6,8($7)Cycle 3, State 2 Calculate address

ALUOut A + SignExt(IR[15:0])

1000010

• A register is: 1000010

• Immediate value is: 810 (0000 0000 0000 10002)• Immediate value is padded with leading 0s to get 2nd 32-bit number

0000 0000 0000 0000 0000 0000 0000 10002

810

1000810

Same as normal lw

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

25

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

Cycle 4, State 3: Get data from memoryMDR Memory[ALUOut]

• Address 1000810 sent to memory• Want to load 7010 into Memory Data Register

1000810

1000810

Data from memory is 7010

address 100010: lw++ $6,8($7) Part 1:Same as normal lw

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

26

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

Cycle 4, State 3: Get data from memoryMDR Memory[ALUOut] || ALUOut [A] + 4

address 100010: lw++ $6,8($7)

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

Part 2:NEW!

1000010

810

Content of A and B registers still has not changed

Idea:Use idle ALU to update the value in register A (i.e. $7) while the memory access occurs.

27

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

Cycle 4, State 3: Get data from memoryMDR Memory[ALUOut] || ALUOut [A] + 4

address 100010: lw++ $6,8($7)

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

Part 2:NEW!

To make this work, need to assert other control signals in State 3 to do an add operation:• ALUSrcA = 1 # select A input• ALUSrcB = 01 # select 4 input• ALUOp = 00 # perform add

MemReadIorD = 1

ALUSrcA = 1ALUSrcB = 01ALUOp = 00

3

New state would look like…

28

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

Cycle 4, State 3: Get data from memoryMDR Memory[ALUOut] || ALUOut [A] + 4

address 100010: lw++ $6,8($7)

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

Part 2:NEW!

1

1000010

See control logic discussion

do add

01

1000410

ALUOut contains 1000410

29

Now, to finish, we need to support the write back of both the MDR

register AND the ALUOut register

For dramatic effect, let’s continue on another slide…

30

Option A:Write back MDR and ALUOut in

the same CC…

31

Register fileaddress content6 (00110) 910

7 (00111) 1000010

PC value: 100410

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

Cycle 5, State 12: Write data back…RF[IR(20-16)] MDR || RF[IR(25:21)] ALUOut

address 100010: lw++ $6,8($7)

Memoryaddress content100010 lw++ encoding

… …

1000010 5010

1000410 6010

1000810 7010

Option A

Aw, snap!With existing datapath, only 1 register can be written at a time…

32

Option A:Write back MDR and ALUOut in

the same CC… Solution:• Add register file hardware• Update the FSM

Let’s update the register file hardware 1st…

33

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

Cycle 5, State 12: Write data back…RF[IR(20-16)] MDR || RF[IR(25:21)] ALUOut

address 100010: lw++ $6,8($7) Option A

Can keep existing hardware the same, but need to add:

• Another address port• “Write register 2”

• Another data port• “Write data 2”

• Another control signal• RegWrite2

IR(25:21) – i.e. 001112

Input toWrite Register 2

ALUOut(1000410)

Input toWrite Data 2

New control signal:RegWrite2

34

New FSM diagram is thus:

RegDst = 0RegWrite

MemtoReg = 1

RegWrite2

12

lw++

Need a new state because we want to do different things for lw and lw ++

35

Option B:Write back MDR and ALUOut in

the different CCs…

36

Register fileaddress content6 (00110) 910 7010

7 (00111) 1000010

PC value: 100410

Memoryaddress content100010 lw encoding

… …

1000010 5010

1000410 6010

1000810 7010

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

Cycle 5, State 4: Write data from memory to the register fileRF[IR(20:16)] MDR

0

1

610

610

7010

7010

address 100010: lw++ $6,8($7)

Same as normal lw

37

Opcode Source Destination Immediate value

Bits 31-26 Bits 25-21 Bits 20-16 Bits 15-0

100011 00111 00110 0000 0000 0000 1000

Cycle 5, State 13: Write data from ALUOut to the register fileRF[IR(25:21)] ALUOut

address 100010: lw++ $6,8($7)

Aw, snap!No path for bits 25:21 of IR to use as write address…

To fix:• Add another input to mux• Now need 2 control

signals instead of 1

00

01

10

IR(20:16)

IR(15:11)

IR(25:21)

38

New FSM diagram is thus:

RegDst = 10RegWrite

MemtoReg = 0

13

lw++

Notes:• RegDst = 10

• Selects IR(25:21)• RegWrite

• Enables register file to be written

• MemtoReg = 0• Selects ALUOut as

input to the register file

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