Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT

Logic Synthesis for

Asynchronous Circuits Based

on Petri Net Unfoldings and

Incremental SAT

Victor Khomenko, Maciej Koutny,

and Alex Yakovlev

University of Newcastle upon Tyne

2

Talk Outline

• Introduction Asynchronous circuits Logic synthesis based on state graphs State graphs vs. net unfoldings

• Logic synthesis based on net unfoldings

• Experimental results

• Future work

3

Asynchronous CircuitsAsynchronous circuits – no clocks: Low power consumption Average-case rather than worst-case

performance Low electro-magnetic emission Modularity – no problems

with the clock skew

Hard to synthesize The theory is not sufficiently developed Limited tool support

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Example: VME Bus Controller

lds-d- ldtack- ldtack+

dsr- dtack+ d+

dtack- dsr+ lds+

DeviceVME Bus

Controller

lds

ldtack

d

Data Transceiver

Bus

dsrdtack

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Example: CSC Conflict

dtack- dsr+

dtack- dsr+

dtack- dsr+

00100

ldtack- ldtack- ldtack-

0000010000

lds- lds- lds-

01100 01000 11000

lds+

ldtack+

d+

dtack+dsr-d-

01110 01010 11010

01111 11111 11011

11010

10010

M’’ M’

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Example: Enforcing CSC

dtack- dsr+

dtack- dsr+

dtack- dsr+

001000

ldtack- ldtack- ldtack-

000000 100000

lds- lds- lds-

011000 010000 110000

lds+

ldtack+

d+

dtack+dsr-

d-

011100 010100 110100

011111 111111 110111

110101

100101

011110

csc+

csc-

100001

M’’ M’

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Example: Deriving EquationsCode Nxtdtack Nxtlds Nxtd Nxtcsc001000000000100000100001011000010000110000100101011100010100110100110101011110011111111111110111

0000000000001111

0001000100011111

0000000000010111

0011000100010011

Eqn d d csc csc ldtack dsr(ldtackcsc)

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Example: Resulting Circuit

Device

d

Data TransceiverBus

dsr

dtacklds

ldtack

csc

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State Graphs:

Relatively easy theory Many efficient algorithms

Not visual State space explosion problem

State Graphs vs. Unfoldings

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State Graphs vs. UnfoldingsUnfoldings:

Alleviate the state space explosion problem More visual than state graphs Proven efficient for model checking

Quite complicated theory Not sufficiently investigated Relatively few algorithms

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Complex-gate synthesis

State Graphs vs. Unfoldings

SG Unf

Checking consistency

Checking semi-modularity

Deadlock detection

Checking CSC

Enforcing CSC

Deriving equations

Technology mapping

DATE’03

ACSD’04

DATE’02 &ACSD’03

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Synthesis using unfoldingsOutline of the algorithm:

for each output signal z

compute (minimal) supports of z

for each ‘promising’ support X

compute the projection of the set of reachable encodings onto X

sorting them according to the corresponding values of Nxtz

apply Boolean minimization to the obtained ON- and OFF-sets

choose the best implementation of z

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CSCz property

• The CSC property: the next-state function of every output signal is a well-defined Boolean function of encoding of current state, i.e., all the signals can be used in its support

• The CSCz property: Nxtz is a well-defined Boolean function of encoding of current state; again, all the signals can be used in its support

• The CSCz property: Nxtz is a well-defined Boolean function of projection of the encoding of the current state on set of signals X; i.e., X is a support

X

X

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CSCz conflicts

• States M’ and M’’ are in CSCz conflict if

Codex(M’)=Codex(M’’) for all xX, and

Nxtz(M’) Nxtz(M’’)

• Nxtz can be expressed as a Boolean function

with support X iff there are no CSCz conflicts

X

X

X

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Example: CSCz conflictXdtack- dsr+

dtack- dsr+

dtack- dsr+

001000

ldtack- ldtack- ldtack-

000000 100000

lds- lds- lds-

011000 010000 110000

lds+

ldtack+

d+

dtack+dsr-

d-

011100 010100 110100

011111 111111 110111

110101

100101

011110

csc+

csc-

100001

Nxtcsc (M’)=1

Nxtcsc (M’’)=0

M’’

M’

X={dsr, ldtack}

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Example: CSCz conflict in unfolding

lds-

d-

ldtack-

ldtack+ dsr-dtack+d+

dtack-

dsr+ lds+ csc+

dsr+e1 e2 e3 e4 e5 e6 e7 e9

e11

e14e10e8

X

dsr ldtack dtack lds dcsc

Code(C’) 1 1 0 1 0 1

Code(C’’) 1 1 0 0 0 0

csc+ csc-

e12

e13

Nxtcsc = dsr (ldtack csc)

X

Nxtcsc (C’)=1Nxtcsc (C’’)=0

C’ C’’

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Computing supports

• Using unfoldings, it is possible to construct a Boolean formula CSCz(X,…) such that CSCz(X,…)[Y/X] is satisfiable iff Y is not a support

• The projection of the set of satisfying assignments of CSCz(X,…) onto X is the set of all non-supports of z (it is sufficient to compute the maximal elements of this projection)

• The set of supports can then be computed as

{ Y | YX, for all maximal non-supports X }

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Outline of the algorithmfor each output signal z

compute (minimal) supports of z

for each ‘promising’ support X

compute the projection of the set of reachable encodings onto X

sorting them according to the corresponding values of Nxtz

apply Boolean minimization to the obtained ON- and OFF-sets

choose the best implementation of z

Need to know how to compute projections!

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Example: projections

=(a b)(a b)(c d e)a b c d e0 1 0 0 10 1 0 1 00 1 0 1 10 1 1 0 00 1 1 0 10 1 1 1 00 1 1 1 11 0 0 0 11 0 0 1 01 0 0 1 11 0 1 0 01 0 1 0 11 0 1 1 01 0 1 1 1

a b

Proj{a,b,c}

a b c0 1 00 1 11 0 01 0 1

max Proj{a,b,c}

a b c0 1 11 0 1

min Proj{a,b,c}

a b c0 1 01 0 0

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Computing projections

0 1 0 0 1

Proj{a,b,c} a b c d e

0 1 1 0 0

1 0 0 0 1

1 0 1 0 0UNSAT

(abc) (abc) (abc) (abc)

a b

=(ab)(ab)(cde)

• Incremental SAT

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Optimizations

Triggers belong to every support –

significantly improves the efficiency

Further optimizations are possible for

certain net subclasses, e.g. unique-choice

nets

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Experimental Results

• Unfoldings of STGs are almost always small in practice and thus well-suited for synthesis

• Huge memory savings• Dramatic speedups• Every valid speed-independent solution can be

obtained using this method, so no loss of quality

• We can trade off quality for speed (e.g. consider only minimal supports): in our experiments, the solutions are the same as Petrify’s (up to Boolean minimization)

• Multiple implementations produced

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Future Work

SG Unf

Checking consistency

Checking semi-modularity

Deadlock detection

Checking CSC

Enforcing CSC

Deriving equations

Technology mapping

Timing assumptions?

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Thank you!Any questions?