View
32
Download
1
Category
Tags:
Preview:
DESCRIPTION
METU EE413 FINAL REPORT
Citation preview
EE 413 TERM PROJECT Simple Serial Peripheral Configuration Interface (SSPCI) Design
2013-01-30 EREN AYDIN 1740588
2
TABLE OF CONTENTS INTRODUCTION............................................................................................................................. 3
1. THEORITICAL BACKGROUND ................................................................................................... 3
1.1. What is Serial Communication......................................................................................... 3
1.2. SPI (Serial Peripheral Interface Bus) ................................................................................. 3
1.3. SCI (Universal asynchronous receiver/transmitter) (UART)................................................ 4
1.4. I2C (Inter Integrated Circuits)........................................................................................... 5
2. DESIGN PROCEDURE .............................................................................................................. 6
2.1. Conceptual Design.......................................................................................................... 6
2.2. Subblock Design ............................................................................................................. 7
2.2.1 SIPO Shift Register ......................................................................................................... 7
2.2.2 Shadow Register ............................................................................................................ 8
2.2.3 Decoder ........................................................................................................................ 9
2.2.4 Data Storage ............................................................................................................... 16
2.2.5. PISO Shift Register ...................................................................................................... 23
2.3 Design of Full System ......................................................................................................... 24
3. TESTING PROCEDURE OF DIGITAL INTEGRATED CIRCUITS ....................................................... 25
4. CONCLUSUON ..................................................................................................................... 29
3
INTRODUCTION Serial Communication is the most practical way of transferring data from one IC to another
IC. Thousands of bits data can be transferred using just three wires thanks to serial
communication. In this project, we were supposed to design a serial peripheral configuration
interface. There are different types of serial communication protocols used. In this project a
different serial communication is described and we designed our modules according to this
new protocol.
In this report first of all brief information about serial communication and serial
communication protocols are mentioned. Then assigned serial communication will be
explained and after this design procedure will be told in detail. All implemented systems and
overall systems will be mentioned and how overall system was tested will be mentioned in
detail. Finally a brief conclusion will be done.
1. THEORITICAL BACKGROUND
1.1. What is Serial Communication
Serial communication is defined as process of sending data one bit at a time (clock cycle),
sequentially over a communication channel or a computer bus. It differs from parallel
communication with sending one bit data at a time. In parallel communication lots of bits
(equal to number of data pins) can be sent at a time, so parallel communication is much faster
than serial communication. In spite of speed of parallel communication, it is not preferred too
much since it needs lots of pins. Increasing pin number causes price of communication. That
is why serial communication is used instead of parallel communications in lots of field. There
are different ways of serial communications and there are lots of serial communication
protocols. According to application correct serial communication protocol can be used.
1.2. SPI (Serial Peripheral Interface Bus)
It is a protocol defined by Motorola. That is a system operating in full duplex mode (two
device can send data to each other at same time). Devices communicate at master/slave mode
where master initiate and stop communication. In a communication line one master and at
least one slave device is included. In SPI protocol there are four wires named SCLK (Serial
Clock), MOSI (Master Output Serial Input), MISO (Master Input Parallel Output) and SS
(Slave Select).
Figure 1: SPI Data Directions
Increasing slave number causes increment in SS pin number.
Typical SPI hardware is implemented in Figure 2.
4
Figure 2: SPI Hardware
In SPI protocol there is no need unique addresses. SS pin activate the slave and bidirectional
dataflow starts. Master starts when data flow will stop. End of data flowing transferred data is
used (stored or processed). It is an extremely simple serial data interface but dataflow is not
controlled, no handshake and no error checking. It works properly in small distances and due
to its simplicity it is used in various applications.
1.3. SCI (Universal asynchronous receiver/transmitter) (UART) UART is a piece of computer hardware that translates data between parallel and serial forms.
It is widely used with different communication protocols such as RS-232, RS-422 or RS-485.
In UART data transmission speed and data format are configurable. A UART is usually an
individual integrated circuit used for serial communication over a computer or peripheral
device serial port. Moreover most microcontrollers include UART. In UART half duplex or
full duplex modes are available. Furthermore UART is much more reliable than SPI since it
has start/stop bits and parity bits. The bit rate of serial port is named as baud rate and there are
different specific baud rates for UART. Baud rate can be configured. It should be same for
receiver and transmitter devices. Start bit indicates communication is started and stop bit
indicates communication is ended. Parity bits are added optionally to detect errors.
Figure 3: UART bit configuration
One byte data is sent at one cycle (between start and stop bits.)
5
Figure 4: Data transmission at UART
Data is taken by transmitter and start, stop and parity bits are added and sent to
receiver. Receiver removes start, stop and parity bits and takes only data part. Full block
diagram of UART is given in Figure 5.
Figure 5: UART block diagram
1.4. I2C (Inter Integrated Circuits)
I2C is a multimaster serial single-ended computer bus invented by Philips. It is a two wire
serial communication protocol (SCL and SDA).
Figure 6: Wire configuration in I2C
SCL is the clock and SDA is data to be sent or received. Using SDA line mode of operation,
slave address and data is determined. For example if data is going to be read by the master
device, first of all read command is sent then address information is sent and then the slave at
desired address is enabled. After enabling the desired slave read command is sent and data
flow begins. In every one byte an acknowledge bit is sent to confirm data flow is successful.
I2C protocol is used widely especially in microcontrollers or embedded systems.
1.5. SSPCI
6
It is a unique protocol designed for EE413 project. It is a 4-wire serial communication
scheme.
Figure 7: SSPCI Block Diagram
sdata is 24 bit serial data. First 16 bit of the sdata input is the data input, 7 bit of the remaining
byte is address in data storage and the last bit is R/W command. If Read mode is active first
16 bit will be ignored. If Write mode is active the data is written to data storage.
2. DESIGN PROCEDURE The design procedure of the project is basically in three steps: Conceptual design, design of
subblocks and design of full system.
2.1. Conceptual Design
First of all all specifications and requirements are analyzed and a block diagram including
subsystems is drawn.
7
Figure 8: Block Diagram of SSPCI
After designing block diagrams architectures of subblocks are determined and designed.
2.2. Subblock Design
2.2.1 SIPO Shift Register
SIPO Shift register converts serial input to parallel output. It is designed connecting 24 D flip
flops cascaded.
Figure 9: Schematic of SIPO shift register
Figure 10: Layout of SIPO shift register
Figure 11: Extracted View of SIPO shift register
It is connected to Shadow register. Therefore output of the SIPO shift register is directly fits
to input of Shadow Register.
8
2.2.2 Shadow Register
Shadow register is a parallel to parallel register. It is used to store data instantaneously it
takes the data in input register at negative edge of “senb” signal and holds data until another
data is written on it. It sends data to the other subblocks. Since it is used, taking another data
is possible while internal writing/reading processes continue. Therefore dataflow becomes
faster and more reliable. Data loss is prevented thanks to shadow register.
Figure 12: Schematic of Shadow Register
Figure 13: Layout of Shadow Register
Figure 14: Extracted View of Shadow Register
9
2.2.3 Decoder
To design a 7x128 decoder hierarchy is used. First of all 1x2 decoder is designed and then it is
made bigger and finally 7x128 decoder is designed. Although this configuration seems easy,
regular layout could not been drawn. However due to lack of time I could not fix the
configuration.
Figure 15: 1x2 Decoder schematic
Figure 16: 1x2 decoder layout
10
Figure 17: 1x2 decoder extracted view
Figure18: Schematic of 2x4 decoder
11
Figure 17: Layout and extracted view of 2x4 decoder
Figure 20: Schematic of 4x16 decoder
12
Figure 21: Layout and extracted view of 4x16 decoder
Figure 22: Schematic of 6x64 decoder
13
Figure 23: Layout and extracted view of 6x64 decoder
14
Figure 24: Schematic of 7x128 decoder
15
Figure 24: Layout and extracted view of 7x128 decoder
16
2.2.4 Data Storage
Data storage is designed using hierarchy. First of all one bit data storage cell is designed and
then it is made bigger and bigger.
Figure 25: 1 bit data storage cell
Figure 26: 1 bit data storage cell
17
Figure 27: Extracted view of 1 bit data storage
Figure 28: Schematic of 16 bit data storage
Figure 29: Layout of 16 bit data storage
Figure 30: Extracted view of 16 bit data storage
18
Figure 31: Schematic of 8 row 16 column data storage
19
Figure 32: Layout of 8 row 16 column data storage
Figure 33: Extracted view of 8 row 16 column data storage
20
Figure 34: Schematic of 128 row 16 column data storage
21
Figure 34: Layout of 128 row 16 column data storage
22
Figure 35: Extracted view of 128 row 16 column data storage
23
2.2.5. PISO Shift Register
I did not have time to draw layout of PISO Shift Register. I was planning to use hierarchy to
draw it.
Figure 36: 1 bit PISO Shift Register
Figure 37: 16 bit PISO Shift register
24
2.3 Design of Full System
Designed subsystems are connected together according to block diagram. Some delay
elements are put across the component to make system more stable.
Figure 38: Schematic of the whole system
25
3. TESTING PROCEDURE OF DIGITAL INTEGRATED CIRCUITS Testing digital circuits in detail is a very important step before producing it.
There are the important concepts for testability of a digital integrated circuit. First concept is
controllability. Controllability means being able to set up known internal states. Observability
is the other concept. It means being able to observe the effects of a state change. The last
concept is combinational testability. It means being able to generate all states to fully exercise
all combinations of circuit states.
To verify that circuit is working properly all input and output combinations should be tried,
however it takes very long time. In fact it is impossible after some number of input and
output.
Before processing it lots of simulations should be done. Furthermore some test points should
be added to the circuit for post processing testing.
Simulations before processing are done for verifying the functionality of the circuit. It is
controlled that the blocks are created correctly or not. After digital simulations analog
simulations are required. Furthermore some capacitive loads can be connected for simulation.
Digital integrated circuits are verified basically using three ways.
Simulation: Software-based simulation is widely used, but even when running on a
really high-end (and correspondingly expensive) computer platform, it runs six to ten
orders of magnitude slower than the actual ASIC hardware, which makes it an
extremely time consuming and inefficient technique. To provide a sense of scale,
software simulation of the entire system can typically achieve equivalent speeds of
only a few Hz (that is, a few cycles of the design's system clock for each second of
real time). In practice, this means that extensive software verification can be
performed on only small portions of the design.
Emulation: Hardware-based emulation is another alternative, but it is still at least
three orders of magnitude slower than the actual ASIC hardware, because the massive
amounts of multiplexing involved slows the verification speed down to only 500 KHz
to 2 MHz. Furthermore, this approach is extremely expensive, both in terms of budget
and resources (depending on the size of the emulator, the cost can be anywhere from
25 cents to $1 per equivalent gate). What designers need is an alternative that will
allow them to get to market quickly with low risk and at low cost.
FPGA-based Prototyping: The third method of ASIC design verification is FPGA-
based prototyping. This technique has been around for many years, but only recently
has become widely adopted.
FPGA based prototyping is becoming very popular in these days since it is fast and cheap
enough. Moreover developing technology increases capacity of FPGA boards.
26
In this project we were supposed to use Verilog-XL simulator. The code I write to simulate
our circuit is given at Table 1.
Table 1: Whole test code
// Verilog stimulus file.
// Please do not create a module in this file.
// Default verilog stimulus. integer M; //control registers, counters. The simulation code is based on this registers.
reg RW; reg[6:0] address;
reg[15:0] datain; reg[5:0] cn0;
reg[7:0] cn1;
initial //initializing registers, counters and inputs begin M = 10000000;
clk = 1'b0; RN = 1'b0; senb = 1'b0;
sin = 1'b0; RW = 1'b0; address[6:0] = 7'b0000000;
datain15:0] = 16'b1111111111111111; cn0 = 0; cn1= 0;
end
initial begin
always #100 clk = ~clk; //period of clk is 200 ps
#50 RN = 1'b1; //if RN=0 memory is resetted. end
always @(negedge clk) //senb signal is high for 24 clock cycles. begin if (cn0 >= 0 && cn0 <24) senb <= 1'b1;
else if ( cn0 >= 24 && cn0 < 41) senb <= 1'b0; else senb <= 1'b0; end
27
always @(negedge clk) begin
if (RN == 1) cn0 <= cn0 + 1; //if RN=0 simulation is trivial else if (cn0 > 40) cn0 <= 0; else cn0 <= 0; //resetting the counter
end
always @(negedge clk) //serial data transmission begin if (cn0 >= 0 && cn0 <16) sin <= datain[cn0];
if (cn0 >= 16 && cn0 <23) sin <= address[cn0-16]; if (cn0 == 23) sin <= RW; end
always @(negedge senb) begin #10 datain <= datain - 1;
#10 address <= address + 1; cn1 <= cn1+1; if (cn1 >= 127 ) //after writing the full memory Read mode is activated
begin RW <= ~RW; if (cn1 >= 256) cn1 <= 0;
end end
initial #(M) $finish; //finish the simulation
Figure 39: Simulation results of the whole system
28
Figure 40: Simulation results for 0th row
Figure 41: Simulation results for 2nd row
Figure 42: Simulation results for 47th row
When we look at the simulation results write mode of our circuit works properly, however
serial read mode is not working properly.
29
4. CONCLUSUON In this project we learned serial communication protocols briefly and designed a circuit
according to the given serial communication protocol. It was a very beneficial project. First of
all we learned serial communication protocols and serial communication which is used
everywhere. Moreover we designed some subsystems and brought them together and made
them work. It was an important engineering problem and we found some solutions for
problems occurred. Furthermore we have drawn layouts of some big circuits. We handled
DRC and LVS errors and created very successful layouts. Drawing layouts so that they can be
connected each other directly is a very important issue and we worked on it. I could not be
exactly successful but I learned that before starting drawing layout floorplaning should be
done very carefully. The distances of output and input pins should be equal each other. We
also learned using Verilog-XL simulator and writing codes for testing integrated circuits. I
could not draw layout of the whole system since I have an airplane ticket at 28 th January so I
did not have time to draw the layout of the whole system.
All in all it was a very beneficial project for the students considering developing themselves
in VLSI.
Recommended