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8/9/2019 Micro Lec Note4
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--11
I/O devices
Peripheral devices (alsocalled I/O devices)arepiecesofequipmentthatexchange data witha CPU
Examples:switches, LED, CRT,printers, keyboard,keypad
Speed and characteristicsofthese devicesareverydifferent fromthatofCPU sotheycannotbeconnected directly
Interface chipsareneeded toresolvethisproblem
Mainfunctionofaninterfacechipistosynchronizedatatransferbetween CPUand I/O device
Datapinsofinterfacechipareconnected to CPU databusand I/O portpinsareconnected to I/O device
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--22
I/O devices
SinceaCPU mayhavemultiple I/O devices, CPU databusmaybeconnected to databusesofmultipleinterface
Anaddress decoderisused toselectone deviceto
respond tothe CPU I/O request Different CPUs deal with I/O devicesdifferently
Some CPUshave dedicated instructionsforperforminginputand outputoperations (isolated I/O)
Other C
PUsusethesameinstructionforreadingfrommemoryand readingfrominput devices,as wellas
writing dataintomemoryand writing dataintooutputdevices (memory-mapped I/O)
MCS-51 (8051) is memory mapped
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--33
Synchronizationof CPUand interfacechip
Theremustbeamechanismtomakesurethattherearevalid dataintheinterfacechip when CPUreadsthem
Inputsynchronization:two waysof doingthis1. Pollingmethod
interfacechipusesastatus bit toindicateifithasvalid datafor CPU
CPU keepschecking statusbituntilitisset,and thenreads
datafrominterfacechip Simple method,used when CPUhasnothingelseto do
2. Interrupt drivenmethod:interfacechipinterruptsthe CPU whenithasnew data. CPUexecutestheISR
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--44
Synchronizationof CPUand interfacechip
Outputsynchronization:two waysof doingthis
1. Pollingmethod interfacechipusesastatus bit toindicatethatthe data
registerisempty CPU keepscheckingstatusbituntilitisset,and then writes
dataintointerfacechip
2. Interrupt drivenmethod:interfacechipinterruptsthe CPU whenit dataregisterisempty. CPUexecutes
theISR
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--55
Synchronizationof CPUand interfacechip
Methodsused tosynchronize datatransferbetweeninterfacechipand I/O devices:
1. Brute force method: interfacechipreturnsvoltagelevelsinitsinputportsto CPUand makes data writtenby CPU directly
availableon
its
output
ports All 8051portcanperformbruteforce I/O
2. Strobe method: Duringinput,the I/O deviceactivatesastrobesignal when dataare
stable. Interfacechiplatchesthe data Foroutput,interfacechipplacesoutput dataonoutputport. when
dataisstable,itactivatesastrobesignal. I/O devicelatchesthedata
3. Handshake method: twohandshakesignalsareneeded Oneisasserted byinterfacechipand theotherby I/O device
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--66
8051ports
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--77
8051ports Ports1, 2,and 3 haveinternalpullups,and Port 0
hasopen drainoutputs.
Tobeused asaninput,theportbitlatchmustcontaina1, whichturnsofftheoutput driverFET.
ForPorts1, 2,and 3,thepinispulled highbyaweak internalpullup,and canbepulled low byanexternalsource.
Port 0 differsinthatitsinternalpullupsarenotactive duringnormalportoperation (writinga1tothebitlatchleavesbothoutputFETsoff,sothepinfloats).
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--88
8051 I/O Ports: Hardware Specs
P0 isopen drain.Hastobepulled highbyexternal10K resistors.
Notneeded ifP0 isused foraddresslines
P1,P2,P3 haveinternalpull-ups
Portfan- out (numberof devicesitcandrive)islimited.Usebuffers (74LS244, 74LS245,etc)to
increase drive.
P1,P2,P3 can driveupto 4 LS-TTL inputs
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--99
8051- Switch On I/O Ports
Case-1: Givesalogic 0 onswitchclose
Currentis 0.5maonswitchclose
Case-2: Givesalogic1onswitchclose
Highcurrentonswitchclose
Case-3: Can damageportif 0 isoutput
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--1010
Simpleinput devices
DIPswitchesusuallyhave 8 switches
Usethecase-1frompreviouspage
Sequenceofinstructionstoread a
valuefromD
IPswitches:
mov P1,#FFH
mov A,P1,
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--1111
Interfacinga Keypad
A 16-key keypad isbuiltasshowninthefigurebelow. 16 keysarranged as
a 4X4 matrix.Must activate
eachrow byplacinga 0 onits R output.
Thenthecolumnoutputisread.
Ifthereisa 0 ononeofthecolumnbits,thenthebuttonatthecolumn/row
intersectionhasbeenpressed.
Otherwise,trynextrow. Repeatconstantly
C1
C2
C3
C4
R1
R2
R3
R4
0123
567
DEF
9AB
C
8
4
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--1212
Bouncing Contacts
Push-buttonswitches,toggleswitches,andelectromechanicalrelaysallhaveonethingincommon:contacts.
Metalcontactsmakeand break thecircuitandcarrythecurrentinswitchesand relays.Becausetheyaremetal,contactshavemass.
Sinceatleastoneofthecontactsismovable,ithasspringiness.
Sincecontactsare designed toopenand closequickly,thereislittleresistance (damping)totheirmovement
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--1313
Bouncing
Becausethemovingcontactshavemassandspringiness withlow dampingthey willbe "bouncy"astheymakeand break.
Thatis, whenanormallyopen (N.O.)pairof
contactsisclosed,thecontacts willcometogetherand bounceoffeachotherseveraltimesbeforefinallycomingtorestinaclosed position.
Theeffectiscalled "contactbounce" or,inaswitch, "switchbounce.
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--1414
Whyisitaproblem?
Ifsuchaswitchisused asasourcetoanedge-triggered inputsuchas INT0,thentheMCS-51 willthink thatthere were
severalevents
an
drespon
dseveral
times.
Thebouncingoftheswitchmaylastforseveralmilliseconds.GiventhattheMCS-51operatesatmicrosecond
speed,ashort ISR mayexecuteseveraltimesinresponsetotheabove described bounciness
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--1515
Hardware Solution
Thesimplesthardwaresolutionusesan RC timeconstanttosuppressthebounce. Thetimeconstanthastobelargerthantheswitchbounceand istypically 0.1seconds.
Aslongascapacitorvoltage doesnotexceed athreshold value,
theoutputsignal willbecontinued toberecognized asalogic1. Thebufferaftertheswitchproducesasharphigh-to-low
transition.Vcc
OUT
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--1616
Hardware Solution
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--1717
Software Solution
Itisalsopossibletocounterthebouncingproblemusingsoftware.
Theeasies wayisthe wait-and-seetechniqueWhentheinput drops,an appropriate delayis
executed (10 ms),thenthevalueofthelineischecked againtomakesurethelinehasstopped
bouncing
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--1818
Interfacinga Keypad
scan: mov P1,#EFH
jnb P1.0,db_0
scan1: jnb P1.1,db_1
scan2: jnb P1.2,db_2
scan3: jnb P1.3,db_3scan4: mov P1,#DFH
jnb P1.0,db_4
..
..
..P1.3
P1.2
P1.1
P1.0
P1.7
P1.6
P1.5
P1.4
0123
567
DEF
9AB
C
8
4
8051
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--1919
Interfacinga Keypaddb_0: lcall wt_10msjb P1.0, scan1
mov A, #0
ljmp get_code
db_1: lcall wt_10ms
jb P1.1, scan2
mov A, #1ljmp get_code
..
..
get_code: mov DPRT, #key_tab
movc A, @A+DPRTljmp scan
key_tab: db 0123456789ABCDEF
END
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--2020
Simpleoutput devices
Case-1 LEDis ONforanoutputofzeroMost LEDs drop1.7 to 2.5 voltsand need about10ma Currentis (5-2)/470
Case-2 Toomuchcurrent FailureofPortor LED
Case-3Notenough drive (1ma) LEDtoo dim
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--2121
The 7-SegmentDisplay
7 LEDsarranged toformthenumber 8.Byturningonand offtheappropriatesegments
(LEDs), differentcombinationscanberoduced.
usefulfor displayingthe digits 0 through 9,and somecharacters.
a
b
c
f
e
g
d
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--2222
The 7-segmentDisplay (Cont.)
7-segment displayscomein 2 configurations:
Common Anode Common Cathode
As wehaveseen,it would bepreferabletoconnect
thecathode ofeach diodetotheoutput pin. Therefore,thecommonanode variety would be
better forourinterfacingneeds.
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--2323
Interfacinga 7-segment display
Also,asseen withinterfacingthe LED,aresistor willbeneeded tocontrolthecurrentflowingthroughthe diode. Thisleavestwopossibilities:
Case 2 would bemoreappropriateascase1 willproduce differentbrightness dependingonthenumberof LEDsturned on.
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--2424
Useofcurrentbuffer
InterfacingtoaDIPswitchand 7-segment display Outputa 1toON asegment
Wecanuse 74244 tocommoncathode 7_seg
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--2525
BCDto 7_Seglookuptable
mov a,p3
anl a,0fh
get_code: mov DPTR, #7s_tab
movc A, @A+DPRT mov p1,a
7s_tab: db 3fh,30h,5bh,4fh,66h
db 6dh,7dh,07h,7fh,6fh
END
a
b
c
f
ed
f
e
a
b
e
g
d
a
b
c
g
d
b
c
fg
a
c
fg
d
a
c
f
e
g
d
a
b
c
a
b
c
f
e
g
d
a
b
c
fg
d
BCD pgfe d cba
7_seg
he
x
0000 0 0 1111 11 3f
0001 0 0 11 0 0 0 0 30
0010 0 1 0 11 0 1 1 5b
0011 0 1 0 0 11 11 4f
0100 0 11 0 0 1 1 0 66
0101 0 11 0 11 0 1 6d
0110 0 11111 0 1 7d
0111 0 0 0 0 0 111 07
1000 0 1111111 7f
1001 0 11 0 1111 6f
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--2626
LCD Interfacing
Liquid CrystalDisplays (LCDs)
cheap and easy wayto displaytext
Variousconfigurations (1lineby 20 X charupto 8
lines X 80 ). Integrated controller
The displayhastworegister command register
data register
By RS youcanselectregister
Datalines (DB7-DB0)used totransfer dataandcommands
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--2727
Alphanumeric LCD Interfacing
Pinout 8 datapinsD7:D0 RS:Dataor Command
Register Select R/W: Read orWrite E:Enable (Latch data)
RS Register Select RS = 0 p Command Register RS = 1p Data Register
R/W = 0 p Write , R/W = 1p Read E Enable
Used tolatchthe datapresentonthe datapins.
D0 D7 Bi-directional data/command pins. Alphanumericcharactersaresentin ASCII format.
E
R/W
RS
DB7DB0
LCD
controller
communications
bus
Microcontrolle
r
8
LCD Module
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--2828
LCD Commands
The LCDsinternalcontrollercanacceptseveralcommandsand modifythe displayaccordingly.Thesecommands would bethingslike: Clearscreen
Returnhome
Decrement/Incrementcursor
After writingtothe LCD,ittakessometime forit
tocompleteitsinternaloperations.Duringthistime,it willnotacceptanynew commandsor data.Weneed toinserttimedelay betweenanytwocommands
or datasentto LCD
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--2929
PinDescription
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Command Codes
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--3131
LCD Addressing
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--3232
LCD Timing
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--3434
Interfacing LCD with 8051
LM015
8051
P1.7-P1.0 D7-D0
RW
RS
E
P3.4
P3.5
P3.3
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--3535
Interfacing LCD
with 8051
mov A, commandcall cmddelaymov A, another_cmd
call cmddelaymov A, #Acall datadelaymov A, #Bcall datadelay.Command and Data Write Routines
data:mov P1, A ;A is ascii datasetb P3.3 ;RS=1 dataclr P3.4 ;RW=0 for writesetb P3.5 ;H->L pulse on Eclr P3.5
retcmd:mov P1,A ;A has the cmd word
clr P3.3 ;RS=0 for cmdclr P3.4 ;RW=0 for writesetb P3.5 ;H->L pulse on Eclr P3.5ret
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--3636
Example
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--3737
StepperMotors
moreaccuratelycontrolled thananormal
motorallowingfractionalturnsorn
revolutionstobeeasily done low speed,and lowertorquethana
comparableD.C.motor
usefulforprecisepositioningforrobotics Servomotorsrequireapositionfeedback
signalforcontrol
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--3838
StepperMotorDiagram
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--3939
StepperMotor Step Angles
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--4040
Terminology
Stepspersecond, RPM
SPS = (RPM * SPR) /60
Numberofteeth
4-step, wave drive 4-step, 8-step
Motorspeed (SPS)
Holdingtorque
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--4141
StepperMotor Types
Variable Reluctance
PermanentMagnet
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--4242
Variable ReluctanceMotors
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--4343
Variable ReluctanceMotors
Thisisusuallyafour wiremotor thecommon wiregoestothe +vesupplyand thewindingsarestepped through
Ourexampleisa 30o motor Therotorhas 4 polesand thestatorhas6
poles
Example
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--4444
Variable ReluctanceMotors
Torotate weexcitethe 3 windingsinsequenceW1 - 1001001001001001001001001
W2 - 0100100100100100100100100
W3 - 0010010010010010010010010
Thisgivestwofullrevolutions
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--4545
UnipolarMotors
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--4646
UnipolarMotors
Torotate weexcitethe 2 windingsinsequenceW1a - 1000100010001000100010001
W1b - 0010001000100010001000100
W2a - 0100010001000100010001000
W2b - 0001000100010001000100010
Thisgivestwofullrevolutions
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--4747
Basic ActuationWaveForms
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--4848
UnipolarMotors
Torotate weexcitethe 2 windingsinsequenceW1a - 1100110011001100110011001
W1b - 0011001100110011001100110
W2a - 0110011001100110011001100
W2b - 1001100110011001100110011
Thisgivestwofullrevolutionsat1.4 times
greatertorquebuttwicethepower
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--4949
EnhancedWaveforms
bettertorque
moreprecisecontrol
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--5050
UnipolarMotors
Thetwosequencesarenotthesame,sobycombiningthetwoyoucanproducehalfstepping
W1a - 11000001110000011100000111
W1b - 00011100000111000001110000
W2a - 01110000011100000111000001
W2b - 00000111000001110000011100
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--5151
Motor Control Circuits
Forlow currentoptionstheULN200xfamilyofDarlington Arrays will drivethewindings direct.
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Interfacingto StepperMotors
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--5353
Example
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--5454
Digitalto Analog Converter
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--5555
Example Step Ramp
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AnalogtoDigital
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Vin Range
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--5858
Timing
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Interfacing ADC
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Example
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--6161
Temperature Sensor
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--6262
Printer Connection
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IO Base Addressfor LPT
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--6464
PrintersPorts
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--6565
8255
8051haslimited numberof I/O ports
onesolutionistoadd parallelinterfacechip(s)
8255 isaProgrammablePeripheralInterfacePPI
Add itto 8051toexpand numberofparallelports
8051 I/O port doesnot havehandshaking capability
8255 canadd handshakingcapabilityto 8051
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hsabaghianbhsabaghianb @ kashanu.ac.ir@ kashanu.ac.ir MicroprocessorsMicroprocessors 11--6666
8255
Programmable
Peripheral
Interface
(PPI)Has 3 8_bitports A,Band C
Port C canbeused astwo 4 bitports CL and Ch
Twoaddresslines A0, A1and a Chipselect CS
8255can
be
configure
dby
writing
acontrol-
wor
din CR register
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8255 ControlWord
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8255 ModeDefinition Summary
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Mode 0
Providessimpleinputand outputoperationsforeachofthethreeports.No handshakingisrequired, dataissimply
writtentoorread fromaspecified port.Two 8-bitportsand two 4-bitports.
Anyportcanbeinputoroutput.
Outputsarelatched.
Inputsarenotlatched
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Mode1
Mode1BasicfunctionalDefinitions:TwoGroups (Group A and GroupB).
Eachgrouphasone 8-bit dataportand one 4-bitcontrol/dataport.
The 8-bit dataportcanbeeitherinputoroutput.Bothinputsand outputsarelatched.
The 4-bitportisused forcontroland statusofthe 8-bit dataport.
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8255 mode1 (output)
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Mode1 Control Signals
Output Control SignalDefinitionOBF (OutputBufferFullF/F). (C7 for A, C1forB)
The OBFoutput willgo lowtoindicatethatthe CPUhas written dataouttothespecified port.l A signaltothe devicethatthereis datatoberead.
ACK (Acknowledge Input). (C6for A, C2 forB)A lowonthisinputinformsthe 8255 thatthe data
fromPort A orPortBhasbeenaccepted.l A responsefromtheperipheral deviceindicatingthatit
hasread the data.
INTR (Interrupt Request). (C3 for A, C0 for
B)
A highonthisoutputcanbeused tointerrupttheCPU whenanoutput devicehasaccepted datatransmitted bythe CPU.
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Timing diagramformode1(output)
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8255 mode1 (input)
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Mode1 Control Signals
Input Control SignalDefinition STB (Strobe Input). (C4 for A, C2 forB)
A lowonthisinputloads dataintotheinputlatch.
IBF (InputBufferFullF/F) (C5 for A, C1forB)
A highonthisoutputindicatesthatthe datahasbeenloaded intotheinputlatch;inessence,anacknowledgementfromthe 8255 tothe device.
INTR (Interrupt Request) (C3 for A, C0 forB)
A highonthisoutputcanbeused tointerruptthe
CPU whenaninput deviceisrequestingservice.
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Timing diagramformode1(input)
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Mode 2 - Strobed BidirectionalBus I/O
MODE 2 BasicFunctionalDefinitions:Used inGroup A only.
One 8-bit,bi-directionalbusport (Port A)and a
5-bitcontrolport (Port C).Bothinputsand outputsarelatched.
The 5-bitcontrolport (Port C)isused forcontroland statusforthe 8-bit,bi-directionalbusport (Port A).
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Mode 2 Output Operations
OBF (OutputBufferFull). The OBFoutputwillgolow toindicatethatthe CPUhaswritten dataouttoport A.
ACK (Acknowledge). A low onthisinputenablesthetri-stateoutputbufferofPort A tosend outthe data. Otherwise,theoutputbuffer willbeinthehighimpedancestate.
Input Operations STB (Strobe Input). A low onthisinput
loads dataintotheinputlatch. IBF (InputBufferFullF/F). A highonthis
outputindicatesthat datahasbeenloadedintotheinputlatch.
Pin Function
PC7 /OBF
PC6 /ACK
PC5 IBF
PC4 /STB
PC3 INTR
PC2 I/O
PC1 I/O
PC0 I/O
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BSR Mode
Ifused inBSR mode,thenthebitsofportC canbesetorresetindividually
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BSR Modeexample
Move dptr, 0093h
Up: Move a, 09h ;set pc4
Movx @dptr,a
Acall delay
Mov a,08h ;clr pc4
Movx @dptr,a
Acall delaySjmp up
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Interfacing 8255 with 8051
CS isused tointerface 8255 with 8051 If CS isgenerated fromletssay Addresslines
A15:A12 asfollows,A15:A13 = 110
Addressof 8255 is110 xxxxxxxxxxx00b
Baseaddressof 8255 is 1100 0000 0000 0000b=C000H
Addressoftheregisters A = C000H
B = C001H
C = C002H CR = C003H
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Interfacing 8255 with 8051
8255
8051
7413838 decoder
74373
P0.7-P0.0(AD7-AD0)
D7-D0
D7-D0
/CS
A0
A1O0
O1
O7
A2
A1
A0
P2.7(A15)
P2.6(A14)
P2.5(A13)
ALE
/RD
/WR
/RD
/WR
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8255 Usage: SimpleExample 8255 memorymapped to 8051ataddress C000H base
A = C000H,B = C001H, C = C002H, CR = C003H Control word forallportsasoutputsinmode0
CR :1000 0000b = 80H
test: mov A, #80H ; control word mov DPTR, #C003H; address of CR movx @DPTR, A ; write control word
mov A, #55h ; will try to write 55 and AA; alternatively
repeat:mov DPTR,#C000H ; address of PA movx @DPTR, A ; write 55H to PAinc DPTR ; now DPTR points to PB movx @DPTR, A ; write 55H to PB
inc DPTR ; now DPTR points to PC movx @DPTR, A ; write 55H to PCcpl A ; toggle A (55pAA, AAp55)acall MY_DELAY ; small delay subroutinesjmp repeat ; for (1)
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