Microprocessor system architectures – IA32 tasks Jakub Yaghob

Microprocessor system architectures – IA32

tasks

Jakub Yaghob

Using tasks in OS

1 thread = 1 task 1 process = 1 task All processes = 1 task

Structure of a task

Task state Segment selectors CS, DS, ES, FS, GS, SS General registers EAX-ESP Flags EFLAGS Instruction pointer EIP Control register CR3

Private paging virtual address space The state of TR Selector in LDTR The I/O map Software interrupt redirection map (Pentium+) Stack pointers to the 0-2 privilege level stacks Link to previously executed task

Involved registers and data structures

Task State Segment TSS

TSS descriptor Task gate descriptor Task register TR The flag NT in EFLAGS

NT = Nested Task

TSS structure

Fields in the TSS 32b – I

Fields in the TSS 32b – II

Fields in the TSS 32b – III

TSS descriptor 32b

Task gate descriptor

Using task gate

Task register

Holds a selector to a TSS descriptor

Hidden part

Current task

Task switching Explicit switch

Explicit task switching as a subprogram using CALL Explicit task switching using JMP As a target is either TSS descriptor or task gate descriptor

Checking EPL ≤ DPL Implicit switch

Implicit switch (CPU makes it during some operation) for interrupt or exception handling A target task is provided by task gate descriptor in the IDT

Return from a task using IRET with pre-set NT in EFLAGS Return from „subprogram“ A target task taken from the LINK field of the current TSS

Task switching – mechanism Obtaining a target TSS Checking EPL ≤ DPL The target task is present and its

length≥67h The target task is available for

jumps or busy for return Paging in current, target TSSs and

all used descriptors Clearing B in the old descriptor for

JMP and IRET, leaving original B (=1) for CALL and IRQ

Clearing NT executing IRET

Storing current state into current TSS

Setting NT in new EFLAGS executing CALL or during IRQ, keeping the NT value from new EFLAGS executing JMP or IRET

Setting B in the new descriptor for JMP, CALL, IRQ, leaving original B for IRET

Loading TR with new TSS descriptor

Loading a new state from TSS Loading new segment

descriptors Executing the new task

Task linking

Only when a task is switched using CALL or an interrupt/exception handling using a task gate

It is not possible to make a recursion

Task management in long mode

Task switching not available All attempts cause #GP

64-bit TSS must exist RSPn – stacks for privilege levels 0-2 ISTn – Interrupt Stack Table I/O map

Fields in the TSS 64b – I

Fields in the TSS 64b – II