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Confidential © ams AG 2015
Mixed signal ASIC – design and
development considerations
Richard Maguire
August, 2015
Confidential © ams AG 2015
ams introduction
Foundry and silicon overview
Agenda
Fabrication
Assembly + Test
Summary
Confidential © ams AG 2015
Page 3
At a glance
• Focus on high performance analog semiconductors
• Sensor solutions, sensor interfaces, power management, wireless
• Ultra-low power, highest accuracy, sensitivity and integration
• Analog IDM: world class design + in-house manufacturing
Wafer manufacturing
• 200mm in-house fab (2015E 180k wafers p.a.)
• CMOS nodes: 0.18µm – 0.35µm – 0.8µm
• Specialty analog processes
• Best-in-class efficiency
• Multi-source security: TSMC, UMC, GlobalFoundries (former IBM)
Assembly and test
• In-house test in Austria and the Philippines
• Multi-source assembly locations
• End-to-end fully integrated supply chain
• Further expansion of test capacity in 2015
ams overview
Confidential © ams AG 2015
Page 4
Our focus
High performance analog ICs and foundry services
Target markets Consumer and Communications Industrial, Medical, & Automotive
64% of revenues 2014 36% of revenues 2014
Core expertiseSensor and sensor
interfaces
Power
managementWireless
Confidential © ams AG 2015
Page 5
Quality commitment
• Certified under
- ISO/TS16949 (automotive)
- ISO/TS13485 (medical)
- ISO 14001 (environment)
• Zero defect commitment with industry-leading field failure rates
• Global quality systems with local resources/labs in key markets
• Top rankings by customers
Corporate responsibility
• Member of the UN Global Compact
• CDP (Carbon Disclosure Project) participant
• Conflict metals/hazardous-use materials program implemented
• 70% reduction of CO2 footprint since 2003;
ongoing reduction measures
Quality and responsibility commitment
Confidential © ams AG 2015
ams introduction
Foundry and silicon overview
Agenda
Fabrication
Assembly + Test
Summary
Confidential © ams AG 2015
Page 7
Digital v Analog / Mixed Signal
Digital – 90nm, 45nm, 23nm .. Analog – 350nm, 180nm, 130nm
Brain Senses
Defined I/O – > 1 or 0
Standard building blocks
AND, NAND, OR,
NOR, XOR
Low voltage
Low power
High Speed
“a bit like SW”
Decision making and logic
applications
Range of I/O – Voltage, Current, Frequency
Custom IP blocks
tracks, resistors, capacitors,
inductors, diodes, transistors
Noise
Sensitivity
Interference / protection
“jigsaw puzzle”
Sensors, Sensor interfaces, Power
Management, RF
Confidential © ams AG 2015
Page 8
DesignSilicon
FabricationAssembly Test
3rd Party
Own
In-house
I want to make a chip ….
Confidential © ams AG 2015
Page 9
analog mixed-signal PDK should help you to achieve
• Optimum Time to Market
• Complete Environment for First Time Right Designs
• More Efficient Designs (Die Size, Performance, Yield)
• Simulation and proven models
PDK can include
• Proven design flows
• Silicon qualified building blocks (analog/digital/IP libraries)
• Statistical models, device parasitics, noise models, …
• Support of several design platforms
• Userware & interface software
• Documentation, training & design support
Design environment: PDK
Confidential © ams AG 2015
Page 10
IP blocks – examples for mixed signal
hitkit
Digital Library (3.3V)
Digital Library (5.0V)
Digital IO Cells
Bandgap cells
OpAmps, Comparators
Converters (8, 10 bit)
POR Library (5.0V)
Analog IO Cells
Internal IP blocks
ADCs (up to 12 bit)
DAC (12 bit)
LVDS / PECL driver
RAM / ROM blocks
OTPs
Embedded EEPROM & Flash
Advanced IP blocks
LED drivers
LDOs
DC-DC converters
SoC blocks
Interfaces (SPI, I²C)
Microcontroller
ARM cortex
Standard One time license fee License + royalty
Confidential © ams AG 2015
Page 11
DesignSilicon
FabricationAssembly Test
• Design Kit
• Design support
• IP blocks
• ESD protection
• Design for test
• Design verification
• Lead time planning
• Wafer test / sort
• Special flow
• Post processing
• Build planning
• Lead frame / RDL
• Special packaging
• Resource planning
• Mixed signal capability
• Ownership
• Resource
• Problems
• Optimization / improvement
• Qualification
What do you need?
Confidential © ams AG 2015
Page 12
Production planning - considerations
Option 1 – Silicon only / Foundry
Silicon lead time – 16 weeks Fab out = invoice
Transportation / Shipping
Assembly – 2 weeks Assembly out = invoice 2
Transportation / Shipping **
Test - 2 weeks Test - pack - ship = invoice 3 (or 2 **)
Option 2 – Full Service Foundry
Silicon lead time – 16 weeks Fab out
Assembly – 2 weeks Assembly out
Test - 2 weeks Test - pack - ship = invoice
Option 2 Managed end to end
Costs
Pull-ins and Push-outs
Yields
Confidential © ams AG 2015
ams introduction
Foundry and silicon overview
Agenda
Fabrication
Assembly + Test
Summary
Confidential © ams AG 2015
Page 14
Fabrication – what you need
Tape-out,
Mask generation
Parasitic EXT
Accurate models
DRC/LVS/ERC
Rule files LEF FilesPcells
Technology file
IP Blocks
Schematics
Symbols
Components
Schematic/
Gate level
Pre-layout
Simulation
Block
Layout
Place &
Route
Layout
Verification
Post-
layout
Simulation
Synthesis
Std. Cell Libs
Timing Libs
Simulation
env.
Acc. models
Timing Libs
Tape-out is a major milestone - it means the design phase is completed
Next step is to make a mask set - often the most expensive NRE-related cost in ASIC production.
Typically, there are 3 types of maskset services
Confidential © ams AG 2015
Page 15
Multi project wafer (MPW) or Taxi run or Shuttle Service
+ Lowest costs
- Limited number of devices
- Fixed schedule
- Prototyping only
Multi Layer Reticle (MLR) or Multi Layer Mask (MLM)
+ Tape out at any time
+ Manufacture as many samples as required
+ Moderate NRE due to reduced # of masks
- Mask set cannot be used for mass production
Single die tooling (SDT)
+ Tape out at any time
+ Manufacture as many samples as required
+ Mask set can be immediately used for mass production
mask set options
Confidential © ams AG 2015
Page 16
Mask options
$X$6X$10X
MPW
MPW mask
Confidential © ams AG 2015
Page 17
Production – points to note
Queue time
1 day – 4 weeks
Wafer manufacture
~2-3 days per mask
Wafer lots
25 wafers typical production lot
engineering runs
~1-2 days per mask
6 or 12 wafers
Process hold options
Additional processing available throughout the flow ……
Confidential © ams AG 2015
Page 18
Customized solutions
• Special finishes
• Color coating
• Stitching
• Optional sorts
• Probe temp from
-40°C to +150°C
• MCMs
• WLCSP
• Gold bumping
• Temp test
• Burn In
• QA screen
• T&R, tubes, tray
Get your unique high performance analog IC solution
High quality Advanced packaging Known good dies Custom process
Automotive versus Standard Flow
Frontend A Frontend B Backend WATFAB
100%
Test@TmaxSORT MRB
Safety Ink
1st Opt. Inspect AssemblyAssembly
100%
Test@25°C
QA Sample
Test@3TempFINAL TEST MRB
Automotive versus Standard Flow
Frontend A Frontend B Backend WATFAB
Defect Engineering EXT WAT
AOI
100%
Test@Tmax
100%
Test @ TminSORT
PAT, SBL, SYL
AOI
MRB
Safety ink
Defect Map Merge
DynPAT
Cleanroom
1st Opt. Inspect AssemblyASSEMBLY2nd Opt.
Insp.Temp Cycles
100%
Test@25°C100% Test
@Tmin+Tmax
QA Sample
Test@3TempFINAL TEST
PAT
MRB
DynPAT
Burn-In Safe Launch
Confidential © ams AG 2015
ams introduction
Foundry and silicon overview
Agenda
Fabrication
Assembly + Test
Summary
Confidential © ams AG 2015
Page 22
Standard technologies
• Ceramic Packages
• Standard Plastic Packages
• BGA Packages
• QFN/MLF packages
• Wafer Level Packages (WLCSP)
• Multi-Chip-Modules (MCM)
• System-in-Package (SiP)
Advanced customized packaging
• Optical packages
• Chip on Flex (COF)
• Gold Bumping
• Trench Dicing
• ECP™ (Embedded Component Packaging)
• TSV (Through Silicon Via)
Package portfolio
Confidential © ams AG 2015
Page 23
Test services
• Optimised test development
• Design For Test (DFT)
• Continuous improvement
• Test support
Test capabilites
• Dedicated testers for mixed signal / analog
• Wafer sort
• Clean room / wafer handling
• Specialist expertise eg MEMS
Test options
Confidential © ams AG 2015
ams introduction
Foundry and silicon overview
Agenda
Fabrication
Assembly + Test
Summary
Confidential © ams AG 2015
Page 25
Foundry only or Full Service FoundryFor turn-key high performance analog IC solutions
Design & eng.
support
State-of-the-art
manufacturing
Process
customization
Wafer probing
& final test
Packaging &
IC integrationIP cells
Foundry
Full Service Foundry
Confidential © ams AG 2015
Page 26
Your benefits
• Known Good Dies (no yield risks)
• Reduced lead times
• Improved cash flow
• Focus on your markets (not on your supply chain)
backend capabilities
• Test development for mixed-signal
• Good analog tester base for Wafer Sort and Final Test
• QA-screen capability from -40°C to max. 150°C
• Test handler solutions for numerous types of packages
• Multi-sourced standard and advanced package portfolio
Turnkey solutions – Full Service Foundry
Fully managed
Confidential © ams AG 2015
Thank you
Please visit our website www.ams.com
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