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ESA UNCLASSIFIED – For Official Use
Overview of Radiation Test Activities on Memories at ESA
Dr. Véronique Ferlet-Cavrois IEEE Fellow ESA ESTEC, TEC-QEC 30/04/2015
Contact for information: Veronique.Ferlet-Cavrois@esa.int
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 2
ESA UNCLASSIFIED – For Official Use
Outline
o Memories in space applications o Different types, usage in space o Availability on the market
o Radiation effects
o Radiation Hardness Assurance o Utilisation of COTS in space
o Typical examples of radiation effects in memories
o PCRAM o NAND flash o SDRAM o SRAM
o Utilisation of COTS in-flight
o Example: SRAM
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 3
ESA UNCLASSIFIED – For Official Use
Memories in space applications
Program / Configuration Storage (BIOS, FPGA configuration, etc.): PROM / E²PROM, MRAM, NAND/NOR Flash
Data Buffer (TM, HK, Instrument data, etc.): SRAM (async., sync., FIFO, DPRAM), SDRAM
MPU/MCU Memory: SRAM (async., sync.), SDRAM
Mass Memory Platform Data Handling (OBC MM):
SDRAM Payload Data Handling (PDHU, SSR, Compression MMU):
SDRAM, NAND Flash [H. Schmidt, Airbus
under ESA contract, Nov. 2014]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 4
ESA UNCLASSIFIED – For Official Use
Memories in Space Applications Payload Data Handling
4
Increase of storage
size: 10 Tbit (SAR, new optical instruments)
Increase of Data Rate: 10 Gbps (SAR)
Introduce of non-volatile memory to increase storage size at reduced power consumption and weight
[H. Schmidt, Airbus under ESA contract, Nov. 2014]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 5
ESA UNCLASSIFIED – For Official Use
Market Analysis Overview
5
2014 Forecast: Memory Market
(US$ 69.9 Billion)
2014 Forecast: Memory Units
(33.5 Billion)
* NAND = 37% NOR = 3%
* NAND = 19% NOR = 13%
Source: IC Insights [H. Schmidt, Airbus under ESA contract, Nov. 2014]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 6
ESA UNCLASSIFIED – For Official Use
Market Analysis Overview
Volatile Memory SRAM async. / sync. I/F FIFO, DPRAM, etc.
DRAM Computing (SDR, DDRx SDRAM) Mobile (LPDDRx) Graphic (GDDRx,…)
Non-volatile Memory ROM / EPROM / E²PROM
Flash NOR (1 bit, 2 bits) NAND (SLC, MLC, TLC, 3-D)
MRAM
PCRAM
FeRAM
ReRAM, …
[H. Schmidt, Airbus under ESA contract, Nov. 2014]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 7
ESA UNCLASSIFIED – For Official Use
Main radiation effects in electronic components
[R. Ecoffet, TNS June 2013]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 8
ESA UNCLASSIFIED – For Official Use
Radiation Hardness Assurance Application to Memories
ECSS-Q-ST-60-15C Space product assurance – Radiation hardness assurance – EEE components The flight lot is tested to: - TID (Co60) - SEE
- high and low energy protons - Heavy ions
- Comparison to the mission environment and device function
Difficulty when using COTS components
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 9
ESA UNCLASSIFIED – For Official Use
COTS in space
Why use Complexity of function Performance Availability Drawback Little or no traceability Rapid and un-announced design and process changes Rapid obsolescence
Packaging issues (plastic) Effects of burn-in on radiation effects Deep dielectric charging in space
Use of COTS The use of COTS does NOT necessarily result in cost saving Increase of the RISK
[L. Adams, Radiation training course May 2003]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 10
ESA UNCLASSIFIED – For Official Use
Real systems use a large variety of IC technology and generations, Different TID hardness levels
200 krad
[P. E. Dodd, 2009]
Compilation from data workshops between 2002 and 2004
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 11
ESA UNCLASSIFIED – For Official Use
Examples of radiation effects in memories
PCRAM o TID o SEE: functional failures, SEFIs
Other memory types NAND-Flash memories
o TID o Destructive events
SDRAM
o Stuck bits o SEFIs
SRAM
o MBU o Sensitivity to low energy protons o In-flight example of Latch-up
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 12
ESA UNCLASSIFIED – For Official Use
PCRAM
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 13
ESA UNCLASSIFIED – For Official Use
Micron (ex-Numonyx) Omneo P8P NP8P128A13TSM60E phase change memory Radiation test results
1. TID tests a. Co60: No functional failure up to 700 krad(Si) (also after annealing following
irradiation)
b. X-rays: No functional failures before 1.6 Mrad(Si), with one still functional above 4 Mrad(Si)
2. SEE tests a. Few SEUs under heavy ions at grazing angles
b. latch-up in all operating conditions,
c. to a minor extent single event functional interrupts, and bursts of read errors.
d. Permanent functional failures were also observed in one revision of the chips.
e. No events observed under high energy protons
3. Despite the very good TID tolerance, SEL may prevent these devices to be used in space.
[S. Gerardin, M. Bagatin, A. Paccagnella, U. Padova, 2013, ESA contract]
[S. Gerardin, et al. IEEE TNS 2014]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 14
ESA UNCLASSIFIED – For Official Use
TID test of the Omneo P8P NP8P128A13TSM60E phase change memory
Increase in the standby current as a function of x-ray received dose
[S. Gerardin, M. Bagatin, A. Paccagnella, U. Padova, 2013, ESA contract]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 15
ESA UNCLASSIFIED – For Official Use
SEE test of the Omneo P8P NP8P128A13TSM60E phase change memory
In one case, sudden spike in the supply current, which after less than 1 s went back to its normal value, likely due to a logic conflict triggered by an SEU
A previous report [O’Bryan et al. REDW 2010] indicated a lower SEL LETth than found here, but likely due to different chip revision
Revision B of the die exhibited functional failure at low LET (3.3 MeVcm2/mg)
Revision A: SEL, SEFI
Rev. A, latch-up
[S. Gerardin, M. Bagatin, A. Paccagnella, U. Padova, 2013, ESA contract]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 16
ESA UNCLASSIFIED – For Official Use
Errors signaled by dedicated bits in the status register (SR). Other times, the SR reports a successful operation, but a following read showed that the array had not been properly programmed
Single Event Functional are likely due to heavy-ion strikes on sensitive regions of the microcontroller (few thousand bits)
SEFI recovery: At low LET: reset is effective
most of the time At high LET: a power-cycle is
required in 50% of the cases In few cases, repeating the
operation is enough
Rev. A, SEFIs
[S. Gerardin, M. Bagatin, A. Paccagnella, U. Padova, 2013, ESA contract]
SEE test of the Omneo P8P NP8P128A13TSM60E phase change memory
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 17
ESA UNCLASSIFIED – For Official Use
Radiation effects in different types of memories
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 18
ESA UNCLASSIFIED – For Official Use
NAND-Flash TID: Errors in Storage Mode
18
functional breakdown of each DUT is marked with dotted line first random data errors already between 5 and 10 krad(Si) Destructive Failure between 32 and 64 krad (Si)
1E-9
1E-8
1E-7
1E-6
1E-5
1E-4
1E-3
1E-2
1E-1
1E+0
1E+1
1E+2
0 20 40 60 80 100 120
Erro
r Sha
re
Dose [krad (Si)]
DUT 51, Micron 32 Gbit, Storage 85°C, 3.6VDUT 45, Micron 16 Gbit, Storage 85°C, 3.6VDUT 60, Micron 4x32 Gbit, Storage 25°C, 3.3VDUT 53, Micron 32 Gbit, MUB Storage 25°C, 3.3VDUT 40, Micron 16 Gbit, Storage 25°C, 3.3VDUT 52, Micron 32 Gbit, Storage 25°C, 3.3VDUT 41, Micron 16 Gbit, MUB Storage 25°C, 3.3V
[K. Grürmann, IDA, ESA contract 2012-2014]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 19
ESA UNCLASSIFIED – For Official Use
NAND-Flash TID: Errors in Refresh Mode
19
Refresh every 2.5 krad(Si) first random data errors already between 3 and 30 krad(Si) periodic refresh keeps the error share below 1 · 10-5, tolerable before ECC Refresh has no influence on the Destructive Failure with periodic refresh the Destructive Failure occurrence determines the total dose
Samsung 51nm: first SEUs after 70 krad(Si), no functional breakdown until end of test at 90 krad(Si)
1E-9
1E-8
1E-7
1E-6
1E-5
1E-4
1E-3
1E-2
1E-1
1E+0
1E+1
1E+2
0 20 40 60 80 100 120
Erro
r Sha
re
Dose [krad (Si)]
DUT 61, Micron 4x32 Gbit, Refresh 25°C, 3.3VDUT 50, Micron 32 Gbit, Refresh 85°C, 3.6VDUT 54, Micron 32 Gbit, Refresh 25°C, 3.3VDUT 42, Micron 16 Gbit, Refresh 25°C, 3.3VDUT 43, Micron 16 Gbit, MUB Refresh 25°C, 3.3VDUT 44, Micron 16 Gbit, Refresh 85°C, 3.6VDUT 20, Samsung 4x8 Gbit, Refresh 25°C, 3.3V
[K. Grürmann, IDA, ESA contract 2012-2014]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 20
ESA UNCLASSIFIED – For Official Use
[Edmonds 2001]
Large part to part variations
Samsung 1Gbits DDR1 SDRAM Hyundai 64-Mb SDRAM
Single Event Hard Errors: stuck bits
Micro-dose or displacement damage
[Edmonds 2008]
20
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 21
ESA UNCLASSIFIED – For Official Use
DDR3 results – Stuck bits
21
Stuck bits: can not be removed by rewriting
4E-10
4E-8
4E-6
4E-4
4E-2
4E+0
1E-19
1E-17
1E-15
1E-13
1E-11
0 10 20 30 40 50 60 70 80
Cros
s sec
tion
[cm
² / d
evic
e]
Cros
s sec
tion
[cm
² / b
it]
LET [MeV cm² / mg]
4 Gbit Samsung - SEU4 Gbit Samsung - hard SEU4 Gbit Elpida - SEU4 Gbit Elpida - hard SEU
[M. Herrmann, IDA, ESA contract 2012-2014]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 22
ESA UNCLASSIFIED – For Official Use
Stuck bits in NAND-flash
22
0
0
0
0
0
0
0
0
0
1.E-17
1.E-16
1.E-15
1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
0 10 20 30 40 50 60
σ SEU
[cm
2bi
t-1]
LET [MeV mg-1 cm2]
SEU, Micron 16-Gbsoft SEU after 20 days, Micron 16-Gbhard SEU, Micron 16-Gbhard SEU after 20 days, Micron 16-Gb Ch
ip A
rea
/ bi
t [cm
2bi
t-1]
16-G Micron
significant soft SEU Annealing only at Nitrogen
SEU = soft SEU + hard SEU
0
10
20
30
40
50
60
1000 1200 1400 1600 1800 2000 2200 2400
Page
Add
ress
Byte Address
soft SEU
hard SEU
0 200 400 600 800 1000 1200 1400
[K. Grürmann, IDA, ESA contract 2012-2014]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 23
ESA UNCLASSIFIED – For Official Use
Destructive events in NAND-Flash
23
• Permanent damage with definite data loss
• 16 Gbit Micron shows also other DF types affecting the on-chip microcontroller
[K. Grürmann, IDA, ESA contract 2012-2014]
Thermal picture charge pump region
Samsung 8Gb NAND-Flash
[F. Irom, TNS Feb. 2010]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 24
ESA UNCLASSIFIED – For Official Use
Multiple Cell Upset in SRAMs
40nm SRAM Tilt=0, Roll=90, Xenon, UCL
[ESTEC contract 18799/04/NL/AG Hirex SEE test report, HRX/SEE/0288 STMicroelectronics 40nm SRAM test vehicle]
One ion strike can induce more than 100 cell upsets
24
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 25
ESA UNCLASSIFIED – For Official Use
SEU sensitivity for low energy proton in SRAM from 90nm and beyond
25
Devices with very low LET thresholds are sensitive to proton-induced upset by direct ionization.
[H. Puchner, REDW 2011] [B. Sierawski, TNS 2009]
Bulk 65nm SRAM
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 26
ESA UNCLASSIFIED – For Official Use
Low energy protons sensitivity in 28nm SRAMs STMicroelectronics
Method needed to calculate the SEE rate due to low energy protons in space
Low energy protons High energy beam
28nm ST
[H. Kettunen, et. al. IEEE REDW 2014] ESA contract
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 27
ESA UNCLASSIFIED – For Official Use
In-flight example SRAM Aboard Proba-2
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 28
ESA UNCLASSIFIED – For Official Use
GPS receiver: latch-up events in 512kx8 SRAM Samsung K6R4016V1D-TC10
[M. D’Alessio, et al. ESA at RADECS 2013]
The GPS counts two redundant receiver units and a current limiter; in cold redundancy logic
Samsung K6R4016V1D-TC10 DC 220 TANO6EE KOREA The devices were unsufficiently tested before flight
Proba-2: polar LEO
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 29
ESA UNCLASSIFIED – For Official Use
Statistical analysis of the GPS latch-up events from Oct-10 to Dec-12
• Average upset rate of 12 SELs/month (0.4 SEL/day) • Large variability, from 6 to 27 SELs/months • 87% SELs are in the SAA
[M. D’Alessio, et al. ESA at RADECS 2013]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 30
ESA UNCLASSIFIED – For Official Use
Statistical analysis of the GPS latch-up events (cont.)
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Cum
ulat
ive
Wei
bull
ln(-l
n(1-ΔT
)
Time difference between two consecutive latch-ups (s)
1 orbit4 orbits
14 orbits
Slope of 1: Signature of random single event effects
[M. D’Alessio, et al. ESA at RADECS 2013]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 31
ESA UNCLASSIFIED – For Official Use
The ground tests of the Samsung K6R4016V1D-TC10 shows large differences vs. Date Code – Heavy ion test
Heavy ions
[V. Ferlet-Cavrois, ESA test report 2012]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 32
ESA UNCLASSIFIED – For Official Use
The ground tests of the Samsung K6R4016V1D-TC10 shows large differences vs. Date Code – Proton test
DC220 DC328
DC922
High energy protons
[V. Ferlet-Cavrois, ESA test report 2012]
Resistive memories workshop | Véronique Ferlet-Cavrois | ESTEC | 30/04/2015 | Slide 33
ESA UNCLASSIFIED – For Official Use
Conclusion
o Test the flight lots
o Test in the application conditions
o Test to the environment specifications
Test standards: ESCC22900 TID ESCC25100 SEE RHA ECSS-Q-ST-15C Find information in: www.escies.org
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