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PROCESS AND EQUIPMENT

ENHANCEMENTS FOR C2W BONDING

IN A 3D INTEGRATION SCHEME

Keith A. Cooper, Michael D. Stead SET- North America Daniel Pascual, Sematech Gilbert Lecarpentier, Jean-Stephane Mottet SET SAS

Outline

Introduction and Statement of Challenges Hybrid Bonding with Collapsible Polymer Particulate Improvement Study Removal of Oxides prior to Bonding Conclusions and Further Work

3D Definitions

3D-Packaging: Traditional packaging interconnect technologies, including package stacking, wire bonding

3D-WLP: Wafer-level packaging, where interconnects processed post-IC passivation

3D-IC: IC technology, where 3D interconnects processed at the local level*

* Adapted from Huyghebaert, Soussan, et al. IMEC. ECTC 2010

Via “middle” Cu process

1. TSV litho (I-line)

2. TSV etch, strip & clean

3. O3-TEOS liner

5. Cu electro- plating/anneal

6. Cu/barrier/ liner CMP

Start: After W CMP

After TSV: BEOL or

passivation + sintering

W-via or contact plug

4. Ta/Cu Cu seed

Adapted from Huy-ghebaert, Soussan, et al. IMEC. ECTC 2010

Attractions of Cu TSV Fill

Familiarity of Processing Mechanical Strength Electrical Integrity Scalability of Copper Cost

Die-to-Wafer (D2W) Bonding

DIE-TO-WAFER Lower Throughput Single Chip Placement Long Bond Processes High Yield Known Good Die Good Overlay Flexibility Component and wafer sizes Different Technologies

Heterogeneity!

Challenges with Cu–Cu bonding

Bond requires high temp, long process Flat, particle-free surfaces Oxides

Cu oxidizes at STP, oxidizes rapidly at elevated temperatures

Metal oxides inhibit mechanical and electrical integrity

Outline

Introduction and Statement of Challenges Hybrid Bonding with Collapsible Polymer Particle Improvement Study Removal of Oxides prior to Bonding Conclusions and Further Work

Collective Hybrid Bonding

Cost-effective processing by segmentation of 3D assembly into D2W + Collective Bonding

Combines: High Yield and flexibility of D2W High Speed and efficiency of parallel process

Landing wafer

Wafer-level bonding tool

Landing wafer

TSV-die

Pick-and-place tool

Patterned

dielectric

glue

Landing wafer

Wafer-level bonding tool

Landing wafer

Wafer-level bonding tool

Landing wafer

TSV-die

Pick-and-place tool

Patterned

dielectric

glue

Landing wafer

TSV-die

Pick-and-place tool

Patterned

dielectric

glue

Die pick and place Collective bonding

In-Situ vs. Collective Bonding

Temperature Profile

Sequential D2W bonding High Accuracy capability,

controlled by the bonder Time consuming Landing wafer sees several

bonding T-cycles

Temp.

Met

al b

ondi

ng

Die

1

time

Met

al b

ondi

ng

Die

2

Met

al b

ondi

ng

Die

n

Temp.

Bon

ding

, po

lym

er

cure

Collective bonding @ wafer level

LT

Pick

& p

lace

: die

1

Poly

mer

Ref

low

time

die

2

die

n

Wafer population @ wafer level

Collective D2W bonding Higher throughput Landing wafer sees only one

temperature cycle Accuracy depends upon

several process steps

2-Step Cu-Cu Direct Bond*

Advantages Low temp and force

attachment process Strong initial bond

maintains alignment for collective bond step

Challenges Very planar, clean,

smooth surfaces Long diffusion process Very clean bonding

environment

Bond evolution with annealing

Direct Metallic Bond after annealing (2h @ 400C)

Triple junctions at equilibrium T-Shape Triple junctions

Diffusion cones

*Source: CNRS-CEMES and CEA-LETI

1. TSV wafer with bond and probe pads 2. Spin coat thin layer of sacrificial adhesive 3. Tack dice individually using die bonder tool 4. Apply heat/force to decompose the adhesive and bond all dice in

parallel using wafer bonding tool

1. 2.

3. 4.

Bonding Plate

Heat + Force

N2 Environment

Tack/Collective Bond Overview

Die Tacking Results

Tack dice onto wafer Align each die to bond site on 300 mm wafer Place die onto wafer and apply force at

low temperature (~135 C) Repeat tack process to populate wafer 2.5 μm average placement accuracy

observed Source: Sematech

Alignment Shift From

Collective Bonding

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

11

-11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11

• Optimized Tooling and Process • Alignment improved to 2 μm (average = 0.8 um) • No damage to tooling

Misalignment vector map 300 mm wafer 1unit = 1μm

FIB-SEM Sectional Image

• Diffusion of Cu across bonding interface

Particles at Cu-Cu interface were major source of yield loss

Outline

Introduction and Statement of Challenges Hybrid Bonding with Collapsible Polymer Particle Improvement Study Removal of Oxides prior to Bonding Conclusions and Further Work

Schematic of Cu-Cu Bonding

Areas of Particulate Contributors

Particle Reductions

Performed in the framework of PROCEED project funded by French authorities and by European authorities (FEDER). PROCEED partners are: ALES, CEA LETI, STMicroelectronics, CNRS-CEMES and SET.

Sample Modifications

TEFLON Cable

channels

Particle collection

Stages and guides of low-particulate materials

Teflon Cable channels Enclosures around specific

assemblies to exhaust any particles generated locally

After Particulate Improvements

Particle counts reduced by 2-3 orders of magnitude

Alignment improved to ± 1μm Tight distribution of daisy chain contact

resistance

Outline

Introduction and Statement of Challenges Hybrid Bonding with Collapsible Polymer Particle Improvement Study Removal of Oxides Conclusions and Further Work

Requirements of

Oxide Removal Process Rapid and effective Inert to surrounding materials Minimal or no residue EHS Compliant Long-lasting Low-cost

Historical Methods of

Reducing Oxides Wet acid dips, e.g. HCl, citric acid Liquid or paste fluxes Vacuum plasma treatments

In-situ Removal of oxides

Description Schematic of In-situ reduction

Reduction Chamber Hardware

2 versions – D2D and D2W Photos of micro-chamber D2D version:

View of Chuck View of Bonding Arm

Proposal:

Novel Ex-situ Removal of Oxides Dry process at atmospheric ambient Non-toxic, non-corrosive chemistry Rapid turnaround (< 1 minute) Reduces oxide from metal surfaces and

passivates surface against re-oxidation

Ellipsometry

Change in polarization defined by Δ = phase change of reflected light Δ indicates morphology or composition

Ellipsometry of In

SETNA/SET Proprietary

► Ellipsometry confirms oxide removal

Results with Indium Bumps

Untreated Indium No adhesion Bumps were coined

Treated Indium Good adhesion Good “taffy pull”

Process Validated for Indium

Validated for: Indium-to-Indium Indium-to-metal contact pads

Room temp bonding process Strong bump-to-bump adhesion Perfect tensile rupture with pull test Demonstrated for Indium-to-Nickel Demonstrated for Indium-to-Titanium

SETNA/SET Proprietary

Process Validated for In alloys

Validated for Indium alloy-to-metal contact pads Room temp and elevated temp bonding Strong bump-to-pad adhesion MP > In, depending on composition Demonstrated for In alloy to Ni or Ti Projected to work on Sn and Ag solders

Protection from Re-oxidation

SETNA/SET Proprietary

Passivated Indium surface remains stable after 50 hours

Application-Specific Metallurgy

Indium* Indium alloys* Titanium* Nickel* Copper** Silver ** Tin** Aluminum** SnAg**

Surface prep process shows promise for a broad range of metals and alloys:

*Demonstrated with bonding tests

**Ellipsometry results are promising, no bonding tests yet

Summary

3D-IC Integration opportunity is expanding, good process flow options

Technical hurdles addressed: Throughput – Hybrid Polymer Bonding Yield – Particulate Reduction Materials – Oxide Removal Options

Areas for further study

Further Work foreseen: Characterization of ex-situ oxide reduction

process Further exploration of Collective Hybrid

Bonding

Thanks for your attention

For further info, please contact: kcooper@set-na.com glecarpentier@set-sas.fr +33 4 50 35 83 92

www.set-sas.fr