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PS/SPD Electronics Installation and Commissioning
17 July 2007
Valentin NiessOn behalf of LPC Clermont
2
PS/SPD FEB Production Status Production & Tests running smoothly now: 16 PS/SPD FEB/week (Thanks
to dedicated test team! - Catherine & Christophe - )
- No more PCB issues : 2/7 boards in preserie II
- PGA programmed before implantation / Delayed production
But … No more PGA problems !!! ( 6/15 boards PGA issues in preserie )
Potential shortcut spotted with RJ45 A2 connectors shielding back manufacturer ( Hitachi )
12 %
RJ 45 A2 connector
C side threshold
Pre
s.
Lo
t 1
Lo
t 2
Lo
t 3
Lo
t 4
16/07 23/0711/0722/06
Pre
s.
Lo
t 1
Lo
t 2
Lo
t 3
Lo
t 4
16/07 23/0711/0722/06 Valid PRS FEB
stat
us
Target is to equip C side before end of July / installation ‘on flight’
10 FEBswith A2 to
be fixed
Fai
llure
Rat
e (
% )
# P
RS
FE
B
3
PRS Electronics Installation Status
All VFE previously installed & cabled April-May
All tested and left OK
Problems: Dead contacts (RJ45 analogic signal/clock) ~1/5 boards VFE not powered / Low Voltage ~1/50 boards
Solved by re-plugging RJ45 or VFE power cable
Notice: RJ45 dead contact occur both on FE and VFE side
2 FE Half crates installed end of June: PRS0 ( SM1 )
PRS3 ( SM4 )
but A2 connector issue de-cabled / re-cabling
What did we learn from this ? + PhoTo
4
FE Installation: 1st Trial
Cabling rate: 1 crate / day … and … Its ‘feasible’ to get boards out after / but in packs of 3-4 …
Traveller Test: Short serie of production Tests ensure travel was good No surprises!
Hunt RJ45 dead contacts with noise measurements ( VFE noise rules )
With VFE
Without VFE
inf( VFE ) > sup( FE )
Dead contacts: easy to see however repairing a contact can endommage another one …
Let’s cross our fingers that the procedure always converges …
Final check required when ‘closing the box’
No excess noise
with HV up to 650 V
5
VFE POWER ISSUES
3 out of 14 VFE tested end of June seemed to be badly powered : They were left functionnal in may !!!
SM1 bottom box opened … 3 screws damaged in the battle
re-plugging power cable on VFE side solved the problem
but … no obvious bad connection spotted …
Further investigation : Access required !!!
Is the problem really mechanical? Never happened @ LPC …
So what’s about regulator boards?
The box SM1 was checked fully functional after closure. And now?
1 RJ45 bad connection spotted on VFE side ( SM4 top ), previously left due to miss-interpretation : … expect others …
6
PS LEDs as Seen with PRS0 FEBs PS/SPD> CROC / FEBs and LED TSB in PRS0 ( temporary )
steered locally ( CAT / PVSS ) Prototype CU + Final HV : operated @ nominal value of 550 V Steering HV for PMTs, VLED via PVSS (final)
Acquisition with PS/SPD FEB FE-PGA spy-RAMs
Test Sequence broadcasted on back-plane by PRS CROC / Triggers - LED TSB - FE-PGA RAM
30 c
ycle
s FE-PGA Read Start
Signal max
t
channelsTotal charge
LED TSB : external
trigger o
ut not seen
(Jumper require
d?)
)( PedVQ i
V1
V2
V3 V4 V5
Tail
7
Measured Charge, Q, in SM1
NO HV(soft bug)
Now Corrected
VFE KO(no power?)
BOTTOM
TOP
14
5
3
10
5
Max / Min is in Green
Half Board
Go
od
Go
od
Bad
Evi
lE
vil
Nominal HV 550 V
Color Map:COLD
MEDIUMHOT
8
The Good : SM1-B-VFE01
Stationary
2 GQ
rms on Q Q vs time
Q stat. dist.
Fluctuation dominated PMT
Q
2
hottest
coldest
hottest
coldest
500 evts / Ch.
2
2
Q
N e
Non uniformity in charge ~5results from:- Gain ( ~1.7 )- Illumination
Deconvoluatefrom source
non uniformities- Assume cte light / Ch. -
Q
Den
sit
y
Time ( s )
Q
9
The Good : Timing, Shape & Gain
1
2
V
V
Gain: Max / Min = 1.5 -1.7 in global agreement with
LPC measurementsBut +/- 0.2 variations by Ch.
Timing:Same t0 for all ChannelsBut … varies …
Corr = 0.8 with N-e
14-33 %
Variableshape factorsbetween Ch.
rms on
~10 % fluctuationswithin a Ch.
1
2
V
V
N-e
) (
% )
10
The Bad: SM1-B-VFE03
G 2 / Q
Additional noise‘pollutes’ signal?
From LEDs?
Gain: 1.6 measured @ LPC
Q stat. dist.OK
coldest
hottest
: 12-23 %
OK PathologicCharge, Q
Gain too high 2.1 vs 1.6
Timing &Shape OK
Compatiblewith X-talk
Q
Den
sit
y
11
The Evil: SM1-T-VFE02
Multiplepeaks
Multiplepeaks
Q: Saturation FE
2 GQ
Q stat. dist.
rms on Q Q vs timehottest
hottest
coldest
coldest
strangest
strangestFluctuations not dominated PM
Q
Time ( s )
Q
Den
sit
y
Q
2
12
The Evil Continued: VLED
Not possible toclose the light !!!
Strange behaviourof noise with VLED
To be investigated furtherIn good cases
Signal saturation for SM1-TOP
)(1033.1)( 4 ADCVVV LEDLED
VLED controlled via PVSS / calibrated with multimeter :
VLED tuned according to SM1-Bottom
Nom
inal value
No signal expected
Q
VLED ( V )VLED ( V )
(
Q )
13
Tentative Tests With SPD VFE
DAQ Tests:
Pattern injection from SPD VFE / PRS2 FEBs
Read SPD data with FEB : result = OK, but …
LED Tests:
Flash SPD LEDs and read with PS/SPD FEBs
Half of the channels have SPD bit inverted !
‘Mis-understanding between Barcelona & LPC’
Where to absorb it now? Not realistic @ FEB level
conclusion … a suivre … voir Rémi
14
Conclusion
PS/SPD FEB production on good way :
C side should be equipped end of July
Investigate VFE Powering issues / Dead contacts simultaneously
LED acquisition with FEBs performed in close to final state
Further investigate noise / more statistics
Investigate VLED behaviour
FE / VFE connection can tested from noise measurements solely
but fragile … requires the crate to be sealed after …
Fill in the Online Calo Logbook …
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