Registers and Counters

Adapted from slides b y R. H. Katz

RegistersStorage Register

Group of storage elements read/written as a unit

4-bit register constructed from 4 D FFsShared clock and clear lines

TTL 74171 Quad D-type FF with Clear(Small numbers represent pin #s on package)

Schematic Shape

D3D2D1D0

CLK Q3Q3Q2Q2

RegistersInput/Output Variations

Selective Load CapabilityTri-state or Open Collector OutputsTrue and Complementary Outputs

74377 Octal D-type FFswith input enable

74374 Octal D-type FFswith output enable

EN enabled low andlo-to-hi clock transition

to load new data intoregister

OE asserted lowpresents FF state to

output pins; otherwisehigh impedence

EN CLK

D2D1D0

13141718

256912151619

HGFEDCBA

QHQGQFQEQDQCQBQA

13141718

256912151619

Registers

Register FilesTwo dimensional array of flipflopsAddress used as index to a particular wordWord contents read or written

74670 4x4 Register File withTri-state Outputs

Separate Read and Write EnablesSeparate Read and Write AddressData Input, Q Outputs

Contains 16 D-ffs, organized asfour rows (words) of four elements (bits)

D4D3D2

Q3Q2Q1

Shift RegistersShift Registers

Storage + ability to circulate data among storage elements

Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal

Wrap around from rightmost element to leftmost element

Master Slave FFs: sample inputs while clock is high; change outputs on falling edge

Shift Direction\Reset

\ResetShift

CLK CLK CLK CLK

Q 1 1 0 0 0

Q 2 0 1 0 0

Q 3 0 0 1 0

Q 4 0 0 0 1

SQ1 Q2 Q3S S

Shift Registers

• Bidirectional Shift Registers

Q1 Q2 Q3Q0

RIGHT/LEFT

Serial data in

Shift Registers

Universal Shift Register Serial vs. Parallel InputsSerial vs. Parallel OutputsShift Direction: Left vs. Right

74194 4-bit UniversalShift Register

Serial Inputs: LSI, RSIParallel Inputs: D, C, B, AParallel Outputs: QD, QC, QB, QAClear SignalPositive Edge Triggered Devices

S1,S0 determine the shift functionS1 = 1, S0 = 1: Load on rising clk edge synchronous loadS1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element DS1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element AS1 = 0, S0 = 0: hold state

Multiplexing logic on input to each FF!

Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications

QAQBQCQD

S1S0LSIDCBA

RSICLK

QAQBQCQD

S1S0LSIDCBA

RSICLK

D7D6D5D4

Sender

D3D2D1D0

QAQBQCQD

S1S0LSIDCBA

RSICLK

QAQBQCQD

S1S0LSIDCBA

RSICLK

Receiver

D7D6D5D4

D3D2D1D0

194 194

194194

ParallelInputs

Serialtransmission

ParallelOutputs

Shift Registers

• Shift Register Application:– Parallel-to-Serial/Serial-to-Parallel Conversion

Shift Registers

• Shift Register Application:– Parallel to Serial Conversion for asynchronous communication

8-bit register

8-bit shift register

counterdiv 8

one-shot

clkgen

Serialdata in

parallel data out

D7 D6 D5 D4 D3 D2 D1 D0startbit

stopbit

Shift Registers

• Shift Register Application:– Universal Asynchronous Receiver Transmitter (UART)

micro-processor

systemUART

externaldevice

paralleldata bus

serial data out

serial data in

buffers

xmitterdata

register

receiverdata

register

xmittershift

register

receivershift

register

paralleldatabus

serialdataout

serialdata

CountersCounters

Proceed through a well-defined sequence of states in response to count signal

3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...

3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...

Binary vs. BCD vs. Gray Code Counters

A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output

Counters

Johnson (Mobius) Counter

End-Around

8 possible states, single bit change per state, useful for avoiding glitches

J CLK K

Q 1 Q 2 Q 3 Q 4

\Reset

Q CLK CLK CLK

Counters

• Up counter

• Down counter

Counters

• Uo/down counter

UP/DOWN

CountersCatalog Counter

74163 Synchronous4-Bit Up counter

Synchronous Load and Clear Inputs

Positive Edge Triggered FFs

Parallel Load Data from D, C, B, A

P, T Enable Inputs: both must be asserted to enable counting

RCO: asserted when counter enters its highest state 1111, used for cascading counters "Ripple Carry Output"

74161: similar in function, asynchronous load and reset

QAQBQCQD

163RCO

Counters74163 Detailed Timing Diagram

RCO 12 13 14 15 0 1 2

Clear Load Count Inhibit

PresentState

NextState

FlipflopInputs

Counter Design ProcedureIntroduction

This procedure can be generalized to implement ANY finite state machine

Counters are a very simple way to start: no decisions on what state to advance to next current state is the output

Example: 3-bit Binary Upcounter

State TransitionTable

FlipflopInput Table

Decide to implement withToggle Flipflops

What inputs must bepresented to the T FFsto get them to change

to the desired state bit?

This is called"Remapping the Next

State Function"

C+00011110

\Reset

Counter Design ProcedureExample Continued

K-maps for Toggle Inputs:

Resulting Logic Circuit:

Timing Diagram:

\Reset

TB = A

TC = A • B

T A = 1

00 01 11 10

1 1 1 1

00 01 11 10

0 0 0 0

1 1 1 1

00 01 11 10

0 0 0 0

0 1 1 0

Counter Design ProcedureMore Complex Count Sequence

Step 1: Derive the State Transition Diagram000 110

101010

Count sequence: 000, 010, 011, 101, 110

Step 2: State Transition Table

PresentState

NextState

C00001111

B00110011

A01010101

C+0X01X10X

B+1X10X10X

A+0X11X00X

Counter Design ProcedureMore Complex Counter Sequencing

Step 3: Choose flip-flop type for Implementation Use Excitation Table to Remap Next State Functions

Toggle ExcitationTable

Remapped Next StateFunctions

PresentState

ToggleInputs

NextState

Q+0101

C00001111

B00110011

A01010101

C+0X01X10X

B+1X10X10X

A+0X11X00X

TC0X01X01X

TB1X01X11X

TA0X10X10X

Step 4: Draw remapped K-Maps

0 0 1 X

X 1 X 0

00 01 11 10

1 0 1 X

X 1 X 1

00 01 11 10

0 1 0 X

X 0 X 1

00 01 11 10

TC = A C + A C = A xor C

TB = A + B + C

TA = A B C + B C

Step 5: Obtain minimized logic expressions

Resulting Logic:

Timing Waveform:

RCount

\Reset

5 Gates13 (Input Literals + Flip-flop connections)

Step 6: Implement

Self-Starting CountersStart-Up States

At power-up, counter may be in possible state

Designer must guarantee that it (eventually) enters a valid state

Especially a problem for counters that use a subset of states

Self-Starting Solution:Design counter so that even the invalid states eventually transition to valid state

Two Self-Starting State Transition Diagrams for the Example Counter

Implementationin Previous

Slide!000

001 011 100

Self-Starting Counters

Deriving State Transition Table from Don't Care Assignment

Present State

Next State

C+ 0 1 0 1 0 1 0 1

B+ 1 1 1 0 1 1 0 0

A+ 0 1 1 1 1 0 0 1

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Inputs to Toggle Flip-flops State Changes

State Transition Table

0 0 1 X

X 1 X 0

00 01 11 10

1 0 1 X

X 1 X 1

00 01 11 10

0 1 0 X

X 0 X 1

00 01 11 10

0 1 0 1

1 1 1 0

00 01 11 10

1 1 0 1

1 0 0 1

00 01 11 10

0 0 0 0

1 1 1 1

00 01 11 10

Implementation with Different FF Types

J-K FFs

J-K Excitation Table

Remapped Next State Functions

PresentState

NextState

Remapped Next State

Q+ = J Q + K Q

Q+0101

C00001111

B00110011

A01010101

C+0X01X10X

B+1X10X10X

A+0X11X00X

JC0X01XXXX

KCXXXXX01X

JB1XXXX1XX

KBXX01XX1X

JA0X1XXX0X

KAXXX0X1XX

Implementation with Different FF TypesJ-K FFs Continued

JC = A

KC = A

JB = 1

KB = A + C

JA = B C

KA = C

0 0 X X

X 1 X X

00 01 11 10

X X 1 X

X X X 0

00 01 11 10

1 X X X

X X X 1

00 01 11 10

X 0 1 X

X 1 X X

00 01 11 10

0 1 0 X

X X X X

00 01 11 10

X X X X

X 0 X 1

00 01 11 10

Implementation with Different FF TypesJ-K FFs Continued

Resulting Logic Level Implementation: 2 Gates, 10 (Input Literals + Flip-flop Connections)

CLK CLK CLK J

\ C KB

A C KB JA

• D FFs– Simplest Design Procedure: No remapping needed!

PresentState

NextState

0 0 0 X

X 1 X 1

00 01 11 10

1 1 0 X

X 0 X 1

00 01 11 10

0 1 0 X

X 1 X 0

00 01 11 10

ADC = A

DB = A C + B

DA = B C

C00001111

B00110011

A01010101

C+0X01X10X

B+1X10X10X

A+0X11X00X

Implementation with Different FF TypesD FFs Continued

DC = A

DB = A C + B

DA = B C

Resulting Logic Level Implementation: 3 Gates, 8 (Input Literals + Flipflop connections)

CLK CLK

DA DB B

\ B CLK

\ C Count

\ C \ A

B \ C DA DB

• Comparison– T FFs well suited for straightforward binary counters

» But yielded worst gate and literal count for this example!

– J-K FFs yielded lowest gate count» Tend to yield best choice for packaged logic where gate count is

– D FFs yield simplest design procedure» Best literal count» D storage devices very transistor efficient in VLSI» Best choice where area/literal count is the key

Asynchronous vs . Synchronous CountersRipple Counters

Deceptively attractive alternative to synchronous design style

Count signal ripples from left to right

State transitions are not sharp!

Can lead to "spiked outputs" from combinational logic decoding the counter's state

CLK CLK

Asynchronous vs . Synchronous CountersCascaded Synchronous Counters with Ripple Carry Outputs

First stage RCOenables second stage

for counting

RCO assertedsoon after stageenters state 1111

also a functionof the T Enable

Downstream stageslag in their 1111 to

0000 transitions

Affects Count periodand decoding logic

(1) Low order 4-bits = 1111

(2) RCO goes high

(3) High order 4-bits are incremented

Asynchronous vs . Synchronous CountersThe Power of Synchronous Clear and Load

Starting Offset Counters: e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, ...

Use RCO signal to trigger Load of a new state

Since 74163 Load is synchronous, state changes only on the next rising clock edge

0110is the state

to be loaded

D C B A

L O A D

D C B A

Asynchronous vs . Synchronous CountersOffset Counters Continued

Ending Offset Counter: e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000

Decode state todetermine when to

reset to 0000

Clear signal takes effect on the rising count edge

Replace '163 with '161, Counter with Async ClearClear takes effect immediately!

D C B A

L O A D

C L KP T

Q Q Q Q D C B A

D C B A

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