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Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability Measurement of FPGA Implementationson Software-Defined Radio Platforms
Presented by Dr. Armando Astarloa
APERT 2013
12 June 2013
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Index
1 Introduction and MotivationReliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
2 Experimental Acquisition of λ (MTBF)SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
3 Hardware for Reliable SDR
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
1 Introduction and MotivationReliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
2 Experimental Acquisition of λ (MTBF)SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
3 Hardware for Reliable SDR
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
Reliability in Electronic Devices (hardware)Parameters
(λ): Device’s failure rate.
Failure In Time (FIT) rate: Number of failures that can beexpected in 109 device-hours of operation.
Figure: The Bathtub curve[1].
Figure: Evolution of theBathtub curve.
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
Reliability in Electronic Devices (hardware)Parameters
Reliability (R(t)): The probability of an electronic system toperform its required functions under stated conditionsfor a specified period of time. R(t1) is the probabilityof a system will not fail in time t1.
R(t) = e−λt (1)
Mean Time Between Failures (MTBF): Average time a systemruns between failure.
MTBF =
∫ ∞0
e−λtdt =1
λ(2)
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
Reliability in Electronic Devices (hardware)Temporal errors in electronic devices
Single Event Effects (SEEs):1 Heavy ion strikes the silicon2 It loses its energy via the production of free electron hole pairs3 A dense ionized track in the local region is generated4 A bit-flip can be induced (SEU, SET, SEFI, MBU, SEL
-permanent-)
Figure: An ion passing through a transistor
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
Reliability in Electronic Devices (hardware)Fault tolerance techniques in electronic devices
Redundancy:
Physical redundancy: Plain design, Tripe ModularRedundancy with simple voter, Partitioned Tripe ModularRedundancy with multiple simple voters, XTMR.
Temporal redundancy: Same processing ∆(t) and furthercomparison.
Figure: Tripe Modular Redundancy with simple voter.
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
Reliability in Electronic Devices (hardware)Standard for Functional Safety and Certifications
Electronic products certification forcritical applications
Analysis and development methods
Safety integrity levels: SIL1-SIL4(IEC 61508)
Two modes of operation: Highdemand rate and Low demand rate
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
Reliability in Electronic Devices (hardware)Safety integrity levels
Table: IEC-61508 Safety integrity Level for high demand rate systems(dangerousfailures/hr)
Safety integrity Level λ required
SIL4 between 10−8 and 10−9
SIL3 between 10−7 and 10−8
SIL2 between 10−6 and 10−7
SIL1 between 10−5 and 10−6
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FPGAs nowadaysThe electronic design is living a ‘revolution’
Current status:
New silicon technologies allow the integration of whole digitalsystems in a single ‘chip’
The design of Application Specific Integrated Circuits is moreand more expensive, complex and risky
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FPGAs nowadaysAnswer: Reconfigurable logic (FPGAs)
What is a FPGA?:
It is similar to a ‘un-formatted chip’
It can be ‘load’ with a custom circuit designed using specificEDA tools
Modern FPGAs offer similar features to ASICs
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FPGAs nowadaysFPGAs trade-off
Success keys:
Affordable engineering
Low risk: Reconfigurable
Low product time-to-market
Flexible electronic boards (they can bereused for different products)
Challenges:
Susceptible to SEE (SEUs)
Programmability (Safety standards)
Example:
Virtex-5 nominal 131 FIT/Mbconfiguration cells [2]XC5VLX50T 11,37 Mb ofconfiguration cells > 1489 FITnominal or an MTBF of 77 years
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
COTS FPGAs on critical applicationsNASA SpaceCube (source [3])
Figure: SPACE cube1.0 CPU.
Figure: STS-125launch.
Figure: Californiawildfire scene
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FT and EM techniques in FPGAsTemporal errors in FPGAs
Figure: FPGA architecture.Figure: SEU effect in FPGAs.
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FT and EM techniques in FPGAs
A XOK
OK
X X XX
MAJORITYVOTER
B
CLK
COMB
LOGIC
COMBLOGIC
COMBLOGIC
OK
Figure: Tripe Modular Redundancy with simple voter in a FPGA. [4]
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FT and EM techniques in FPGAs
XTMR architecture - XTMRtriplicates:
All inputs including clocks andthroughput (combinational) logic.
Feedback logic and insertingmajority voters on feedback paths.
All outputs, using minority votersto detect and disable incorrectoutput paths.
COMBLOGIC
TR0
COMBLOGIC
TR1
COMBLOGIC
TR2
A
X
B
CLK
MAJORITYVOTER
MAJORITYVOTER
MAJORITYVOTER
MINORITYVOTER
MINORITYVOTER
MINORITYVOTER
LUT
LUT
LUT
Figure: XTMR architecture.
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FT and EM techniques in FPGAs
XTMR design flow:
Tra ns la te (NGDBuild)
Ma p
BitGe n
.BIN
Tra ns la te (NGDBuild)
Ma p
BitGe n
.BIN
IS E P roje ct
(.NGC)
(.NGC)
(.EDF)
P a s o 1P roye cto P re -XTMR
P a s o 2P roye cto TMR Tool
P a s o 3P roye cto P os t -XTMR
Ge ne ra r Ne tlis XTMR
Figure: XTMR design flow.
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FT and EM techniques in FPGAs
Scrubbing:
FPGA
Memory Comparator
Modifier
...010101010 ...
...010101010...
...010111010...
Original Frame Data
Erroneous Frame Data
Corrected Frame Data
Figure: Scrubbing concept.
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FT and EM techniques in FPGAs
Internal Scrubbing combined with Error Correcting Code(ECC):
Control LogicPicoBlaze Processor
PicoBlaze BRAM
Frame ECC ICAP
DMA BRAM
ICAP DMAFPGA Primitives
Configuration Memory
Figure: SEU controller macro in Virtex-5 [5].
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FT and EM techniques in FPGAs
Block RAMs Scrubbing (Internal RAM memory):
Din_B
AB
Web
Data_OutB0
BRAM_Block0
VD
ERRORData_Voter0
Voted_Data0
Din_B
AB
Web
Data_OutB1
BRAM_Block1
VD
ERRORData_Voter1
Voted_Data1
Din_B
AB
Web
Data_OutB2
BRAM_Block2
VD
ERRORData_Voter2
Voted_Data2
Data_Out[0|1|2]
Address_CNTR
EN[0|1|2]
Address_B[0|1|2]
Error_indication[0|1|2]
CNT_TR[0|1|2]
COMPARATOR
ENB[0|1|2]
WEB[0|1|2]
�
CEN_BSCNTR_TMR[0|1|2]CEN_BSCNT_TMR[0|1|2]
BRAM ENB for Address Compare
ADDRA_[0|1|2] + WEA[0|1|2]
Figure: BlockRAM scrubber macro block diagram [6].
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Reliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
FT and EM techniques in FPGAsPartial Reconfiguration for Fault Tolerance
Partial reconfiguration is supported by Xilinx
Technological challenges overcome (Virtex-4):
Internal reconfiguration ports (ICAP)No frame restriction (16-CLB range)No SRL16 and LUT RAMs limitations
RPD Design flow enhanced
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
1 Introduction and MotivationReliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
2 Experimental Acquisition of λ (MTBF)SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
3 Hardware for Reliable SDR
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
SEU Test Set-upTest Flow
COM2
COM1
USB
3 3TMR_CLK TMR_UART
FPGA RS232
Evaluation Board (EB)
FPGA RS232
Board Under Test (BUT)JTAG
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
Analysis Results for Cipher BlocksTest Flow
Analyzed SEU Resilience of thefollowing VHDL Cipher Blocks[7]:
DES [8]
AES [9]
Twofish [10]
Inject SEU or MBU intooriginal bitstream
program device with altered bitstream
send input
read output of thecipher chain
verify correct operation and log current testrun
next input
(1)
(2)
(3)
(4)
(5)
UART_in UART_out
Data
Key
Start
Blockciphercore 0
Out
Rdy
Out
Rdy
Data
Key
Start
Blockciphercore 1
Data
Key
Start
Blockciphercore n
RX
Reg
iste
r
RS232receive
RS232transmitM
uxOut
Rdy
Out
Rdy
Data
Key
Start
Blockciphercore 2
Out
Rdy
Out
Rdy
Out
Rdy
Out
Rdy
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
Analysis Results for Cipher BlocksAnalysis Results
0
50
100
150
200
DES AES TwoFish
Mea
n T
ime
Bet
wee
n F
ailu
re in
yea
rs
InjectionEstimation
82.4
75.6 74.1
182.1
190.4
149.9
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
Analysis Results for on-chip bus ArchitecturesRedundant Architectures Compared
Inject SEU or MBU into random bit- stream position
program deviceusing modified
configuration stream
run application on FPGA and read
device output
check outputagainst expected
and log the test run
nexttestrun
(a) Test Flow (b) Wishbone shared in-
terconnection
[11]WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
Analysis Results for on-chip bus ArchitecturesRedundant Architectures Compared
CLK0
CLK1
TMRmaster 0
TMRmaster 1
TMRmaster n
TMRslave 0
TMRslave 1
TMRslave m
ArbiterShared WishBone Inter- connection
RST0
TMRmaster 0
TMRmaster 1
TMRmaster n
TMRslave 0
TMRslave 1
TMRslave m
ArbiterShared WishBone Inter- connection
RST1
Master 0 Master 1 Master n
Slave 0 Slave 1 Slave m
Arbiterconnection
CLK2
RST2
UART Voter to PC
Shared WishBone Inter- ...
(c) Coarse-grained TMR
ArbiterArbiter
Slave 0Instance 2
M0 Voter M1 Voter Mn Voter
S0 Voter S1 Voter Sm Voter
Master 0Instance 2
ArbiterShared WishBone Inter- connection
CLK
RST
CLK1
CLK2
CLK0
RST1
RST2
RST0
Master 1Instance 2
Master nInstance 2
Slave 1Instance 2
Slave mInstance 2
UART Voter to PC
...
(d) Medium-grained TMR
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
Analysis Results for on-chip bus ArchitecturesAnalysis Results
Table: Test Results for External and Internal voting
Error type TestrunsCoarse-grained Medium-grained
Errors Per-cent
Errors Per-cent
SEU 17500 0 0 36 0.21
2bit-MBU 12500 58 0.46 51 0.41
2bit-MBU∗ 12500 36 0.29 67 0.54
3bit-MBU 12500 185 1.48 67 0.54
4bit-MBU 12500 337 2.70 103 0.82
5bit-MBU 12500 558 4.46 140 1.12
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
Analysis Results for on-chip bus ArchitecturesAnalysis Results
Table: Categories of test results
Cat. DescriptionSystembehavior
A All TMR layer counters are zero
CorrectB One TMR layer counter differs from zero
CTwo or three of the TMR layer counters differ fromzero
DTwo or three of the TMR layer counters differ fromzero Erroneous
E Two or three of the TMR layer counters are zero
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
Analysis Results for on-chip bus ArchitecturesAnalysis Results
90,3%83,7% 80,9%
73,5%67,2%
59,8%
9,7%15,9%
18,5%
24,7%
29,4%
34,7%
2,7% 4,4%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
SEU 2bit-MBU* 2bit-MBU 3bit-MBU 4bit-MBU 5bit-MBU
Cat.D
Cat.C
Cat.B
Cat.A
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
1 Introduction and MotivationReliability in Electronic Devices (hardware)FPGAs nowadaysCOTS FPGAs on critical applicationsFT and EM techniques in FPGAs
2 Experimental Acquisition of λ (MTBF)SEU Test Set-upAnalysis Results for Cipher BlocksAnalysis Results for on-chip bus Architectures
3 Hardware for Reliable SDR
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Partial Reconfiguration and TMR on FPGA based Rugged Systems
SafeVPX has 3U Eurocard size and it can run in stand-alonemode or it can be plugged in a 3U VPX (VITA 46, air-cooled)back-plane. In this last case, SafeVPX supports 3 fat-pipes. Eachfat-pipe is composed of four bidirectional Multi-Gigabit-Transceiver(MGT) links. Each fat-pipe channel allows the implementation ofPCIe x4, Aurora or other protocol among high-speedcommunication standards.
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Key features
Features
Virtex-5 FPGA (5VFX100-TFF1136) industrialrange
Hard PowerPC processor FPGA embedded
CRC protected DDR2 memory (5 Gb)
2 isolated CAN communication channels
1 isolated serial communications link
3 isolated sigma-delta ADCs
1 SFP connector (Gigabit Ethernet or FibreOptics)
Ready for stand-alone or VPX racked operation
3U Eurocard factor form (3U VPX VITA 46)
FMC connector (only available for stand-alone(operation mode)
Multiple options for full and partial bitstreamsstorage
Extended temperature range
FPGA ready for Xilinx X-TMR implementation:
Triplicated clock inputs
Triplicated CAN communication lines
Triplicated serial communication lines
Triplicated General Purpose I/Os
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Combination with SDR boards
RuggedSDR Boards(VPXor stand-alone)Last generationSoftware-Defined-Radio boards for airor conduction cooledsystems
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Air-cool or Conduction-Cool
SDRlab Chassis3U VPX Laboratory Equipmentwith Power Supply and easilyremovable cover
LightVPX Chassis3U Conduction-cooled chassis andclamshells
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Conclusions
Reliability in electronics systems is a challenge with nowadayslevels of integration and complexityModern FPGAs and SoPCs are the key circuits instate-of-the-art boardsError mitigation and Fault Tolerance traditional techniquesare applicable with FPGAsExperimental analysis techniques combined with the use ofstandards defined for rugged systems can ensure high levels ofreliability on SDR Platforms
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Research Projects:
This work has been partially supported by the Ministerio de Ciencia e Innovacion of Spain within theproject TEC2011-28250-C02-01.
This work has been carried out inside de Research and Education Unit UFI11/16 of the UPV/EHU andsupported by the Department of Education, Universities and Research of the Basque Government withinthe fund for research groups of the Basque university system IT394-10.
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
Thank you for your attention!
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
C. Constantinescu, “Trends and challenges in VLSI circuit reliability,” IEEE Micro, vol. 23, no. 4, pp.
14–19, 2003.
Xilinx Corp., “Device reliability report, fourth quarter 2010,” Xilinx Documentation, http://www.xilinx.com,
Feb. 2011.
D. Petrick, T. Flatley, A. Geist, D. Espinosa, G. Crum, M. Lin, J. Hosler, M. Buenfil, and K. Blank,
“SpaceCube: Current Missions and Ongoing Platform Advancements,” in Military and AerospaceProgrammable Logic Devices (MAPLD), 2009.
A. Morillo, A. Astarloa, A. Zuloaga, U. Bidarte, and J. Lazaro, “Tecnicas de diseno seguro con FPGAs,” in
XVII Seminario Anual de Automatica, Electronica Industrial e Instrumentacion (SAAEI10), vol. ISBN978-84-95809-75-9, 2010.
K. Chapman and L. Jones, “SEU strategies for Virtex-5 devices,” XAPP864, 2009, Xilinx Inc.
G. Miller, C. Carmichael, and G. Swift, “Single-Event Upset Migration for Xilinx FPGA Block Memories,”
Xilinx Application Notes, http://www.xilinx.com/support/documentation/application notes/xapp962.pdf,Mar. 2008.
U. Kretzschmar, A. Astarloa, and J. Lazaro, “Seu resilience of des, aes and twofish in sram-based fpga,” in
Reconfigurable Computing: Architectures, Tools and Applications. Springer, 2013, pp. 37–46.
Tetraedre Sarl, Auvernier, “TCDG - DES cryptographic module,”
http://www.tetraedre.com/advanced/index.php, sep. 2010.
H.Satyanarayana, “AES128 - Project: aes crypto core,” OPENCORES http://opencores.org, dec. 2004.
Opencores.org, “Twofish - Project: Twofish Core,” OPENCORES http://opencores.org, feb. 2002.
WIF Europe 2013
Introduction and MotivationExperimental Acquisition of λ (MTBF)
Hardware for Reliable SDRConclusions
U. Kretzschmar, A. Astarloa, J. Lazaro, M. Garay, and J. Del Ser, “Robustness of different tmr granularities
in shared wishbone architectures on sram fpga,” in Reconfigurable Computing and FPGAs (ReConFig),2012 International Conference on, 2012, pp. 1–6.
WIF Europe 2013
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