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sCombinational and Sequential Logic Circuits.
MODULE 3
Half Adder
C A B S 0 0 0 1 A 0 B 0
S 0
C 1
0 0 0 00 1 1 01 0 1 01 1 0 1
Dec Binary 1 1+1 +1 2 10
° Add two binary numbers• A0 , B0 -> single bit inputs
• S0 -> single bit sum
• C1 -> carry out
Multiple-bit Addition
A3 A2 A1 A0
0 1 0 1A 0 1 1 1B3 B2 B1 B0
B
0 1 0 10 1 1 1
A
B
0
1
0
1
1
1
1
Ai
+Bi
Ci
Si
Ci+1
° Consider single-bit adder for each bit position.
Each bit position creates a sum and carry
Full Adder
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Ci Ai Bi Si Ci+1
1 1
1 1
Ci
AiBi00 01 11 10
0
1
Si
° Full adder includes carry in Ci
° Notice interesting pattern in Karnaugh map.
Full Adder
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Ci Ai Bi Si Ci+1 Si = !Ci & !Ai & Bi
# !Ci & Ai & !Bi
# Ci & !Ai & !Bi
# Ci & Ai & Bi
° Full adder includes carry in Ci
° Alternative to XOR implementation
Full Adder
Si = !Ci & !Ai & Bi
# !Ci & Ai & !Bi
# Ci & !Ai & !Bi
# Ci & Ai & Bi
Si = !Ci & (!Ai & Bi # Ai & !Bi)
# Ci & (!Ai & !Bi # Ai & Bi)
Si = !Ci & (Ai $ Bi)
# Ci & !(Ai $ Bi)
Si = Ci $ (Ai $ Bi)
° Reduce and/or representations into XORs
Full Adder
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Ci Ai Bi Si Ci+1
1
1 11
Ci
AiBi00 01 11 10
0
1
Ci+1
° Now consider implementation of carry out
° Two outputs per full adder bit (Ci+1, Si)
Note: 3 inputs
Full Adder
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Ci Ai Bi Si Ci+1 Ci
AiBi00 01 11 10
0
1
1
1 11
Ci+1
Ci+1 = Ai & Bi
# Ci & Bi
# Ci & Ai
° Now consider implementation of carry out
° Minimize circuit for carry out - Ci+1
Full Adder
Ci+1 = Ai & Bi
# Ci !Ai & Bi
# Ci & Ai & !Bi
Ci+1 = Ai & Bi
# Ci & (!Ai & Bi # Ai & !Bi)
Ci+1 = Ai & Bi # Ci & (Ai $ Bi)
Recall:Si = Ci $ (Ai $ Bi)
Ci+1 = Ai & Bi # Ci & (Ai $ Bi)
Full Adder
A
B
S
C
C i+1
i
i
i
i
Si = Ci $ (Ai $ Bi)
Half-adder Half-adder
Ci+1 = Ai & Bi # Ci & (Ai $ Bi)
° Full adder made of several half adders
Full Adder
half-adder
half-adderA
B
i
i
C i
C i+1
S i
S
C
C
A full adder can be made fromtwo half adders (plus an OR gate).
° Hardware repetition simplifies hardware design
Full Adder
Full Adder
A B
C C
S
i i
i+1 i
i
Block Diagram
° Putting it all together • Single-bit full adder
• Common piece of computer hardware
4-Bit Adder
Full Adder
A B
0 C
S
0 0
1
0
Full Adder
A B
C
S
1 1
2
1
Full Adder
A B
C
S
2 2
3
2
Full Adder
A B
C S
3 3
4 3
C 1 1 1 0A 0 1 0 1B 0 1 1 1S 1 1 0 0
° Chain single-bit adders together.
° What does this do to delay?
4-bit Subtractor: E = 1
Full Adder
A B
C
0 0
1
0
Full Adder
A B
C
1 1
2
1
Full Adder
A B
C
2 2
3
2
Full Adder
A B
C SD
3 3
4 3 SD SD SD
E
+1
Add A to B’ (one’s complement) plus 1
That is, add A to two’s complement of BD = A - B
Adder- Subtractor Circuit
Comparator
The comparison of two numbers
outputs: A>B, A=B, A<B
Design Approaches
the truth table
22n
entries - too cumbersome for large n
use inherent regularity of the problem
reduce design efforts
reduce human errors
MagnitudeCompare
A[3..0]
B[3..0]A = B
A < B
A > B
ComparatorA0
A1
A2
A3
B0
B1
B2
B3
A_EQ_B
C0
C1
C3
C2
D01
D23
How can we find A > B?
How many rows would a truth table have?
28 = 256
Magnitude ComparatorA0
A1
A2
A3
B0
B1
B2
B3
A_EQ_B
C0
C1
C3
C2
D01
D23
If A = 1001 and B = 0111is A > B?Why?
Because A3 > B3i.e. A3 . B3’ = 1
Therefore, one term in thelogic equation for A > B isA3 . B3’
Find A > B
Comparator
If A = 1010 and B = 1001is A > B?Why? Because A3 = B3 and
A2 = B2 and A1 > B1i.e. C3 = 1 and C2 = 1 and A1 . B1’ = 1
Therefore, the next term in thelogic equation for A > B isC3 . C2 . A1 . B1’
A > B = A3 . B3’ + C3 . A2 . B2’ + …..
Magnitude Comparison
Algorithm -> logic
A = A3A2A1A0 ; B = B3B2B1B0
A=B if A3=B3, A2=B2, A1=B1and A1=B1
Test each bit: equality: xi= AiBi+Ai'Bi'
(A=B) = x3x2x1x0
More difficult to test less than/greater than
(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'
(A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0
Start comparisons from high-order bits
Implementation
xi = (AiBi'+Ai'Bi)’
Magnitude Comparison Hardware chips
Multiplexers
Select an input value with one or more select bits
Use for transmitting data
Allows for conditional transfer of data
Sometimes called a mux
4– to– 1- Line Multiplexer
Quadruple 2–to–1-Line Multiplexer
° Notice enable bit
° Notice select bit
° 4 bit inputs
°25
DEMULTIPLEXERS
A DEMULTIPLEXER (DEMUX) basically reverses the multiplexing function. It takes data from one line and distributes them to a given number of output lines. For this reason, the demultiplexers is also known as a data distributor.
A multiplexer takes several inputs and transmits one of them to the output.
A demultiplexer (DEMUX) performs the reverse operation ; it takes a single input and distributes it over several outputs.
°26
General demultiplexerFunctional diagram:- The large arrow indicates one
or more lines. The select i/p code determines to which output the DATA input will be transmitted
In other words, the demultiplexer takes one data input source and selectively distributes it to 1 of N output channels just like multiposition switch.
°27
A 1-line-to-4-line demultiplexer.
°28
The serial data input waveform (Data in) and data select inputs (So and S1) and
the corresponding data output waveforms (D0 through D3) are shown below
°29
1-line- to-8 line demultiplexer
Binary Decoder
Black box with n input lines and 2n output lines
Only one output is a 1 for any given input
BinaryDecoder
ninputs 2n outputs
2-to-4 Binary Decoder2-to-4 Binary Decoder
From truth table, circuit for 2x4 decoder is:
Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY)
X Y F0 F1 F2 F3
0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1
F0 = X'Y'
F1 = X'Y
F2 = XY'
F3 = XY
X Y
Truth Table:
2-to-4Decoder
X
Y
F0
F1
F2
F3
3-to-8 Binary Decoder3-to-8 Binary Decoder
x y z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1
F1 = x'y'z
x zy
F0 = x'y'z'
F2 = x'yz'
F3 = x'yz
F5 = xy'z
F4 = xy'z'
F6 = xyz'
F7 = xyz
Truth Table:
3-to-8Decoder
X
Y
F0
F1
F2
F3
F4
F5
F6
F7
Z
Implementing Functions Using Decoders
Any n-variable logic function can be implemented using a single n-to-2n decoder to generate the minterms OR gate forms the sum.
The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate.
Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder with m OR gates.
Suitable when a circuit has many outputs, and each output function is expressed with few minterms.
Implementing Functions Using Decoders
Example: Full adder
S(x, y, z) = (1,2,4,7)
C(x, y, z) = (3,5,6,7)
3-to-8Decoder
S2
S1
S0
x
y
z
0
1
2
3
4
5
6
7
S
C
x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
Standard MSI Binary Decoders ExampleStandard MSI Binary Decoders Example
74138 (3-to-8 decoder)
(a) Logic circuit. (b) Package pin configuration. (c) Function table.
Building a Binary Decoder with NAND Gates
Start with a 2-bit decoder Add an enable signal (E) Note: use of NANDs
only one 0 active!
if E = 0
Use two 3 to 8 decoders to make 4 to 16 decoder
Enable can also be active high
In this example, only one decoder can be active at a time.
x, y, z effectively select output line for w
Encoders
If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder.
e.g. 2n-to-n
The simplest encoder is a 2n-to-n binary encoder
One of 2n inputs = 1
Output is an n-bit binary number
.
.
.
.
.
.
2n
inputsn outputs
Binaryencoder
8-to-3 Binary Encoder8-to-3 Binary EncoderAt any one time, only one input line has a value of 1.
Inputs Outputs
I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0
1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1
I0
I1
I2
I3
I4
I5
I6
I7
y0 = I1 + I3 + I5 + I7
y1 = I2 + I3 + I6 + I7
y2 = I4 + I5 + I6 + I7
PLA’s A B
A programmable logic array (PLA) has all links programmable in both AND and OR arrays.
Very flexible.
Many applications don’t require such flexibility
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