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BY: Grass Grass RenRen
Repair Technology Research Department /EDVDRepair Technology Research Department /EDVDAug.2004
SERVICE MANUAL FOR
8399839983998399
SERVICE MANUAL FORSERVICE MANUAL FOR
83998399839983998399839983998399
83998399 N/B MaintenanceN/B Maintenance
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1. Hardware Engineering Specification …………………………………………………………………..1.1 Introduction ……………………………………………………………………………………………1.2 Hardware Specification …………………………………………………………………………………1.3 System Hardware Parts …………………………………………………………………………………1.4 Other Functions …………………………………………………………………………………….….
2. System View & Disassembly…………………………………………………………………………….2.1 System View…………………………………………………………………………………….………2.2 System Disassembly …………………………………………………………………………………….
3. Definition & Location of Connectors / Switches Setting ………………………………………………
4. Definition & Location of Major Component …………………………………………………………..
5. Pin Description of Major Component…………………………………………………………………..5.1 AMD Mobile Athlon 64 (ClawHammer) Processor ……………………………………………………….5.2 VIA K8N800 North Bridge ………………………………………………………………….…………..5.3 VIA VT8235CD South Bridge …………………………………………………………………………...
6. System Block Diagram ……………………………………………………….……………………….....
7. Maintenance Diagnostics ………………………………………………………………………………..7.1 Introduction ……………………………………………………………………………………………7.2 Diagnostic Tool for Mini PCI Slot ………………………………………………………………………7.3 Error code……………………………………………………………………………………….……..
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8. Trouble Shooting ……………………………………………………………………………………..….8.1 Base Work Condition ……………………………………………………………………………………8.2 No Power ……………………………………………………………………………………………….8.3 Battery Can not Be Charged ……………………………………………………………………………..8.4 No Display ………………………………… …………………………………………………………...8.5 External Monitor No Display ……………………………………………………………………………. 8.6 Memory Test Error …………………………………………………………………………………….. 8.7 Keyboard/Touch-pad Test Error ………………………………………………………………………...8.8 USB Port Test error……………………………………………………………………………………... 8.9 Hard Disk Drive Test Error………………………………………………………………………………8.10 CD-ROM Test Error …………………………………………………………………………………..8.11 Audio Test Failure………………………………………………………………………………..….…8.12 LAN Test Error ………………………………………………………………………………………..8.13 Modem Test Error…………… …………………………………………………………………..……8.14 Mini-PCI Test Error……….. ……… ………………………………………………………………....8.15 Card Bus&Reader Test Error…………………………………………………………………………...8.16 TV Encoder Test Error …………………………………………………………………………………
9. Spare Parts List ………………………………………………………………………………….…..…...
10. System Exploded View ……………………………………………………………………………...…..
11. Circuit Diagram ………………………………………………………………………………………....
12. Reference Material …………………………………………………………………………………..….
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1.1 Introduction
1. Engineer Hardware Specification
The 8399 motherboard would support the AMD K8 62W Dublin (32 bit) with 256KB L2 cache/ Hammer (64 bit) with 1MB L2 cache with uPGA Package. This system is based on PCI architecture, which have standard hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface (ACPI) 1.0b. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 at system start up or warm reset. System also provides icon LEDs to display system status, such as AC/Battery Power, Battery, WIRELESS LAN status, CD-ROM, HDD, NUM LOCK, CAP LOCK, and SCROLL LOCK status. It also equipped 6 USB2.0 ports.
The memory subsystem supports 0MB on board; Expandable up to 1024MB Expandable with combination of optional 128/256/512 MB memory 200-pin DDR 266/333/400 DRAM Memory Module x2, PC-2100/2700/3200 specification.
The “K8N800”chipset is a high performance, cost-effective and energy efficient solution for the implementation of desktop personal computer systems with 8 / 16-bit 800 / 600 / 400 / 200MHz HyperTransport. CPU host interface based on AMD K8 / ClawHammer. Processors. The K8N800 north bridge supports a high speed 8-bit 8x66 MhzQuad Data Transfer interconnect (V-Link) to the VT8235 South Bridge. These chips also contain a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five levels (double words) of post write buffers are included to allow for concurrent CPU and V-Link operation. For V-Link Host operation, forty-eight levels (double words) of post write buffers and sixteen levels (double words) of prefetch buffers are included for concurrent V-Link bus and DRAM / cache accesses. When combined, the V-Link host / Client controllers realize a
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Complete PCI sub-system and support enhanced PCI bus commands such as “ Master-Read-Line”, “memory-Read-Multiple” and “Memory-Write-Invalid” commands to minimize snoop overhead. In addition, advanced features are supported such as snoop ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also implemented for further improvement of overall system performance.
The VT8235CD “V-Link Client Controller” is a highly integrated PCI /LPC controller. Its internal bus structure is based on a 66 MHz PCI bus that provides 2x bandwidth compared to previous generation PCI bridge chips. The VT8235CD also provides a 533 MB/sec bandwidth Host / Client V-Link interface with V-Link-PCI and V-Link-LPC controllers. It supports six PCI slots of arbitration and decoding for all integrated functions and LPC bus.
To provide for the increasing number of multimedia applications, the AC97 CODEC VT1617/1617A is integrated onto the motherboard
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows XP and Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE, Plug & Play, and Advance configuration and power interface(ACPI).
Following chapters will have more detail description for each individual sub-systems and functions.
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CPU AMD K8 62W Dublin (32 bit)/Hammer (64 bit) with uPGA PackageThermal Ceiling 62W TDP
Core Logic VIA K8N800 + VT8235CDL2 Cache 256KB for Dublin / 1MB for HammerSystem BIOS Inside 256 KB Flash EPROM (Include System BIOS and VGA BIOS)
ACPI 1.0b; DMI 2.3.1 compliantPlug & Play capability
OSD Audio Volume Up/Down status, Brightness status, RF Antenna On/Off status, Display StatusMemory 0MB on board; Expandable up to 1024MB
Expandable with combination of optional 128/256/512 MB memory200-pin DDR 333/400 DRAM Memory Module x2, PC-2700/3200 specification
ROM Driver 12.7mm HeightCD / DVD Rom DriveCombo DriveSuper Combo Drive
HDD 2.5” (9.5 mm height): 40/60/80 GB; ATA 100/133 SupportRemovable for Distributor
Display 15” XGA TFT Display; Resolution: 1024X768Video Controller VIA K8N800 integrated(64MB SMA)Keyboard 19mm key pitch/ 3.0mm key stroke/ 307mm length
Windows Logo Key x 1; Application Key x 1Pointing Device Glide pad with 2x buttons and 2 direction scroll button
1.2 Hardware Specification(1)
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PCMCIA Cardbus Controller: ENE CB1410one type II slots CardBus / no ZV port support/ no wakeup from S3Power switch: ENE CP-2211
Indicator 3 LEDs for Power/Battery/Charge status1 LED for Radio wave status Power LED (BTO: Wireless LAN only )5 LEDs for HDD Access, ODD Access , Num lock, Cap lock and Scroll Lock
Audio System Sound Blaster Pro compatibleAC97 V2.2 CodecBuilt-in Mono Microphone2X 2W Speakers
I/O Port USB port (2.0, backward compatible with USB1.1) x 6RJ-11 port x 1RJ-45 port x 1DC input x 1VGA monitor port x1Audio-out x 1Mic-in x 1S/W Volume Control7-Pin S Video TV-Out x 1 (NTSC/PAL)
Communication Built-in 56Kbps V.90 modem support ISN standard
Built-in 10/100 M based-T LANOne Mini PCI slot and antenna reserved for wireless LAN
1.2 Hardware Specification(2)Continue to previous page
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AC Adapter Universal AC adapter 90W ; Input: 100-240V, 50/60Hz AC (support power on charge)Battery 6/8 cell (2000/2200mAH,3.7V) Li-ion smart batteryDimensions 335*280*30(min) , 335x280x42 (max)Weight 3.5kg (P)Accessories Power Cord, AC Adapter, RJ-11 Phone Cable (p),System Driver CD-TitleArchitecture Microsoft WHQL Designed for Windows XPOptions 128/256/512MB DDR RAM, AC Adapter w/o Power Cord, Battery, Notebook Carry Bag
1.3 System Hardware Parts
1.3.1 ProcessorThe AMD K8 Hammer processor family is designed to support performance desktop and workstation applications. It provides a high-performance HyperTransport. link to I/O, as well as a single 64-bit high-performance DDR memory controller.
Compatible with Existing 32-bit Code Base
Including support for SSE, SSE2, MMXTM, 3DNow!TM, technology and all legacy x86 instructions
Runs existing operating systems and drivers
Local APIC on-chip
1.2 Hardware Specification(3)Continue to previous page
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AMD x86-64 Technology
AMD.s 64-bit x86 instruction set extensions
64-bit integer registers, 48-bit virtual addresses, 40-bit physical addresses
Eight new 64-bit integer registers (16 total)
Eight new 128-bit SSE/SSE2 registers (16 total)
Integrated Memory Controller
Low-latency, high-bandwidth
72-bit DDR at 100, 133, 166 and 200MHz
HyperTransport. Technology to I/O Devices
Two 8-bit links each support 1600 mega-transfers (MT) per second or 1.6 Gbytes/s in each direction
Can be configured as single 16-bit link supporting 1600 MT/s or 3.2 Gbytes/s in each direction
64-Kbyte 2-way Associative ECC-Protected L1 Data Cache
Two 64-bit operations per cycle, 3-cycle latency
64-Kbyte 2-way Associative Parity-Protected L1 Instruction Cache
With advanced branch prediction
16-way Associative ECC-Protected L2 Cache
Exclusive cache architecture.storage in addition to L1 caches
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256 KB, 512 KB, and 1 MB options
Machine Check Architecture
Includes hardware scrubbing of major ECC-protected arrays
Power Management
Multiple low-power states
System Management Mode (SMM)
ACPI 2.0 compliant, including support for processor performance states
Electrical Interfaces
HyperTransport. Technology: LVDS-like differential, unidirectional
DDR: SSTL_2 per JEDEC DDR specification
Clock, reset, and test signals also use DDR-like electrical specifications
Packaging
754-pin lidded micro PGA
1.27-mm pin pitch
29x29 row pin array
40mm x 40mm organic substrate
Organic C4 die attach
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1.3.2 K8N800 North BridgeThe “K8N800”chipset is a high performance, cost-effective and energy efficient solution for the implementation of mobile personal computer systems with 8 / 16-bit 800 / 600 / 400 / 200 MHz HyperTransport. CPU host interface based on AMD K8 / Claw Hammer processors.
Defines Highly Integrated Solutions for Performance PC Desktop Designs
High performance North Bridge with HyperTransport. interface to AMD K8 CPU plus AGP 8x external bus to external Graphics Controller plus high-speed V-Link interface to South Bridge.
Combines with VIA VT8235CD V-Link South Bridge for integrated LAN, Audio, ATA133 IDE, and 6 USB 2.0 ports
587 Ball Grid Array package with 35 x 35 mm body size, 1.27mm ball pitch
1.5V core, 0.15 u process
High Performance HyperTransport CPU Interface
Chipset support for AMD. K8 / ClawHammer. Processor
Processor interface via HyperTransport. Bus
Separate “transmit” and “receive” buses for no lost “bus turnaround” cycles
All transmit and receive signals use 2 pin low-voltage-swing differential signalling for high-reliability and high speed
8 or 16-bit control / address / data transfer both directions
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800 / 600 / 400 / 200 MHz clock rates with “Double Data Rate”-style operation for 1600/1200/800/400 MT/s in both directions simultaneously (total 6.4GB/sec using 16-bit transfer mode)
Default 8-bit / 200 MHz operation on startup for high reliability with speedup to dual 16-bit, 800 MHz operation (6.4 GB/sec total bandwidth) under software control (transmit and receive may be different widths and / or speeds)
Full Featured Accelerated Graphics Port (AGP) 8x Controller
Supports 533 MHz 8x, 266 MHz 4x, and 133 MHz 2x transfer modes for AD and SBA signaling
AGP v3.0 compliant with 8x transfer mode
Pseudo-synchronous with the host CPU bus with optimal skew control
Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)
AGP pipelined split-transaction long-burst transfers up to 1GB/sec
Eight level read request queue
Four level posted-write request queue
Thirty-two level (quadwords) read data FIFO (256 bytes)
Sixteen level (quadwords) write data FIFO (128 bytes)
Intelligent request reordering for maximum AGP bus utilization
Supports Flush/Fence commands
Graphics Address Relocation Table (GART)
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One level TLB structure
Sixteen entry fully associative page table
LRU replacement scheme
Independent GART lookup control for host / AGP / PCI master accesses
Windows 95 OSR-2 VXD and integrated Windows 98 / 2000 / XP mini port driver support
High Bandwidth 533 MB / Sec 8-bit V-Link Host Controller South Bridge Interface
Supports 66 MHz V-Link Host interface with total bandwidth of 533 MB/sec
Operates in 2x, 4x, and 8x modes
Full duplex commands with separate command / strobe for 4x / 2x mode, half-duplex for 8x mode
Request / Data split transaction
Configurable outstanding transaction queue for Host to V-Link Client accesses
Supports Defer / Defer-Reply transactions
Transaction assurance for V-Link Host to Client access eliminates V-Link Host-Client Retry cycles
Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer Latency
All V-Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow
Highly efficient V-Link arbitration with minimum overhead
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All V-Link transactions have predictable cycle length with known command / data duration
Integrated Graphics / Video Accelerator
Optimized Share Memory Architecture (SMA)
16 / 32 / 64 MB frame buffers using system memory
Internal AGP 8x equivalent performance
Separate 128-bit data paths between north bridge and graphics core for pixel data flow and texture/command access
Graphics engine clock up to 200MHz decoupled form memory clock
High quality DVD video playback
Internal hardware VGA controller with true-color / high-color sprite for hardware cursor implementation
128-bit 2D graphics engine
128-bit 3D graphics engine
Floating point triangle setup engine
Microsoft DirectX texture compression
4.5M triangles/second setup engine
400M texels/second bilinear fill rate
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CRT display interface with 24-bit true-color RAMDAC up to 300MHz pixel rate with gamma correction capability
DFP” flat panel interface supporting single-channel or dual-channel LVDS encoders
DVI” Flat Panel Monitor 12-bit DVI 1.0-compatible interface designed for use with external TMDS encoder
AGP 8x / 4x functions muxed on DFP/DVI pins for optional external graphics controller upgrade module
Dedicated 12-bit interface to TV Encoder for NTSC or PAL TV display (may be optionally configured as 12-bit DVI 1.0 interface to external TMDS encoder for driving a Flat Panel Monitor)
DuoView+ Dual Image Capability
Direct Win98, WinME and WinXP multi-monitor, extended desktop support
Independent resolution and color depth for secondary desktop
Improved display flexibility with simultaneous LCD/CRT, CRT/DVI, CRT/TV, LCD/TV, DVI/TV operation capability
CRT, LCD or TV refresh rates are independently programmable to allow optimum image quality
Enables different images on different displays simultaneously for true multitasking
Full Media capabilities on all displays
Support for CRT resolutions up to 1920x1440 and panel resolutions up to 1600x1200
Automatic panel power sequencing and VESA DPMS CRT power-down
Extensive Display Support
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Built-in reference voltage generator and monitor sense circuits
I2C Serial Bus and DDC Monitor Communications for CRT Plug-and-Play configuration
Video Support
High quality 5-tap horizontal and 5-tap vertical scaler (up or down) for both horizontal and vertical scaling (linear interpolation for horizontal and vertical p-scaling filtering for horizontal and vertical down-scaling)
Color space conversion
Color enhancement (contrast, hue, saturation, brightness, and gamma correction)
Color and chroma key support
Hardware sub-picture blending
Bob / weave de-interlacing mode and advanced de-interlacing to improve video quality
Video gamma correction
PAL / NTSC TV output capability using external TV encoder
Support CCIR601 standard
MPEG-2/1 Video Decoder
MPEG-2 hardware slice layer, iDCT, and motion compensation for full speed DVD playback
2-D Hardware Acceleration Features
BitBLT 9bit block transfer) functions including alpha blts
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Text function
Bresenham line drawing / style line function
ROP3, 256 operation
Color expansion
Source and destination color keys
Transparency mode
Window clipping
8, 16, and 32 bpp mode acceleration
3-D Hardware Acceleration Features
Microsoft DirectX 7.0 and 8.0 compatible
OpenGL driver available
Floating-point setup engine
Triangle rate up to 4.5-million triangles per second and Pixel rate up to 400 million pixels per second for 2 texture, depth test and alpha blending
8K Texture Cache
Microsoft DirectX Texture Compression (S3TC)
Flat and Gouraud shading
Hardware back-face culling
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16-bit, 32-bit Z test, and 24+8 Z+ Stencil test support
Z-Bias support
Stipple Test, Line-Pattern test, Text re-Transparence test, Alpha test support
Edge anti-aliasing support
Two textures per pass
Tremendous Texture Format: 16/32 bpp ARGB, 1/2/4/8 bpp Luminance, 1/2/4/8 bpp Intensity, 1/2/4/8 bpp Paletized (ARGB) , YUV 422/420 format
Texture sizes up to 2048x2048
High quality texture filter modes: Nearest, Linear, Bi-linear, Tri-linear, Anisotropic
LOD-Bias support
Vertex Fog and Fog Talbe
Specular Lighting
Alpha Blending
Bump mapping
High quality dithering
ROP2 support
Internal full 32-bit ARGB format for high rendering quality
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System balance to achieve high performance
Advanced System Power Management
Power down of SDRAM (CKE)
Independent clock stop controls for CPU, DDR SDRAM, VLINK interface, graphics engine (2D,3D, video, display) and on-chip AGP bus
Suspend power plane for preservation of memory data
Suspend-to-DRAM and self-refresh power down
Low-leakage I/O pads
ACPI 1.0B and PCI Bus Power Management 1.1 compliant
Full Software Support
Drivers for major operating system and APIs (windows 9x, Windows NT, Windows2000,Windows XP, Direct3D, DirectDraw and DirectShow, OpenGL ICD for Windows 9x, NT, 2000, and XP)
Chipset and Video BIOS support (including all standard VESZA CRT display modes)
1.3.3 VIA VT8235CD BGA PCI-LPC/ISA South BridgeThe VT8235CD South Bridge is a high integration, high performance, power-efficient, and high compatibility device that supports Intel and non-Intel based processor to V-Link bus bridge functionality to make a complete Microsoft PC2001-compliant PCI/LPC system. The VT8235CD includes standard intelligent peripheral controllers:
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IEEE 802.3 compliant 10 / 100 Mbps PCI bus master Ethernet MAC with standard MII interface to externalPHYceiver.
Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT8235CD also supports the UltraDMA-133, 100, 66, and 33 standards to allow reliable data transfer at rates up to 133 MB/sec. The IDE controller is SFF-8038i v1.0 and Microsoft Windows-family compliant.
Universal Serial Bus controller that is USB v2.0 / 1.1 and Universal HCI v2.0 / 1.1 compliant. The VT8235CD includes three root hubs with six function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system environment.
Keyboard controller with PS2 mouse support.
Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the integrated RTC also includes the date alarm, century field, and other enhancements for compatibility with the ACPI standard.
Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep states (power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up. Additional functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI bus clock stop control, modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip select and external SMI.
Full System Management Bus (SMBus) interface.
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Integrated bus-mastering dual full-duplex direct-sound AC97-link-compatible sound system.
Plug and Play controller that allows complete steer ability of all PCI interrupts and internal interrupts / DMA channels to any interrupt channel. One additional steerable interrupt channel is provided to allow plug and play and reconfigure ability of onboard peripherals for Windows family compliance.
The VT8235CD also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to standard ISADMA modes. Compliant with the PCI-2.2 specification, the VT8235CD supports delayed transactions and remote power management so that slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a PCI-to-PCI bridge environment. The chip also includes eight levels (double words) of line buffers from the PCI bus to the ISA bus to further enhance overall system performance.
CPU/Cache North Bridge System Memory
VT8235
487 BGA
Expansion Cards
On boardLPC I/O
VlinkInterface
DIMM Module ID
SMB
RTCCrystal
Boot Rom
USB 2.0 Ports 0~5Keyboard/Mouse
IDE Primary and SecondaryAC97 Link
MII Fast Ethernet Interface
APLC
CACD
MA/CommandMD
GPIO, Power Control, Reset
Figure 1. PC System Configuration Using the VT8233
LPCPCI
Sideband SignalsInit/A20M#INIR/NMI
SMI/Stop CLKFERR/IGNNE Sleep
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Inter-operable with VIA Host-to-V-Link Host Controller
Combine with VT8754 (Apollo P4X333) for a complete 533 / 400 MHz FSB Pentium 4 system
Combine with VT8377 (Apollo KX400) for a complete 266 / 200 MHz FSB Athlon Socket-A system
May be used interchangeably with the VT8235CDLSout h Bridge in most board designs
High Bandwidth 533 MB/s 8-bit V-Link Client Controller
Supports 66 MHz V-Link Client interface with peak bandwidth of 533 MB/sec
V-Link operates in 2x, 4x, and 8x modes
Full duplex commands with separate Strobe / Command
Request / Data split transaction
Configurable outstanding transaction queue for V-Link Client accesses
Auto Client Retry to eliminate V-Link Host-Client Retry cycles
Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency; all V-Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow.
Highly efficient V-Link arbitration with minimum overhead; all V-Link transactions have predictable cycle length with known Command / Data duration
Auto connect / reconnect capability and dynamic stop for minimum power consumption
Parity checking to insure correct data transfers
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Integrated Peripheral Controllers
Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability
Integrated USB 2.0 Controller with three root hubs and six function ports
Dual channel UltraDMA-133 / 100 / 66 / 33 master mode EIDE controller
AC-link interface for AC-97 audio codec and modem codec
HSP modem support
Integrated DirectSound compatible digital audio controller
LPC interface for Low Pin Count interface to Super-I/O or ROM
Integrated Legacy Functions
Integrated Keyboard Controller with PS2 mouse support
Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI
Integrated DMA, timer, and interrupt controller
Serial IRQ for docking and non-docking applications
Fast reset and Gate A20 operation
Concurrent PCI Bus Controller
33 MHz operation
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Supports up to six PCI masters
Peer concurrency
Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time
Zero wait state PCI master and slave burst transfer rate
PCI to system memory data streaming up to 132Mbyte/sec (data sent to north bridge via high speed V-Link Interface)
PCI master snoop ahead and snoop filtering
Eight DW of CPU to PCI posted write buffers
Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
Four lines of post write buffers from PCI masters to DRAM
Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
Delay transaction from PCI master accessing DRAM
Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
Symmetric arbitration between Host/PCI bus for optimized system performance
Complete steerable PCI interrupts
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PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
Fast Ethernet Controller
High performance PCI master interface with scatter / gather and bursting capability
Standard MII interface to external PHYceiver
1 / 10 / 100 MHz full and half duplex operation
Independent 2K byte FIFOs for receive and transmit
Flexible dynamically loadable EEPROM algorithm
Physical, Broadcast, and Multicast address filtering using hashing function
Magic packet and wake-on-address filtering
Software controllable power down
UltraDMA- 133/ 100 / 66 / 33 Master Mode EIDE Controller
Dual channel master mode hard disk controller supporting four Enhanced IDE devices
Transfer rate up to 133MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-133 interface
Increased reliability using UltraDMA-133/100/66 transfer protocols Thirty-two levels (double words) of prefetch and write buffers
Dual DMA engine for concurrent dual channel operation
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Direct Sound Ready AC97 Digital Audio Controller
AC-Link access to 4 CODECs (AC97 + AMC97 + MC97)
Multi channel Audio
Bus Master Scatter / Gather DMA
Dedicated read and write channels supporting simultaneous stereo playback and record
Dedicated read and write channels supporting simultaneous modem receive and transmit
1 stereo DirectSound channel with source / volume control / mixer
1 shared FM / SPDIF PCM read channel
1 dedicated channel supporting multi-channel audio
32-byte line-buffers for each SGD channel
Programmable 8bit / 16bit mono / stereo PCM data format support
AC97 2.1 compliant
Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant
Full scatter gather capability
Support ATAPI compliant devices including DVD devices
Support PCI native and ATA compatibility modes
Complete software driver support
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System Management Bus Interface
Host interface for processor communications
Slave interface for external SMBus masters
Universal Serial Bus Controller
USB v2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compatible
USB v1.1 and Universal Host Controller Interface (UHCI) v1.1 compatible
Eighteen level (double words) data FIFO with full scatter and gather capability
Three root hubs and six function ports
Integrated physical layer transceivers with optional over-current detection status on USB inputs
Legacy keyboard and PS/2 mouse support
Sophisticated PC2001-Compatible Mobile Power Management
Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management
ACPI v1.0 Compliant
APM v1.2 Compliant
CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support
PCI bus clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control
Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options,
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suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up
Multiple suspend power plane controls and suspend status indicators
One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer
Normal, doze, sleep, suspend and conserve modes
Global and local device power control
System event monitoring with two event classes
Primary and secondary interrupt differentiation for individual channels
Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for system wake-up
32 general purpose input ports and 32 output ports
Multiple internal and external SMI sources for flexible power management models
Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field
Thermal alarm on external temperature sensing circuit
I/O pad leakage control
Plug and Play Controller
PCI interrupts steerable to any interrupt channel
Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, and audio
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Microsoft Windows XPTM, Windows NTTM, Windows 2000TM, Windows 98TM and plug and play BIOS compliant
Built-in NAND-tree pin scan test capability
0.22um, 2.5V, low power CMOS process
Single chip 27 x 27 mm, 1.0 mm ball pitch, 487 pin BGA
1.3.4 System Frequency Synthesizer and DDR-SDRAM Buffer: ICS950403The ICS950403 is a system clock synthesizer chip for AMD K8 based notebook systems with AMD, VIA or Ali chipset. This provides all clocks required for such a system. The ICS950403 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I 2 C interface allows changing functions, stop clock programming and frequency selection.
Output Features
2 - Differential pair push-pull CPU clocks @ 3.3V
8 - PCICLK (Including 1 free running) @ 3.3 V
3 - Selectable PCICLK/HTTCLK @ 3.3V
1 - HTTCLK @ 3.3V
1 - 48MHz @ 3.3V fixed
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Features/Benefits
Programmable output frequency
Programmable output divider ratios
Programmable output rise/fall time
Programmable output skew
Programmable spread percentage for EMI control
Watchdog timer technology and RESET# output to reset system if system malfunction
Programmable watch dog safe frequency
Support I2C index read/write and block read/write operations
Uses external 14.318MHz crystal
Support Hyper Transport Technology (HTTCLK)
48-Pin 300mil SSOP
1 - 24_48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz
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1.3.5 PC Card Interface Controller: ENE CB1410
The ENE CB1410 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant with the 1997 PC Card Standard. The ENE CB1410 provides features that make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The ENE CB1410 supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required.
The ENE CB1410 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers orCardBus PC Card bridging transactions. The ENE CB1410 is also compliant with the latest PCI Bus Power Management Interface Specification and PCI Bus Power Management Interface Specification for PCI to CardBusBridges.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The ENE CB1410 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The ENE CB1410 can also be programmed to accept fast posted writes to improve system-bus utilization.
Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the ENE CB1410, such as socket activity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification.
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An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption while operating at PCI clock rates up to 33MHz. Several low-power modes enable the host power management system to further reduce power consumption.
The CB1410 Supports the Following Features
3V operation with 5V tolerant
144-pin LQFP or 144-ball LFBGA package for CB1410 single slot Cardbus controller
Compliant with
PCI Local Bus Specification, Revision 2.2
PCI Bus Power Management Interface Specification, Revision 1.1
PCI Mobile Design Guide, Version 1.1
Advanced Configuration and Power Interface Specification, Revision 1.0
PC99 System Design Guide
PC Card Standard 8.0
Interrupt Configuration
Support parallel PCI interrupts
Support parallel IRQ and parallel PCI interrupts
Support serialized IRQ and parallel PCI interrupts
Support serialized IRQ and PCI interrupts
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Power Management Control Logic
Support CLKRUN# protocol
Supports SUSPEND#
Support PCI PME# from D3, D2, D1 and D0
Support PCI PME# from D3 cold
Supports D3STATE#
Power Switch Interface
Supports parallel 4 wire power switch interface.
Misc Control Logic
Support CLKRUN# protocol
Support serial EEPROM interface
Support socket activity LED
Support 5 GPIOs and GPE#
Support standard Zoomed Video Port
Support SPKOUT, CAUDIO and RIOUT#
Support PCI LOCK
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1.3.6 One-Slot PC Card Power Interface Switch: ENE CP-2211CP-2211 is single Slot PCMCIA and CardBus power switch. It integrates control logic, low switching resistance MOSFET, over current alarm and over temperature auto shutdown circuits. It can deliver 3.3V or 5V to PC Card VCCOUT and 3.3V, 5V or 12V to PC Card VPPOUT. The output current is up to 1A for VCCOUT and 250mA for VPPOUT.
Low Switching Resistance (100mΩ for VCC Switch)
Over temperature auto shutdown
1A output current for VCCOUT
150mA output current for VPPOUT
Only 3.3V is required for chip normal operation
12V is not required for 3.3V or 5V Output
Break-Before-Make Switching
16-Pin SSOP Package
1.3.7 AC’97 Audio System: VIA VT1617/1617AThe VT1617/1617A is a high performance audio codec which complies with the AC’97 revision 2.3. It integrates Sample Rate Converters on all channels and can be adjusted in 1Hz increments. This chip supports 96KHz sampling rates, high-quality 96KHz S/PDIF output, stereo digital playback.
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The 20bit, ΣΔADCs VT1617/1617A implements stereo recording and white noise removal to ensure the best quality of recording. It features 8-channel hardware-expansion for flexible 7.1-channel applications. It also contains a hardware down-mixing feature that allows the end users enjoy 6-channel audio with 2-channel or 4-channel speakers. The analog mixer circuitry integrates a stereo enhancement to provide a pleasing 3D surround sound effect for stereo media. The VT1617/1617A has a built-in quality headphone amplifier and a high-accuracy PLL for cost saving. This codec is designed with aggressive power management to achieve low power consumption; when used with a 3.3V analog supply, the owner consumption is further reduced.
AC’97 V2.3 Audio Codec
Fully compliant with AC’97 Revision 2.3
High Audio Quality
Support sampling rates up to 96KHz
Independent 20-bit ADC and 20-bit DAC
SNR (Signal to Noise Ratio) exceeds 95dB
Built-in 1Hz resolution VSR converter
Various Output Format
Support 8-channel outputs
Hardware down-mixed 6-channel to 2-channel or 4-channel
Center and LFE channel swapping
Alternative Line-Level outputs at surround output
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96KHz S/PDIF output
Direct CD input to S/PDIF output
Added-on Functions
Integrates headphone amplifier with mute
Dual microphones supporting Karaoke mixing
Extension Control
4-bit 3D depth control
Support EAPD control
Supports GPIO pins control
Selectable clock sources
Driver support Magic 5.1
Convenient Design
Flexible Jack-detect design
Built-in accurate PLL for saving an external crystal
Built-in Smart 5.1.
Power
Low power consumption mode
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3.3V or 5V analog, 3.3V digital power supply
2M bit Flash memory
Flashed by 5V only
User can upgrade the system BIOS in the future just running flash program.
48-Pin LQFP Package
1.3.8 System Flash Memory (BIOS)
1.3.9 Memory System
JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
Utilizes 333Mb/s and 400Mb/s DDR SDRAM components
64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64 Meg x 64 [HD])
VDD= VDDQ= +2.5V ±0.2V
Package
64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMMs
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VDDSPD = +2.2V to +5.5V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-aligned with data for WRITEs
Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/received with data—i.e.,source-synchronous data capture
Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)
Four internal device banks for concurrent operation
Selectable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh and Self Refresh Modes
15.6μs (MT4VDDT864H, MT8VDDT1664HD), 7.8125μs (MT4VDDT1664H, MT8VDDT3264HD, MT8VDDT6464HD) maximum average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Fast data transfer rates PC2700, PC2100 or PC1600
Selectable READ CAS latency for maximum compatibility
Gold-plated edge contacts
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1.3.10 LAN: VT6103L 10Base-T/100Base-TX Ethernet PHYThe VT6103L is a Physical Layer device for Ethernet 10BASE-T and 100BASE-TX using category 5 Unshielded, Type 1 Shielded, and Fiber Optic cables. This VLSI device is designed for easy implementation of 10 / 100 Mb/s Fast Ethernet LANs. It interfaces to a MAC through an MII interface ensuring interoperability between products from different vendors.
Single Chip 100Base-TX/10Base-T Physical Layer solution
Dual Speed – 100/10 Mbps
Half And Full Duplex
MII Interface to Ethernet Controller
MII Interface to Configuration & Status
Optional Repeater Interface
Auto Negotiation : 10/100, Full/Half Duplex
Meet All Applicable IEEE 802.3, 10Base-T and 100Base-Tx Standards
On Chip Wave Shaping – No External Filters Required
Adaptive Equalizer
Baseline Wander Correction
LED Outputs
Product Features
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Link Status
Duplex status
Speed Status
Collision
48 Pin SSOP Package
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1.4.1 Hot Key Function
Keys Feature MeaningCombination
Fn + F1 Wireless lan on/off Wireless Lan on ->off
Fn + F2 Reserve
Fn + F3 Volume down Adjust Audio volume down
Fn + F4 Volume up Adjust Audio volume upFn + F5 Display switch LCD->CRT->LCD&CRT, TV-out will be not TV present.
TV->CRT->TV&CRT, TV-out is connected.Fn + F6 Brightness down Adjust LCD panel backlight darkness.
Fn + F7 Brightness up Adjust LCD panel backlight lightness.
Fn + F8 MAX brightness toggle Toggle LCD brightness maximum or user setting
Fn + F9 Reserved
Fn + F10 Battery Low warning beep toggle Toggle to enable/mute the “Battery Low Warning” beep sound
Fn + F11 LCD panel toggle on/off Toggle LCD panel on or off.
Fn + F12 System sleep System sleep button function.
1.4 Other Functions
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1.4.2 Power on/off/Suspend/Resume Button
1.4.2.1 APM Mode
At APM mode, Power button is on/off system power.
1.4.2.2 ACPI Mode
At ACPI mode, power button behavior was set by windows power management control panel. You could set “standby” or “power off” to power button function. Continue pushing power button over 4 seconds will force system off at ACPI mode. There is no sleep button on this machine.
1.4.3 Lid Switch
System automatically provides a Keyboard cover state through PS2 to relative application when user closes the Keyboard cover.
1.4.4 LED IndicatorsSystem has some status LED indicators to display system activity,.
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1.4.4.1 Three LED Indicators on Display Housing/Cover:
From left to right that indicates, AC Power/Battery Power and Battery Charger
AC Power:
This LED lights green when AC powers to the notebook, and flash (on 1 second, off 1 second) when
Suspend to DRAM is active using AC power. The LED is off when the notebook is off or powered by
batteries.
Battery Power:
This LED lights green when Battery powers to the notebook, and flash (on 1second, off 1 second) when
Suspend to DRAM is active using Battery power. The LED is off when the notebook is off or powered by
AC power.
Battery Charge Status:
During normal operation, this LED stays off as long as the battery is charged. When the battery charge
drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is
connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is
being charged. When battery charging error, it will flash orange light.
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WLAN RF Status (BTO: Wireless LAN only):
This LED indicates WLAN RF module power status. User could use Fn+F1 to enable or disable RF.
1.4.4.2 Five LED Indicators above Front Side Housing:
From left to right that indicates CD, HDD, NUM LOCK, CAPS LOCK and SCROLL LOCK.
1.4.5 Fan Power on/off Management
l FAN is controlled by Embedded Controller Winbond W83L950D. Thermal with hardware monitor to sense CPU temperature and EC control fan on/off.
1.4.6 CMOS Battery
CR2032 3V 220mAh lithium battery
When AC in or system main battery inside, CMOS battery will consume no power
AC or main battery not exists, CMOS battery life is at lest 10 years
Battery was put in battery holder, can be replaced.
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1.4.7 I/O Port
One 3 pins AC power socket
One CRT monitor
One S-Video TV out (PAL/NTSC)
Six USB 2.0 ports for all USB devices
One MODEM RJ-11 phone jack for PSTN line
One RJ-45 for LAN
Headphone out Jack
Microphone Input Jack
One Cardbus Sockets for one type II PC card extensionMiTac Secret
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2.1 System View
2.1.1 Front View
2.1.2 Left-side View
Top Cover Latch1
1
Lock Ventilation Openings
1
2
1 2
2. System View and Disassembly
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2.1.3 Right-side View
2.1.4 Rear View
10 98
7
654321
CD/DVD driver Line out jack MIC in jack USB port *2 RJ-45 connector RJ-11 connector AC Power Indicator Battery Power Indicator Battery Charge Indicator PC Card slot
1
2
3
4
5
6
7
8
9
10
1 2 3 4 5
VGA port S-Video output connector Ventilation Openings USB port *4 Power connector
1
2
3
4
5
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2.1.5 Bottom View 1
Wireless Card cover CPU
1
2
1
23
45 6
78 9 10
112
2.1.6 Top-open View
LCD Screen Stereo set Keyboard Caps Lock Wireless Card Indicator CD/DVD-Rom Indicator HDD Indicator Num Lock Caps Lock Scroll Lock Power Button
1
2
3
4
5
6
7
8
9
10
11
2
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The section discusses at length each major component for disassembly/reassembly and show correspondingillustrations. Use the chart below to determine the disassembly sequence for removing components from the notebook.
2.2 System Disassembly
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure thenotebook is not turned on or connected to AC power.
Modular Components
LCD Assembly Components
Base Unit Components
NOTEBOOK
2.2.1 Battery Pack
2.2.2 Keyboard
2.2.3 CPU
2.2.4 HDD Module
2.2.5 DVD-ROM Drive
2.2.6 DDR-SDRAM
2.2.7 Modem Card
2.2.8 LCD Assembly
2.2.9 Inverter Board
2.2.10 LCD Panel
2.2.11 System Board
2.2.12 Touch Pad
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1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a clicking sound.
2. Replace the CPU cover and secure the four screws.
2.2.1 Battery Pack
Disassembly
1. Carefully put the notebook upside down.2. Remove the four screws, then remove the CPU cover. (Figure 2-1)3. Put up the battery pack, then free the battery pack. (Figure 2-2)
Figure 2-2 Remove the battery pack
Reassembly
Figure 2-1 Remove the four screws
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2.2.2 Keyboard
Disassembly
1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)2. Open the top cover.3. Loosen the five latches locking the keyboard. (Figure 2-3)
Figure 2-3 Loosen the five latches
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Reassembly
1. Reconnect the keyboard cable and fit the keyboard back. 2. Replace the keyboard into place and fasten the five latches.3. Replace the battery pack. (Refer to section 2.2.1 reassembly)
4. Slightly lift up the keyboard and disconnect the cable from the mother board, then separate the keyboard. (Figure 2-4)
Figure 2-4 Lift up the keyboard and disconnect the cableMiTac Secret
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1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)2. Disconnect the fan’s power cord from system board and remove five screws that secure the heatsink upon the
CPU, Then free the heatsink. (Figure 2-5)3. To remove the existing CPU, lift the socket arm up to the vertical position. (Figure 2-6)
2.2.3 CPU
Disassembly
Figure 2-5 Free the heatsink Figure 2-6 Disconnect the cable
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CPU socket stopper
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into the holes. Place the lever back to the horizontal position and push the lever to the left.
2. Reconnect the fan’s power cord to the system board, fit the heatsink onto the top of the CPU and secure with five screws.
3. Replace the battery pack. (See section 2.2.1 reassembly)
Reassembly
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2.2.4 HDD Module
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)2. Remove two screws fastening the HDD module and slightly lift up HDD module. (Figure 2-7) 3. Remove four screws to separate the hard disk drive from the bracket, free the hard disk driver. (Figure 2-8)
Figure 2-8 Free the HDD driverFigure 2-7 Remove HDD module
Reassembly
1. Attach the bracket to hard disk drive and secure with four screws.2. Slide the HDD module into the compartment and secure with two screws. 3. Replace the battery pack. (Refer to section 2.2.1 reassembly)
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2.2.5 CD/DVD-ROM Drive
DisassemblyDisassembly
Reassembly
1. Push the CD/DVD-ROM drive into the compartment and secure with one screw.2. Replace the battery pack. (Refer to section 2.2.1 reassembly)
Figure 2-9 Remove the CD/DVD-ROM drive
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)2. Remove one screw fastening the CD/DVD-ROM drive. (Figure 2-9)3. Insert a small rod, such as a straightened paper clip, into CD/DVD-ROM drive’s manual eject hole () and push
firmly to release the tray. Then gently pull out the CD/DVD-ROM drive by holding the tray that pops out(). (Figure 2-9)
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2.2.6 DDR-SDRAM
DisassemblyDisassembly
Reassembly
1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the DDR into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR into position.
2. Replace the battery pack. (Refer to section 2.2.1 reassembly)
Figure 2-10 Remove the DDR-SDRAM
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)2. Pull the retaining clips outwards () and remove the DDR-SDRAM (). (Figure 2-10)
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2.2.7 Modem Card
DisassemblyDisassembly
Reassembly
1. Fit the modem card, Then reconnect the cable and secure with two screws.2. Replace the battery pack. (Refer to section 2.2.1 reassembly)
Figure 2-12 Disconnect the cable
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)2. Remove the two screws. (Figure 2-11)3. Disconnect the cable from the system board, Then free the modem card. (Figure 2-12)
Figure 2-11 Remove the two screws
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2.2.8 LCD ASSY
Disassembly
Figure 2-14 Remove the two screws
1. Remove the battery pack and keyboard. (See sections 2.2.1 and 2.2.2 Disassembly)2. Remove two hinge covers. (Figure 2-13)3. Carefully put the notebook upside down. Remove the two screws fastening the wireless cover. (Figure 2-14)
Figure 2-13 Remove two hinge covers
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4. Disconnect the LCD cable from the system board and detach the antenna. (Figure 2-15)5. Remove the four screws and put up the LCD assembly, then free the LCD assembly. (Figure 2-16)
Figure 2-16 Free the LCD assembly
1. Attach the LCD assembly to the base unit and secure with four screws, then fit the antenna. 2. Reconnect the one cable to the system board, Then replace the wireless cover and secure two screws.3. Replace the two hinge covers. 4. Replace the keyboard and battery pack. (Refer to sections 2.2.2 and 2.2.1 Reassembly)
Reassembly
Figure 2-15 Disconnect the LCD cable MiTac Secret
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2.2.9 Inverter Board
Disassembly
1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.2.1, 2.2.2 and 2.2.8 Disassembly)2. Remove two screws and rubbers on the corners of the LCD panel. (Figure 2-17)3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process until
the cover is completely separated from the housing.4. Remove the one screw fastening the inverter board. (Figure 2-18)
Figure 2-18 Remove the one screwFigure 2-17 Remove LCD cover
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5. To remove the inverter board on the lower part of the LCD housing , disconnect two cables. (Figure 2-19)
Reassembly
1. Reconnect the two cables. Fit the inverter board back into place and secure with one screw. 2. Replace the LCD cover and secure with two screws and rubbers.3. Replace the LCD assembly. (Refer to section 2.2.8 Reassembly)4. Replace the keyboard and battery pack. (Refer to sections 2.2.2 and 2.2.1 Reassembly)
Figure 2-19 Remove the inverter board
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2.2.10 LCD Panel
Disassembly
1. Remove the battery, keyboard and LCD assembly. (Refer to sections 2.2.1, 2.2.2 and 2.2.8 Disassembly)2. Remove the LCD cover. (Refer for two steps 2,3 of section 2.2.9 Disassembly)3. Remove the eight screws fastening the LCD panel and detach the cable, Then lift it up. (Figure 2-20)4. Remove the five screws fastening the LCD brackets. (Figure 2-21)
Figure 2-20 Remove the eight screwsand detach the cable
Figure 2-21 Remove the five screws
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5. Disconnect the cable and free the LCD panel. (Figure 2-22)
Reassembly
1. Reconnect the cable, then replace the LCD brackets and secure with five screws.2. Fit the LCD panel back into place and secure with eight screws, then reconnect the cable to the inverter board. 3. Replace the LCD cover and secure with two screws and rubbers. (Refer to section 2.2.9 Reassembly)4. Replace the LCD assembly. (Refer to section 2.2.8 Reassembly)5. Replace the keyboard and battery pack. (Refer to sections 2.2.2 and 2.2.1 Reassembly)
Figure 2-22 Free the LCD panel
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2.2.11 System Board
Disassembly
1. Remove the battery, keyboard, CPU, hard disk drive, CD/DVD-ROM drive, DDR-SDRAM, modem card and LCD assembly. (Refer to sections 2.2.1, 2.2.2, 2.2.3, 2.2.4, 2.2.5, 2.2.6, 2.2.7 and 2.2.8 Disassembly)
2. Remove the four screws. (Figure 2-23)3. Remove the eleven screws and free the housing. (Figure 2-24)
Figure 2-24 Remove the eleven screwsFigure 2-23 Remove the four screws
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4. Remove the three screws and lift up the housing’s shielding. (Figure 2-25)5. Disconnect the speaker’s cable and the touch pad’s cable, Then remove the one screw and four hex nuts. Now
you can lift up the system board. (Figure 2-26)
Figure 2-25 Remove the three screws Figure 2-26 Free the system board
Reassembly
1. Replace the system board into the top cover and secure with one screw and four hex nuts.2. Reconnect the touch pad’s cable, the speaker’s cable.3. Replace the housing’s shielding and secure with three screws.4. Replace the housing and secure with fifteen screws. 5. Replace the LCD assembly, modem card, DDR-SDRAM, CD/DVD-ROM, HDD, CPU, keyboard and battery
pack. (See sections 2.2.8, 2.2.6, 2.2.5, 2.2.4, 2.2.3, 2.2.2 and 2.2.1 Reassembly)
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2.2.12 Touch Pad
Disassembly
1. Remove the system board. (See section 2.2.11 Disassembly)2. Remove the two screws and disconnect the cable, then free the touch pad. (Figure 2-27)
Reassembly
1. Replace the touch pad and reconnect the cable.2. Replace the touch pad shielding and secure with two screws.3. Reassemble the notebook. (See the previous sections Reassembly)
Figure 2-27 Free the touch pad
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3.1 Mother Board – A(1)
PJ1 : AC Power Jack
PJ2 : Battery Connector
J1 : S-Video Port
J2 : External VGA Connector
J3, J4, J9 : USB Port Connector
J5 : RJ11 & RJ45 Connector
J6 : North Bridge Fan Connector
J7 : MDC Jump Wire Connector
J8 : LCD Connector
J10 : Microphone Jack
J11 : CPU Fan Connector
J12 : Line Out Jack
------ To next page ------
J509
PJ2
J9 J5
J7
J8
J1
J3
J4
PJ1
J2
J11
J6
J10 J12
3. Definition & Location of Connectors / Switches
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3.1 Mother Board – A(2)
------ Continue to previous page ------
J13 : Internal Speaker Connector
J14 : Primary EIDE Connector
J15 : MDC Board Connector
J16,J17 : Extend DDR SDRAM Socket
J18 : Touch-Pad Connector
J20 : RTC Battery Connector
J21 : Secondary IDE Connector
J22 : Mini-PCI Socket
SW1 : H8 Reset Button
J509
J13
J16
J21
J22
J18
J20 SW1
J15
J17
J14
3. Definition & Location of Connectors / Switches
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3.2 Mother Board - B
J501 : Internal Keyboard Connector
J502 : PCMCIA Card Socket
SW501 : Power Button
SW502 : Touch-Pad Up Button
SW503 : Touch-Pad Right Button
SW504 : Touch-Pad Left Button
SW505 : Touch-Pad Down Button
J509
J501
SW501
SW503SW
502
SW50
5
J502
SW504
3. Definition & Location of Connectors / Switches
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4.1 Mother Board - A
U2 : VT6103L LAN Controller
U3 : TV Encoder(VIA_VT1622)
U6 : AMD CPU Socket
U9 : LVDS Encoder(VIA_VT1634)
U10 : VT1617A Audio Codec
U12 : VIA_K8N800 North Bridge
U13 : G1428 Sounder Amplifier
U14 : ICS950403 Clock Generator
U16 : KBC (W83L950D)
U20 : VIA_VT8235CD South Bridge
U25 : LPC BIOS ROM
U26 : CB1410 PCMCIA Controller
J509
U26
U20
U16
U25
U9
U2
U12U
3
U6
U14
U13
U10
4. Definition & Location of Major Components
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DDR SDRAM Memory Interface Pins Signal Name Type Description
MEMCLK_H/L[7] O-IOD Differential DDR SDRAM clock to the top of DIMM 0 for unbuffered DIMMs.1
MEMCLK_H/L[6] O-IOD Differential DDR SDRAM clock to the top of DIMM 1 for unbuffered DIMMs.1
MEMCLK_H/L[5] O-IOD Differential DDR SDRAM clock to the bottom of DIMM 0 for unbuffered DIMMs.1
MEMCLK_H/L[4] O-IOD Differential DDR SDRAM clock to the bottom of DIMM 1 for unbuffered DIMMs.1
MEMCLK_H/L[3] O-IOD Differential DDR SDRAM clock to DIMM 3 for registered DIMMs.1
MEMCLK_H/L[2] O-IOD Differential DDRS DRAM clock to DIMM 2 for registered DIMMs.1
MEMCLK_H/L[1] O-IOD Differential DDR SDRAM clock to the middle of DIMM 1 for unbuffered DIMMs, or DIMM 1 for registered DIMMs.1
MEMCLK_H/L[0] O-IOD Differential DDR SDRAM clock to the middle of DIMM 0 for unbuffered DIMMs, or DIMM 0 for registered DIMMs.1
MEMCKEA MEMCKEB
O-IOS Clock Enables to DIMMs. Used to gate clocks for power management functionality.1
MEMDQS[17:0] B-IOS DRAM Data Strobes synchronous with MEMDATA and MEMCHECK during DRAM read and writes.1
MEMDATA[63:0] B-IOS DRAM Interface Data Bus MEMCHECK[7:0] B-IOS DRAM Interface ECC Check Bits MEMCS_L[7:0] O-IOS DRAM Chip Selects 1 MEMRASA_L MEMRASB_L
O-IOS DRAM Row Address Select. MEMRASA_L and MEMRASB_L are functionally identical. Two copies are provided to accommodate the loading of unbuffered DIMMs.1
MEMCASA_L MEMCASB_L
O-IOS DRAM Column Address Select. MEMCASA_L and MEMCASB_L are functionally identical. Two copies are provided to accommodate the loading of unbuffered DIMMs.1
MEMWEA_L MEMWEB_L
O-IOS DRAM Write Enable. MEMWEA_L and MEMWEB_L are functionally identical. Two copies are provided to accommodate the loading of unbuffered DIMMs.1
MEMADDA[13:0] MEMADDB[13:0]
O-IOS DRAM Column/Row Address. Two copies are provided to accommodate the loading of unbuffered DIMMs. During precharges, activates, reads, and writes, the two copies are inverted from each other (except A[10] which is used for auto-precharge) to minimize switching noise. The signals are inverted only when the bus is used to carry address information.1
DDR SDRAM Memory Interface Pins (Continued) Signal Name Type Description
MEMBANKA[1:0] MEMBANKB[1:0]
O-IOS DRAM Bank Address. Two copies are provided to accommodate the loading of unbuffered DIMMs. During precharges, activates, reads, and writes the two copies are inverted from each other to minimize switching noise. The signals are inverted only when the bus is used to carry address information.1
MEMRESET_L O-IOS DRAM Reset pin for Suspend-to-RAM power management mode. This pin is required for registered DIMMs only.
MEMVREF VREF DRAM Interface Voltage Reference 1 MEMZP A Compensation Resistor tied to VSS 1 MEMZN A Compensation Resistor tied to 2.5 V 1 Note: For connection details and proper resistor values, see the AMD Athlon™ 64 Processor Motherboard Design Guide, order# 24665.
HyperTransport™ Technology Pin Descriptions
Note: 1.These pins are used in an alternating fashion to compensate R TT by internal comparison to 3/4 VLDT and 1/4 VLDTand compensate R ON by comparison to each other around 1/2 VLDT. For proper resistor value, see theAMD Athlon™ 64 Processor Motherboard Design Guide, order# 24665. 2.The unused L0_CTLIN_H/L[1] pins must be properly terminated such that the true pin is pulled High and thecomplement is pulled Low. Refer to the AMD Athlon™ 64 Processor Motherboard Design Guide, order# 24665, for details.
Signal Name Type Description L0_CLKIN_H/L[1:0] I-HT Link 0 Clock Input L0_CTLIN_H/L[1:0] I-HT Link 0 Control Input 2 L0_CADIN_H/L[15:0] I-HT Link 0 Command/Address/Data Input L0_CLKOUT_H/L[1:0] O-HT Link 0 Clock Outputs L0_CTLOUT_H/L[1:0] O-HT Link 0 Control Output L0_CADOUT_H/L[15:0] O-HT Link 0 Command/Address/Data Outputs L0_REF1 A Compensation Resistor to VLDT 1 L0_REF0 A Compensation Resistor to VSS 1
5.1 AMD Mobile Athlon 64(ClawHammer) Processor(1)5. Pin Descriptions of Major Components
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Miscellaneous Pin Descriptions Signal Name Type Description
RESET_L I-IOS System Reset PWROK I-IOS Indicates that voltages and clocks have reached specified
operation LDTSTOP_L I-IOS HyperTransport™ Technology Stop Control Input. Used for
power management and for changing HyperTransport link width and frequency.
VID[4:0] O-IOS Voltage ID to the regulator THERMDA A Anode (+) of the thermal diode THERMDC A Cathode (–) of the thermal diode THERMTRIP_L O-IO-O
D Thermal Sensor Trip output, asserted at nominal temperature of 125 .
COREFB_H/L A Differential feedback for VDD Power Supply VDDIOFB_H/L A Differential feedback for VDDIO Power Supply CORE_SENSE A VDD voltage monitor pin VDDA S Filtered PLL Supply Voltage VTT_SENSE A VTT voltage monitor pin VDDIO_SENSE A VDDIO voltage monitor pin VDD S Core power supply VDDIO S DDR SDRAM I/O ring power supply VLDT_A VLDT_B
S HyperTransport™ I/O ring power supply for side A and side B of the package
VTT_A VTT_B
S VTT regulator voltage for side A and side B of the die
VSS S Ground
JTAG Pin Descriptions Signal Name Type Description
TCK I-IOS JTAG Clock TMS I-IOS JTAG Mode Select TRST_L I-IOS JTAG Reset TDI I-IOS JTAG Data Input TDO O-IOS JTAG Data Output
Debug Pin Descriptions Signal Name Type Description
DBREQ_L I-IOS Debug Request DBRDY O-IOS Debug Ready
Clock Pin Descriptions Signal Name Type Description
CLKIN_H/L I-IOD 200-MHz PLL Reference Clock FBCLKOUT_H/L O-IOD Core Clock PLL 200-MHz Feedback Clock
5.1 AMD Mobile Athlon 64(ClawHammer) Processor(2)
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AGP Bus Interface Signal Name Pin # I/O Signal Description
GD[31:0] (see pin list)
IO Address / Data Bus. Address is driven with GDS assertion for AGP-style transfers and with GFARME# assertion for PCI-style transfers.
GC#BE[3:0] (GCBE[3:0]# for 4x mode)
AC7 AD11 AF11 AD15
IO Command / Byte Enable. (Interpreted as GC/BE# for AGP 2x/4x and GC#/BE for 8x). For AGP cycles these pins provide command information (different commands than for PCI) driven by the master (graphics controller) when requests are being enqueued using GPIPE# (2x/4x only as GPIPE# isn™t used in 8x mode). These pins provide valid byte information during AGP write transactions and are driven by the master. The target (this chip) drives these lines to io0000lt during the return of AGP read data. For PCI cycles, commands are driven with GFARME# assertion. Byte enables corresponding to supplied or requested data are driven on following clocks.
GPAR AC16 IO AGP Parity. A single parity bit is provided over GD[31:0] and GC#BE[3:0].
GDBIH / GPIPE#GDBIL
AC5 AC4
IO Dynamic Bus Inversion High / Low. AGP 8x transfer mode only. Driven by the source to indicate whether the corresponding data bit group (GDBIH for GD[31:16] and GDBIL for GD[15:0]) needs to be inverted on the receiving end (1 on GDBIx indicates that the corresponding data bit group should be inverted). Used to limit the number of simultaneously switching outputs to 8 for each 16-pin group. Pipelined Request. Not used by AGP 8x. Asserted by the master (external graphics controller) to indicate that a full-width request is to be enqueued by the target (North Bridge). The master enqueues one request each rising edge of GCLK while GPIPE# is asserted. When GPIPE# is deasserted no new requests are enqueued across the AD bus. Note: See RxAE[1] for GPIPE# / GDBIH pin function selection.
GADSTB0F(GADSTB0 for 4x), GADSTB0S(GADSTB0# for 4x)
AE15 AF15
IO Bus Strobe 0. Source synchronous strobes for GD[15:0] (the agent that is providing the data drives these signals). GDS0 provides timing for 2x data transfer mode; GDS0 and GDS0# provide timing for 4x mode. For 8x transfer mode, GDS0 is interpreted as GDS0F (i1Firstl. strobe) and GDS0# as GDS0S (iSSecondl. strobe).
AGP Bus Interface (Continued) Signal Name Pin # I/O Signal Description
GADSTB1F(GADSTB1 for 4x), GADSTB1S(GADSTB1# for 4x)
AE7 AF7
IO Bus Strobe 1. Source synchronous strobes for GD[31:16] (i.e., the agent that is providing the data drives these signals). GDS1 provides timing for 2x data transfer mode; GDS1 and GDS1# provide timing for 4x transfer mode. For 8x transfer mode, GDS1 is interpreted as GDS1F (iSFirstle strobe) and GDS1# as GDS1S (iSSecondld strobe).
GFRAME(GFRAME# for 4x)
AC9 IO Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator. Interpreted as active high for 8x.
GIRDY(GIRDY# for 4x)
AC10 IO Initiator Ready. (Interpreted as active low for PCI/AGP2x/4x and high for AGP 8x). For AGP write cycles, the assertion of this pin indicates that the master is ready to provide all write data for the current transaction. Once this pin is asserted, the master is not allowed to insert wait states. For AGP read cycles, the assertion of this pin indicates that the master is ready to transfer a subsequent block of read data. The master is never allowed to insert a wait state during the initial block of a read transaction. However, it may insert wait states after each block transfers. For PCI cycles, asserted when the initiator is ready for data transfer.
GTRDY(GTRDY# for 4x)
AC14 IO Target Ready. (Interpreted as active low for PCI/AGP2x/4x and high for AGP 8x). For AGP cycles, indicates that the target is ready to provide read data for the entire transaction (when the transaction can complete within four clocks) or is ready to transfer a (initial or subsequent) block of data when the transfer requires more than four clocks to complete. The target is allowed to insert wait states after each block transfer for both read and write transactions. For PCI cycles, asserted when the target is ready for data transfer.
GDEVSEL(GDEVSEL# for 4x mode)
AC11 IO Device Select (PCI transactions only). This signal is driven by the North Bridge when a PCI initiator is attempting to access main memory. It is an input when the chip is acting as PCI initiator. Not used for AGP cycles. Interpreted as active high for AGP 8x.
5.2 VIA K8N800 North Bridge(1)
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AGP Bus Interface (Continued) Signal Name Pin # I/O Signal Description
AGP8XDT# Y2 I AGP 8x Transfer Mode Detect. Low indicates that the external graphics card can support 8x transfer mode
GRBF(GRBF# for 4x)
AD6 I Read Buffer Full. Indicates if the master (graphics controller) is ready to accept previously requested low priority read data. When GRBF# is asserted, the North Bridge will not return low priority read data to the graphics controller.
GWBF(GWBF# for 4x)
AC1 I Write Buffer Full.
GSBA[7:0]# (GSBA[7:0] for 4x)
(see pin list)
I Side Band Address. Provides an additional bus to pass address and command information from the master (graphics controller) to the target (North Bridge). These pins are ignored until enabled.
GSBSTBF(GSBSTB for 4x), GSBSTBS(GSBSTB# for 4x)
AF1 AE1
I Side Band Strobe. Driven by the master to provide timing for GSBA[7:0]. 8x mode uses GSBSTBF (iBFirstlr strobe) and GSBSTBS (iBSecondl) strobe). These signals are interpreted as GSBSTB & GSBSTB# for AGP4x.
GST[2:0] AB1 AA1 AA2
O Status (AGP only). Provides information from the arbiter to a master to indicate what it may do. Only valid while GGNT# is asserted. 000 Indicates that previously requested low priority read or
flush data is being returned to the master (graphics controller).
001 Indicates that previously requested high priority read data is being returned to the master.
010 Indicates that the master is to provide low priority write data for a previously enqueued write command.
011 Indicates that the master is to provide high priority write data for a previously enqueued write command.
100 Reserved. (arbiter must not issue, may be defined in the future).
101 Reserved. (arbiter must not issue, may be defined in the future).
110 Reserved. (arbiter must not issue, may be defined in the future).
111 Indicates that the master (graphics controller) has been given permission to start a bus transaction. The master may enqueue AGP requests by asserting PIPE# or start a PCI transaction by asserting GFRM#. ST[2:0] are always outputs from the target (North Bridge logic) and inputs to the master (graphics controller).
AGP Bus Interface (Continued) Signal Name Pin # I/O Signal Description
GSTOP(GSTOP# for 4x)
AC12 IO Stop (PCI transactions only). Asserted by the target to request the master to stop the current transaction. Interpreted as active high for AGP 8x.
GREQ(GREQ# for 4x)
Y1 I Request. Master (graphics controller) request for use of the AGP bus.
GGNT(GGNT# for 4x)
AA3 O Grant. Permission is given to the master (graphics controller) to use the AGP bus.
GSERR(GSERR# for 4x)
AC15 IO AGP System Error.
Note: The AGP interface pins can be optionally configured as additional interfaces for connecting to external display devices. For simplification of the AGP pin description tables above and on the next page, that multiplexing is not shown here (see isAdditional 12C InterfaceslÓo, and display pin description tables later in this document for more information). Note: The AGP interface pins can be optionally configured as additional interfaces for connecting to external display devices. For simplification of the AGP pin description tables above and on the next page, that multiplexing is not shown here (see isAdditional I2C Interfacesll and display pin description tables later in this document for more information). Note: Separate system interrupts are not provided for AGP. The AGP connector provides interrupts via PCI bus INTA-B#. Note: A separate reset is not required for the AGP bus (RESET# resets both PCI and AGP buses) Note: Two mechanisms are provided by the AGP bus to enqueue master requests: GPIPE# (to send addresses multiplexed on the AD lines) and the SBA port (to send addresses unmultiplexed). AGP masters implement one or the other or select one at initialization time (they are not allowed to change during runtime). Only one of the two will be used; the signals associated with the other will not be used. GRBF# has an internal pullup to maintain it in the de-asserted state in case it is not implemented on the master device. AGP 8x mode allows only SBA (GPIPE# isn™t used in 8x mode). Note: AGP 8x signal levels are 0V and 0.8V. AGP 8x mode maintains most signals at a low level when inactive resulting in no current flow.
5.2 VIA K8N800 North Bridge(2)
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V-Link Interface Signal Name Pin # I/O Signal Description
VAD7, VAD6, VAD5, VAD4, VAD3, VAD2, VAD1, VAD0
AF25 AD24 AF20 AE19 AE24 AF24 AD21 AD20
IO IO IO IO IO IO IO IO
Address / Data Bus. Also used to pass strap information from the South Bridge to the North Bridge (the actual straps are on the indicated South Bridge pin and that information is passed tothe North Bridge at reset time via the VAD pins).
VPAR AF19 IO Parity. VBE# AE21 IO Byte Enable. UPCMD AF26 I Command from Client (South Bridge) to Host (North
Bridge). UPSTB AE23 I Strobe from Client to Host. UPSTB# AF23 I Complement Strobe from Client to Host. DNCMD AD23 O Command from Host (North Bridge) to Client (South
Bridge). DNSTB AF22 O Strobe from Host to Client. DNSTB# AD22 O Complement Strobe from Host to Client.
CRT Interface Signal Name Pin # I/O Signal Description
AR AG AB
B3 A3 A2
AOAOAO
Analog Red. Red output to CRT monitor. Analog Green. Green output to CRT monitor. Analog Blue. Blue output to CRT monitor.
RSET C4 AI CRT Output Reference Resistor. Tie to GNDRGB through an external 90.9 ±1% resistor to control the "RGB" RAMDAC full-scale current.
HSYNC A1 O Horizontal Sync. Digital output to CRT monitor. VSYNC B1 O Vertical Sync. Digital output to CRT monitor.
SMB / I 2 C Interface Signal Name Pin # I/O Signal Description
SBPLCLK / GIRDY
AC10 I/O I 2 C Serial Bus Clock for Panel (Muxed on AGP Bus Pins).
SBPLDAT / GC#BE1
AF11 I/O I 2 C Serial Bus Data for Panel (Muxed on AGP Bus Pins).
SBDDCCLK / GREQ
Y1 I/O I 2 C Serial Bus Clock for CRT DDC (Muxed on AGP Bus Pins).
SBDDCDAT / GGNT
AA3 I/O I 2 C Serial Bus Data for CRT DDC (Muxed on AGP Bus Pins).
SPCLK[2:1] C2, P2 IO Serial Port (SMB/I 2 C) Clocks. Clocks for serial data transfer. SPCLK1 is typically used for I 2 C communications. SPCLK2 is typically used for CRT Display DDC communications.
SPDAT[2:1] C1, P1 IO Serial Port (SMB/I 2 C) Data. Data signals for serial data transfer. SPDAT1 is typically used for I 2 C communications. SPDAT2 is typically used for CRT Display DDC communications.
Dedicated Digital Video Port 0 (DVP0) – TMDS Interface Signal Name Pin # I/O Signal Description
DVP0D11/ TVD11 DVP0D10/ TVD10 DVP0D9 / TVD9 DVP0D8 / TVD8 DVP0D7 / TVD7 DVP0D6 / TVD6 DVP0D5 / TVD5 DVP0D4 / TVD4 DVP0D3 / TVD3 DVP0D2 / TVD2 DVP0D1 / TVD1 DVP0D0 / TVD0
M1 M3 M2 L1 M4 L3 L2 K1 L4 K3 K2 J1
O Digital Video Port 0 Data. Default output drive is 8 mA. 16 mA may be selected via SR3D[6]=1. NOTE: DVP0D[6:0] are also used for power-up reset straps for the embedded graphics controller. Check the Strap Pin table for details.
DVP0HS / TVHS N4 O Digital Video Port 0 Horizontal Sync. Internally pulled down.
DVP0VS / TVVS N3 O Digital Video Port 0 Vertical Sync. Internally pulled down. DVP0DE / TVDE N1 O Digital Video Port 0 Data Enable. Internally pulled down. DVP0DET / TVCLKR P4 I Digital Video Port 0 Display Detect. If VGA register
3C5.12[5]=0, 3C5.1A[5] will read 1 if display is connected. Tie to GND if not used.
DVP0CLK / TVCLK P3 O Digital Video Port 0 Clock. Internally pulled down. The terminology ie3C5.nnlg above refers to the VGA iGSequencerl. registers at I/O port 3C5 index “nn”
5.2 VIA K8N800 North Bridge(3)
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Dedicated Digital Video Port 0 (DVP0) - TV Encoder Interface Signal Name Pin # I/O Signal Description
TVD11 / DVP0D11 TVD10 / DVP0D10 TVD9 / DVP0D9 TVD8 / DVP0D8 TVD7 / DVP0D7 TVD6 / DVP0D6 TVD5 / DVP0D5 TVD4 / DVP0D4 TVD3 / DVP0D3 TVD2 / DVP0D2 TVD1 / DVP0D1 TVD0 / DVP0D0
M1 M3 M2 L1 M4 L3 L2 K1 L4 K3 K2 J1
O TV Encoder 0 Data. To configure DVP0 as a TV Out interface port, pins DVP0D[6:5] must be strapped high. Note: One TV Encoder interface is supported through either DVP0 or GDVP1.
TVHS / DVP0HS N4 O TV Encoder 0 Horizontal Sync. Internally pulled down. TVVS / DVP0VS N3 O TV Encoder 0 Vertical Sync. Internally pulled down. TVDE / DVP0DE N1 O TV Encoder 0 Display Enable. Internally pulled down. TVCLKR / DVP0DET P4 I TV Encoder 0 Clock Return. Input from TV encoder.
Internally pulled down.
TVCLK / DVP0CLK P3 O TV Encoder 0 Clock Out. Output to TV encoder. Internally pulled down.
The above pins may be connected to an external TV Encoder chip such as a VIA VT1622A or VT1622AM for driving a TV set. I/O pads for the pins on this page are powered by VCCGFX (3.3V I/O).
AGP-Multiplexed Digital Video Port 1 (GDVP1) – TMDS Interface Signal Name AGP Name Pin # I/O Signal Description
GDVP1D11 GDVP1D10 GDVP1D9 GDVP1D8 GDVP1D7 GDVP1D6 GDVP1D5 GDVP1D4 GDVP1D3 GDVP1D2 GDVP1D1 GDVP1D0
GC#BE3 GD26 GD24 GD30 GD28 GD29
GSBA4# GD27
GSBA5# GSBSTBS GSBSTBF GSBA2#
AC7AE6AF6AE4AF5AF4AF2AD5AD3AE1AF1AD1
O Data.
GDVP1HS GSBA3# AD2 O Horizontal Sync. GDVP1VS GSBA0# AC2 O Vertical Sync. GDVP1DE GSBA1# AC3 O Data Enable. GDVP1DET GD31 AD4 I Display Detect. If VGA register 3C5.3E[0] = 1,
3C5.1A[4] will read 1 if a display is connected. Tie to GND if not used.
GDVP1CLK GSBA6# AE3 O Clock. GDVP1CLK# GSBA7# AF3 O Clock Complement. The GDVP1 Digital Video Port is supported through multiplexing its interface signal pins with AGP pins. GDVP1 can be configured as either a TMDS transmitter interface port or a TV Encoder interface port. (see the TMDS Transmitter Interface and TV Encoder Interface pin lists below for details).
Analog Power / Ground
Signal Name Pin # I/O Signal Description VCCATX C22 P Analog Power for HT Transmit. 3.3V ±5%. Connect
through a ferrite bead for isolation of digital switching noise.GNDATX C21 P Analog Ground for HT Transmit. Connect to main ground
plane through a ferrite bead for isolation of digital switchingnoise.
VCCARX E25 P Analog Power for HT Receive. 3.3V ±5%. Connect through a ferrite bead for isolation of digital switching noise.
GNDARX E26 P Analog Ground for HT Receive. Connect to main ground plane through a ferrite bead for isolation of digital switching noise.
Reference Voltages
Signal Name Pin # I/O Signal Description VLVREF AF21 P V-Link Voltage Reference. 0.625V ±2% derived using a
resistive voltage divider (3K §Ù to 2.5V and 1K §Ù to ground). See Design Guide for details.
AGPVREF[1:0] AC6, AC13
P AGP Voltage Reference. 0.5 VCCQQ (0.75V) for AGP 2.0 (4x transfer mode) and 0.23 VCCQQ (0.35V) for AGP 3.0 (8x transfer mode). See the Design Guide for additional information and circuit implementation details..
5.2 VIA K8N800 North Bridge(4)
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AGP-Multiplexed Digital Video Port 1 (GDVP1) – TV Encoder Signal Name AGP Name Pin # I/O Signal Description
GTVD11 / GDVP1D11, GTVD10 / GDVP1D10, GTVD9 / GDVP1D9, GTVD8 / GDVP1D8, GTVD7 / GDVP1D7, GTVD6 / GDVP1D6, GTVD5 / GDVP1D5, GTVD4 / GDVP1D4, GTVD3 / GDVP1D3, GTVD2 / GDVP1D2, GTVD1 / GDVP1D1, GTVD0 / GDVP1D0
GC#BE3 GD26 GD24 GD30 GD28 GD29
GSBA4# GD27
GSBA5# GSBSTBS GSBSTBF GSBA2#
AC7 AE6 AF6 AE4 AF5 AF4 AF2 AD5 AD3 AE1 AF1 AD1
O Data.
GTVHS / GDVP1HS GSBA3# AD2 O Horizontal Sync. Internally pulled down. GTVVS / GDVP1VS GSBA0# AC2 O Vertical Sync. Internally pulled down. GTVDE / GDVP1DE GSBA1# AC3 O Display Enable. Internally pulled down. GTVCLKR / GDVP1DET
GD31 AD4 I Clock In. Input from TV encoder. Internally pulled down.
GTVCLK / GDVP1CLK
GSBA6# AE3 O Clock Out. Output to TV encoder. Internally pulled down.
GTVCLK# / GDVP1CLK#
GSBA7# AF3 O Clock Out Complement. Output to TV encoder. Internally pulled down.
The above pins may be connected to an external TV Encoder chip such as a VIA VT1623 or VT1623M for driving a TV set. I/O pads for the pins on this page are powered by VCC15AGP (1.5V I/O).
24-Bit / Dual 12-Bit Flat Panel Display Interface Signal Name AGP Name Pin # I/O Signal Description
FPD23 / FPD0D11, FPD22 / FPD0D10, FPD21 / FPD0D09, FPD20 / FPD0D08, FPD19 / FPD0D07, FPD18 / FPD0D06, FPD17 / FPD0D05, FPD16 / FPD0D04, FPD15 / FPD0D03, FPD14 / FPD0D02, FPD13 / FPD0D01, FPD12 / FPD0D00, FPD11 / FPD1D11, FPD10 / FPD1D10, FPD09 / FPD1D09, FPD08 / FPD1D08, FPD07 / FPD1D07, FPD06 / FPD1D06, FPD05 / FPD1D05, FPD04 / FPD1D04, FPD03 / FPD1D03, FPD02 / FPD1D02, FPD01 / FPD1D01, FPD00 / FPD1D00
GD11 GD13 GD14 GD15
GC#BE2GD16 GD17 GD18 GD23 GD20 GD22
GADSSTB1F
GD1 GD0 GD3 GD4 GD5 GD6 GD7
GADSTB0FGC#BE0
GADSTB0SGD10 GD12
AE13AD12AF12AE12AD11AD10AE10AF10AD8 AF9 AE9 AE7 AD18AF18AF17AD17AD16AE16AF16AE15AD15AF15AD13AF13
O Flat Panel Data. For 24-bit or dual 12-bit flat panel display modes. Two FPD interface modes, 24-bit and dual 12-bit, are supported. Strapping pin DVP0D4 is used to select the interface mode to the LVDS transmitter chip: Strap High (3C5.12[4]=1): 24-bit Strap Low (3C5.12[4]=0): Dual 12-bit In in24-bitl] mode, only one set of control pins is required. However, in dual 12-bit mode, the K8N800 Version CD provides two sets of control signals that are required for certain LVDS transmitter chips. In 24-bit mode, two operating modes are supported: 3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=0 Double data rate: each rising & falling clock edge transmits a complete 24-bit pixel 3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=1 Single data rate: each clock rising edge transmits a complete 24-bit pixel In dual 12-bit mode, 3C5.12[4]=0 & 3x5.88[2] = 1 Each rising and falling clock edge transmits half (12 bits) of two 24-bit pixels
FPHS GFRAME AC9 O Flat Panel Horizontal Sync. 24-bit mode or port 0 of dual 12-bit mode.
FPVS GDEVSEL AC11 O Flat Panel Vertical Sync. 24-bit mode or port 0 of dual 12-bit mode.
FPDE GD19 AD9 O Flat Panel Data Enable. 24-bit mode or port 0 of dual 12-bit mode
FPDET GADSTB1S AF7 I Flat Panel Detect. 24-bit mode or port 0 of dual 12-bit mode
FPCLK GD21 AF8 O Flat Panel Clock. 24-bit mode or port 0 of dual 12-bit mode
FPCLK# GWBF AC1 O Flat Panel Clock Complement. 24-bit mode or port 0 of dual 12-bit Mode.
Flat Panel Power Control (Muxed with AGP) Signal Name AGP Name Pin # I/O Signal Description
ENAVDD GST1 AA1 IO Enable Panel VDD Power. ENAVEE GST0 AA2 IO Enable Panel VEE Power. ENABLT GST2 AB1 IO Enable Panel Back Light. Note: I/O pads for all pins on this page are powered by VCC15AGP (i.e., 1.5V I/O).
5.2 VIA K8N800 North Bridge(5)
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24-Bit / Dual 12-Bit Flat Panel Display Interface (Continued) Signal Name AGP Name Pin # I/O Signal Description
FP1HS GD9 AD14 O Flat Panel Horizontal Sync. For port 1 in dual 12-bit mode.
FP1VS GPAR AC16 O Flat Panel Vertical Sync. For port 1 in dual 12-bit mode.
FP1DE GSERR AC15 O Flat Panel Data Enable. For port 1 in dual 12-bit mode.
FP1DET GD8 AF14 I Flat Panel Detect. For port 1 in dual 12-bit mode.
FP1CLK GD2 AE18 O Flat Panel Clock. For port 1 in dual 12-bit mode.
FP1CLK# GSTOP AC12 O Flat Panel Clock Complement. For port 1 in dual 12-bit mode.
Clock, Reset, Power Control, General Purpose I/O, Interrupts and Test
Signal Name Pin # I/O Signal Description GCLK A11 I AGP Clock. 66 MHz clock for AGP logic. DCLKI D7 I Dot Clock (Pixel Clock) In. For spread spectrum. DCLKO A7 O Dot Clock (Pixel Clock) Out. For spread spectrum. RESET# AD25 I Reset. Input from the South Bridge chip. 3.3V tolerant input.
When asserted, this signal resets the chip and sets all register bits to the default value. The rising edge of this signal is used to sample all power-up strap options In addition, HTRST# is driven active to reset the K8 CPU.
PWROK AE26 I Power OK. Driven by South Bridge PWROK output from the power supply PWRGOOD input to the South Bridge.
SUSST# AD26 I Suspend Status. For implementation of the Suspend-to-DRAM feature. Connect to an external pull-up to disable.
TESTIN AC26 I Test In. This pin is used for testing and must be left unconnected or tied high (4.7K §Ù to 2.5V) on all board designs.
BISTIN D3 I Built-In-Self-Test In. Reserved for test. Connect to GND for normal operation.
DEBUG AC17 I Debug. Reserved for test. Connect to ground for normal operation.
XIN C6 I Reference Frequency In. 14.31818 MHz. INTA# E7 O PCI Interrupt Output A. Connect to the South Bridge. GPOUT D2 O General Purpose Output. GPO0 N2 O General Purpose Output.
Compensation
Signal Name Pin # I/O Signal Description RPCOMP D25 AI Host CPU P-Channel Compensation. Connect 50 §Ù 1%
resistor to GND. RNCOMP D26 AI Host CPU N-Channel Compensation. Connect 50 §Ù 1%
resistor to VCCHT. RTCOMP C26 AI Host CPU Compensation. Connect 100 §Ù 1% resistor to
VCCHT. VLPCOMP AD19 AI V-Link P-Channel Compensation. Connect 360 §Ù 1%
resistor to ground. AGPNCOMP W1 AI AGP N-Channel Compensation. Connect 60.4 §Ù 1%
resistor to VCCAGP. AGPPCOMP V1 AI AGP P-Channel Compensation. Connect 60.4 §Ù 1%
resistor to GND.
5.2 VIA K8N800 North Bridge(6)
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Integrated Graphics Power and Ground Signal Name Pin # I/O Signal Description
VCCDAC B2 P DAC Voltage. 3.3V ±5% connected via ferrite bead for isolation of digital switching noise.
GNDDAC C3, D4 P DAC Ground. Connect to main ground plane. VCCRGB A4 P Power for CRT RGB Outputs. 3.3V ±5% connected via
ferrite bead for isolation of digital switching noise GNDRGB B4 P Connection point for RGB Load Resistors. Connect to main
ground plane via ferrite bead for isolation of digital switching noise.
VCCPLL1 D5 P Power for Graphics Controller PLL1 (“E-Clock”). 1.5V ±5% connected via ferrite bead for isolation of digital switching noise.
GNDPLL1 C5 P Ground for Graphics Controller PLL1 (“E-Clock”). Connect to main ground plane via ferrite bead for isolation of digital switching noise.
VCCPLL2 A5 P Power for Graphics Controller PLL2 (“D-Clock”). 1.5V ±5% connected via ferrite bead for isolation of digital switching noise.
GNDPLL2 B5 P Ground for Graphics Controller PLL2 (“D-Clock”). Connect to main ground plane via ferrite bead for isolation of digital switching noise.
VCCPLL3 A6 P Power for Graphics Controller PLL3 (“LCD Clock”). 1.5V ±5% connected via ferrite bead for isolation of digital switching noise.
GNDPLL3 B6 P Ground for Graphics Controller PLL3 (“LCD Clock”). Connect to main ground plane via ferrite bead for isolation of digital switching noise.
5.2 VIA K8N800 North Bridge(7)
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V-Link Interface Signal Name Pin # I/O Signal Description VD[7:0] (see pin
list) IO Data Bus. These pins are also used to send strap information to
the chipset north bridge. At power up, VD7 reflects the state of a strap on SDCS3#, VD[6:4] reflect the state of straps on pins SDA[2:0], and VD[3:0] reflect the state of straps on pins Strap_VD3-0. The specific interpretation of these straps is north bridge chip design dependent.
VPAR F24 IO Parity. If the VPAR function is implemented in a compatible manner on the north bridge, this pin should be connected to the north bridge VPAR pin (P4X333, P4X400, P4X800, KT400). If VPAR is not implemented in the north bridge chip or is incompatible with the 8235CE (4x V-Link north bridges) connect this pin to an 8.2K pullup to 2.5V (Pro266, Pro266T, KT266, KT266A, KT333, P4X266, PN266, KN266, KM266, P4M266, P4N266). See app note AN222 for details.
VBE# G24 IO Byte Enable. VCLK L22 I V-Link Clock. UPCMD K23 O Command from Client-to-Host. DNCMD K25 I Command from Host-to-Client. UPSTB J26 O Strobe from Client-to-Host. UPSTB# J24 O Complement Strobe from Client-to-Host. DNSTB K26 I Strobe from Host-to-Client. DNSTB# H24 I Complement Strobe from Host-to-Client.
CPU Interface Signal Name Pin # I/O Signal Description A20M# U26 OD A20 Mask. Connect to A20 mask input of the CPU to control
address bit-20 generation. Logical combination of the A20GATE input (from internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).
FERR# U24 I Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on the CPU. Internally generates interrupt 13 if active. Output voltage swing is programmable tot 1.5V or 2.5V by Device 17 Function 0 Rx67[2].
IGNNE# T24 OD Ignore Numeric Error. This pin is connected to the CPU iPignore errorlr pin.
INIT# R26 OD Initialization. The VT8235 Version CE asserts INIT# if it detects a shut-down special cycle on the PCI bus or if a soft reset is initiated by the register
INTR T25 OD CPU Interrupt. INTR is driven by the VT8235 Version CE to signal the CPU that an interrupt request is pending and needs service.
NMI T26 OD Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the CPU. The VT8235 Version CE generates an NMI when PCI bus SERR# is asserted.
SLP# V26 OD Sleep. Used to put the CPU to sleep. SMI# U25 OD System Management Interrupt. SMI# is asserted by the
VT8235 Version CE to the CPU in response to different Power-Management events.
STPCLK# R24 OD Stop Clock. STPCLK# is asserted by the VT8235 Version CE to the CPU to throttle the processor clock.
Note: Connect each of the above signals to 150 §Ù pullup resistors to VCC_CMOS (see Design Guide).
5.3 VIA VT8235CD South Bridge(1)
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Advanced Programmable Interrupt Controller (APIC) Interface Signal Name Pin # I/O Signal Description APICD1 T23 O Internal APIC Data 1. Function 0 Rx58[6] = 1 APICD0 R25 O Internal APIC Data 0. Function 0 Rx58[6] = 1 APICCLK U23 I APIC Clock.
CPU Speed Control Interface Signal Name Pin # I/O Signal Description VRDSLP / GPI29/ GPO29
AB9 OD Voltage Regulator Deep Sleep. Connected to the CPU voltage regulator. High selectsthe proper voltage for deep sleep mode. This pin performs the VRDPSLP function if Function 0 RxE5[3] = 0.
GHI# / GPI22/ GPO22
R22 OD CPU Speed Select. Connected to the CPU voltage regulator, used to select high speed (L) or low speed (H). This pin performs the GHI# function if Function 0 RxE5[3] = 0.
DPSLP# / GPI23/ GPO23
P21 OD CPU Deep Sleep. This pin performs the DPSLP# function if Device 17 Function 0RxE5[3]=0.
CPUMISS / GPI17
Y1 I CPU Missing. Used to detect the physical presence of the CPU chip in its socket. High indicates no CPU present. Connect to the CPUMISS pin of the CPU socket. The state of this pin may be read in the SMBus 2 registers. This pin may be used as CPUMISS and GPI17 at the same time.
AGPBZ# / GPI6 AD10 I AGP Busy. Low indicates that an AGP master cycle is in progress (CPU speed transitions will be postponed if this input is asserted low). Connected to the AGP Bus AGPBZ# pin.
PCI Bus Interface Signal Name Pin # I/O Signal Description AD[31:0] (see
pinlist)IO Address / Data Bus. Multiplexed address and data. The address
is driven with FRAME#assertion and data is driven or received in following cycles.
CBE[3:0]# M3, L4, C1, E2
IO Command / Byte Enable. The command is driven with FRAME# assertion. Byteenables corresponding to supplied or requested data are driven on following clocks.
DEVSEL# H2 IO Device Select. The VT8235 Version CE asserts this signal to claim PCI transactions through positive or subtractive decoding. As an input, DEVSEL# indicates the response to a VT8235 Version CE-initiated transaction and is also sampled when decoding whether to subtractively decode the cycle.
FRAME# J1 IO Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator.
IRDY# J2 IO Initiator Ready. Asserted when the initiator is ready for data transfer.
TRDY# H1 IO Target Ready. Asserted when the target is ready for data transfer.
STOP# K4 IO Stop. Asserted by the target to request the master to stop the current transaction.
SERR# C2 I System Error. SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the VT8235 Version CE can be programmed to generate an NMI to the CPU.
PERR# C3 _ Parity Error. PERR#, sustained tri-state, is only for the reporting of data parity errors during all PCI transactions except for a Special Cycle.
PAR F4 IO Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
5.3 VIA VT8235CD South Bridge(2)
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PCI Bus Interface (Continued) Signal Name Pin # I/O Signal Description INTA# INTB# INTC# INTD# INTE# / GPI12, / GPO12, INTF# / GPI13, / GPO13, INTG# / GPI14, / GPO14, INTH# / GPI15, / GPO15
A4 B4 B5 C4 D4 E4 A3 B3
I PCI Interrupt Request. The INTA# through INTD# pins are typically connected to thePCI bus INTA#-INTD# pins per the table below. INTE-H# are enabled by setting Device17, Function 0 Rx5B[1] = 1. BIOS settings must match the physical connection method.
INTA# INTB# INTC# INTD# PCI Slot 1 INTA# NTB# INTC# INTD# PCI Slot 2 INTB# INTC# INTD# INTE# PCI Slot 3 INTC# INTD# INTE# INTF# PCI Slot 4 INTD# INTE# INTF# INTG# PCI Slot 5 INTE# INTF# INTG# INTH# PCI Slot 6 INTF# INTG# INTH# INTA#
REQ5# / GPI7, REQ4#, REQ3#, REQ2#, REQ1#, REQ0#
R3 P3 D5 C5 B6 A5
I PCI Request. These signals connect to the VT8235 Version CE from each PCI slot (oreach PCI master) to request the PCI bus. To use pin R3 as REQ5#, Function 0 RxE4 mustbe set to 1 otherwise this pin will function as General Purpose Input 7.
GNT5# / GPO7, GNT4#, GNT3#, GNT2#, GNT1#, GNT0#
R2 R4 E5 C6 D6 A6
O PCI Grant. These signals are driven by the VT8235 Version CE to grant PCI access to aspecific PCI master. To use pin R2 as GNT5#, Function 0 RxE4 must be set to 1otherwise this pin will function as General Purpose Output 7.
PCIRST# R1 O PCI Reset. This signal is used to reset devices attached to the PCI bus.
PCICLK R23 I PCI Clock. This signal provides timing for all transactions on the PCI Bus.
PCKRUN# AB7 IO PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped (high) or running (low). The VT8235 Version CE drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping. Connect this pin to ground using a 100 §Ù resistor if the function is not used. Refer to the ihPCI Mobile Design Guidelo and applicable VIA North Bridge Design Guide (KT400A, CLE266, or P4X400) for more details.
LAN Controller - Media Independent Interface (MII) Signal Name Pin # I/O PU Signal Description
MCOL B11 I PD MII Collision Detect. From the external PHY. MCRS A11 I PD MII Carrier Sense. Asserted by the external PHY when
the media is active.
MDCK A7 O PD MII Management Data Clock. Sent to the external PHY as a timing reference for MDIO
MDIO B7 IO PD MII Management Data I/O. Read from the MDI bit or written to the MDO bit.
MRXCLK C9 I PD MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY.
MRXD[3-0] C7, A8, B8, C8
I PD MII Receive Data. Parallel receive data lines driven by the external PHY synchronous with MRXCLK.
MRXDV D8 I PD MII Receive Data Valid. MRXERR D10 I PD MII Receive Error. Asserted by the PHY when it detects a
data decoding error.
MTXCLK C10 I PD MII Transmit Clock. Always active 2.5 or 25 MHz clock supplied by the PHY.
MTXD[3-0] A9, B9, B10, A10
O PD MII Transmit Data. Parallel transmit data lines synchronized to MTXCLK.
MTXENA C11 O PD MII Transmit Enable. Signals that transmit is active from the MII port to the PHY.
MIIVCC D9, E9, E10, E11
Power MII Interface Power. 3.3V ±5%.
MIIVCC25 D12, E12
Power MII Suspend Power. 2.5V ±5%.
RAMVCC E7 Power Power For Internal LAN RAM. 2.5V ±5%. RAMGND E6 Power Ground For Internal LAN RAM.
5.3 VIA VT8235CD South Bridge(3)
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Serial EEPROM Interface Signal Name Pin # I/O PU Signal Description EECS# D11 O Serial EEPROM Chip Select. EECK C12 O Serial EEPROM Clock. EEDO B12 I Serial EEPROM Data Output. Connect to EEPROM Data
Out pin. EEDI A12 O Serial EEPROM Data Input. Connect to EEPROM Data
In pin.
Low Pin Count (LPC) Interface Signal Name Pin # I/O PU Signal Description
LFRM# AF6 IO LPC Frame. LREQ# AE6 IO LPC DMA / Bus Master Request. LAD[3-0] AD7,
AE7, AF7, AD8
IO PU LPC Address / Data.
Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#
Universal Serial Bus 2.0 Interface Signal Name Pin # I/O Signal Description USBP0+ E20 IO USB 2.0 Port 0 Data + USBP0Œ D20 IO USB 2.0 Port 0 Data Œ USBP1+ A20 IO USB 2.0 Port 1 Data + USBP1Œ B20 IO USB 2.0 Port 1 Data Œ USBP2+ E18 IO USB 2.0 Port 2 Data + USBP2Œ D18 IO USB 2.0 Port 2 Data Œ USBP3+ A18 IO USB 2.0 Port 3 Data + USBP3Œ B18 IO USB 2.0 Port 3 Data Œ USBP4+ D16 IO USB 2.0 Port 4 Data + USBP4Œ E16 IO USB 2.0 Port 4 Data Œ USBP5+ A16 IO USB 2.0 Port 5 Data + USBP5Œ B16 IO USB 2.0 Port 5 Data Œ USBCLK E23 I USB 2.0 Clock. 48MHz clock input for the USB interface USBOC0# C26 I USB 2.0 Port 0 Over Current Detect. Port 0 is disabled if low. USBOC1# D24 I USB 2.0 Port 1 Over Current Detect. Port 1 is disabled if low. USBOC2# B26 I USB 2.0 Port 2 Over Current Detect. Port 2 is disabled if low. USBOC3# C25 I USB 2.0 Port 3 Over Current Detect. Port 3 is disabled if low. USBOC4# B24 I USB 2.0 Port 4 Over Current Detect. Port 4 is disabled if low. USBOC5# A24 I USB 2.0 Port 5 Over Current Detect. Port 5 is disabled if low. USBVCC (see pin
list) Power
USB 2.0 Port Differential Output Interface Logic Voltage. 3.3V
USBGND (see pin list)
Power
USB 2.0 Port Differential Output Interface Logic Ground.
VSUSUSB C24 Power
USB 2.0 Suspend Power. 2.5V ±5%.
VCCUPLL A23, B23
Power
USB 2.0 PLL Analog Voltage. 2.5V ±5%.
GNDUPLL C23, D23
Power
USB 2.0 PLL Analog Ground.
System Management Bus (SMB) Interface (I 2 C Bus) Signal Name Pin # I/O Signal Description SMBCK1 AC4 IO SMB / I 2 C Channel 1 Clock. SMBCK2 / GPI27 / GPO27
AC3 IO SMB / I 2 C Channel 2 Clock. Rx95[2] = 0
SMBDT1 AB2 IO SMB / I 2 C Channel 1 Data. SMBDT2 / GPI26 / GPO26
AD1 IO SMB / I 2 C Channel 2 Data. Rx95[2] = 0
SMBALRT# AB1 I SMB Alert. (enabled by System Management Bus I/O space Rx08[3] = 1) When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event. Connect to a 10K ohm pullup to VSUS33 if not used.
5.3 VIA VT8235CD South Bridge(4)
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UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface Signal Name Pin # I/O Signal Description PDRDY /PDDMARDY /PDSTROBE
Y22 I EIDE Mode: Primary I/O Channel Ready. Device ready indicator UltraDMA Mode: Primary Device DMA Ready. Output flow control. The device mayassert DDMARDY to pause output transfers Primary Device Strobe. Input data strobe (both edges). The device may stop DSTROBE to pause input data transfers
SDRDY /SDDMARDY /SDSTROBE
AF17 I EIDE Mode: Secondary I/O Channel Ready. Device ready indicator UltraDMA Mode: Secondary Device DMA Ready. Output flow control. The devicemay assert DDMARDY to pause output transfers Secondary Device Strobe. Input data strobe (both edges). The device may stop DSTROBE to pause input data transfers
PDIOR# /PHDMARDY /PHSTROBE
W26 O EIDE Mode: Primary Device I/O Read. Device read strobe UltraDMA Mode: Primary Host DMA Ready. Primary channel input flow control. Thehost may assert HDMARDY to pause input transfers Primary Host Strobe. Output data strobe (both edges). The host may stop HSTROBE to pause output data transfers
SDIOR# /SHDMARDY /SHSTROBE
AF23 O EIDE Mode: Secondary Device I/O Read. Device read strobe UltraDMA Mode: Secondary Host DMA Ready. Input flow control. The host mayassert HDMARDY to pause input transfers Host Strobe B. Output strobe (both edges). The host may stop HSTROBE to pause output data transfers
PDIOW# /PSTOP
Y25 O EIDE Mode: Primary Device I/O Write. Device write strobe UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred inan UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst.
SDIOW# /SSTOP
AE23 O EIDE Mode: Secondary Device I/O Write. Device write strobe UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst.
PDDRQ Y23 I Primary Device DMA Request. Primary channel DMA request SDDRQ AD17 I Secondary Device DMA Request. Secondary channel DMA
request
UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface (Continued) Signal Name Pin # I/O Signal Description PDDACK# Y24 O Primary Device DMA Acknowledge. Primary channel DMA
acknowledge SDDACK# AD23 O Secondary Device DMA Acknowledge. Secondary channel DMA
acknowledge IRQ14 AD24 I Primary Channel Interrupt Request. IRQ15 AE26 I Secondary Channel Interrupt Request. PDCS1# V22 O Primary Master Chip Select. This signal corresponds to CS1FX#
on the primary IDE connector. PDCS3# V23 O Primary Slave Chip Select. This signal corresponds to CS3FX# on
the primary IDE connector. SDCS1# / strap AF25 O Secondary Master Chip Select. This signal corresponds to
CS17X# on the secondary IDE connector. Strap low (resistor to ground) to enable serial EEPROM interface via the MII bus (this disables the EExx pins). This pin has an internal pullup to default to serial EEPROM interface via the EExx pins.
SDCS3# / strap AF26 O Secondary Slave Chip Select. This signal corresponds to CS37X# on the secondary IDE connector. Strap information is communicated to the north bridge via VD[7].
PDA[2-0] W24, V25, W23
O Primary Disk Address. PDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed.
SDA[2-0] / strap AE24, AC22, AF24
O Secondary Disk Address. SDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. Strap information is communicated to the north bridge via VD[6:4].
PDD[15-0] (see pin list)
IO Primary Disk Data.
SDD[15-0] (see pin list)
IO Secondary Disk Data.
Serial IRQ Signal Name Pin # I/O Signal Description SERIRQ AD9 I Serial IRQ. This pin has an internal pull-up resistor.
5.3 VIA VT8235CD South Bridge(5)
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AC97 Audio / Modem Interface Signal Name Pin # I/O Signal Description ACRST# T3 O AC97 Reset. ACBTCK T1 I AC97 Bit Clock. ACSYNC T2 O AC97 Sync. ACSDO U2 O AC97 Serial Data Out. ACSDIN0 (VSUS33)ƒ
U3 I AC97 Serial Data In 0.
ACSDIN1 (VSUS33)ƒ
V2 I AC97 Serial Data In 1.
ACSDIN2 / GPIO20 / PCS0#
U1 I AC97 Serial Data In 2. RxE4[6]=0,E5[1]=0, PMIO Rx4C[20]=1
ACSDIN3 / GPIO21 / PCS1# / SLPBTN#
V3 I AC97 Serial Data In 3. RxE4[6]=0,E5[2]=0, PMIO Rx4C[21]=1
Internal Keyboard Controller Signal Name Pin # I/O PU Signal Description
MSCK / IRQ1 W1 IO / I PU MultiFunction Pin (Internal mouse controller enabled by Rx51[1]) Rx51[2]=1 Mouse Clock. From internal mouse controller. Rx51[2]=0 Interrupt Request 1. Interrupt input 1.
MSDT / IRQ12 W2 IO / I PU MultiFunction Pin (Internal mouse controller enabled by Rx51[1]) Rx51[2]=1 Mouse Data. From internal mouse controller. Rx51[2]=0 Interrupt Request 12. Interrupt input 12.
KBCK / KA20G W3 IO / I PU MultiFunction Pin (Internal keyboard controller enabled by Rx51[0]) Rx51[0]=1 Keyboard Clock. From internal keyboard controller Rx51[0]=0 Gate A20. Input from external keyboard controller.
KBDT / KBRC V1 IO / I PU MultiFunction Pin (Internal keyboard controller enabled by Rx51[0]) Rx51[0]=1 Keyboard Data. From internal keyboard controller. Rx51[0]=0 Keyboard Reset. From external keyboard controller (KBC) for CPURST# generation
KBCS# / strap AF10 O Keyboard Chip Select (Rx51[0]=0). To external keyboard controller chip. Strap high to enable LPC BIOS ROM.
Note: KBCK, KBDT, MSCK, and MSDT are powered by the VSUS33 suspend voltage plane.
Speaker Signal Name Pin # I/O PU Signal Description SPKR / strap AF8 O Speaker. Strap low to enable (high to disable) CPU
frequency strapping.
Resets, Clocks, and Power Status Signal Name Pin # I/O Signal Description PWRGD AC5 I Power Good. Connected to the Power Good signal on the
Power Supply. Internal logic powered by VBAT.
PWROK# AF1 O Power OK. Internal logic powered by VSUS33. PCIRST# R1 O PCI Reset. Active low reset signal for the PCI bus. The
VT8235 Version CE will assert this pin during power-up or from the control register.
OSC AB8 I Oscillator. 14.31818 MHz clock signal used by the internal Timer.
RTCX1 AE4 I RTC Crystal Input: 32.768 KHz crystal or oscillator input. This input is used for the internal RTC and power-well power management logic and is powered by VBAT.
RTCX2 AF3 O RTC Crystal Output: 32.768 KHz crystal output. Internal logic powered by VBAT.
TEST AE9 I Test. TPO AF9 O Test Pin Output. Output pin for test mode. NC (see pin
list) – No Connect. Do not connect.
5.3 VIA VT8235CD South Bridge(6)
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General Purpose Inputs Signal Name Pin # I/O Signal Description GPI0 (VBAT) AE2 I General Purpose Input 0. Status on PMIO Rx20[0] GPI1 (VSUS33) AC2 I General Purpose Input 1. Status on PMIO Rx20[1] GPI2 / EXTSMI#
(VSUS33) AA1 I General Purpose Input 2. Status on PMIO Rx20[4]
GPI3 / RING# (VSUS33)
Y2 I General Purpose Input 3. Status on PMIO Rx20[8]
GPI4 / LID# (VSUS33)
AC1 I General Purpose Input 4. Status on PMIO Rx20[11]
GPI5 / BATLOW# (VSUS33)
V4 I General Purpose Input 5. Status on PMIO Rx20[12]
GPI6 / AGPBZ# AD10 I General Purpose Input 6. Status on PMIO Rx20[5] GPI7 / REQ5# R3 I General Purpose Input 7. RxE4[2] = 0
GPI12 / GPO12 / INTE#
D4 I General Purpose Input 12. RxE4[4] = 0, 5B[1]=0
GPI13 / GPO13 / INTF#
E4 I General Purpose Input 13. RxE4[4] = 0, 5B[1]=0
GPI14 / GPO14 / INTG#
A3 I General Purpose Input 14. RxE4[4] = 0, 5B[1]=0
GPI15 / GPO15 / INTH#
B3 I General Purpose Input 15. RxE4[4] = 0, 5B[1]=0
GPI16 / INTRUDER#
(VBAT)
AE1 I General Purpose Input 16. Status on PMIO Rx20[6]
GPI17 / CPUMISS
Y1 I General Purpose Input 17. Status on PMIO Rx20[5]
GPI18 / THRM# / AOLGPI
Y4 I General Purpose Input 18. Rx8C[3] = 0
GPI20 / GPO20 / ACSDIN2 /
PCS0#
U1 I General Purpose Input 20. RxE4[6]=1, E5[1]=0, PMIO 4C[20] = 1
GPI21 / GPO21 / ACSDIN3 /
PCS1# / SLPBTN#
V3 I General Purpose Input 21. RxE4[6]=1, E5[2]=0 PMIO 4C[21] = 1
GPI22 / GPO22 / GHI#
R22 I General Purpose Input 22. RxE5[3] = 1, PMIO 4C[22] = 1
GPI23 / GPO23 / DPSLP#
P21 I General Purpose Input 23. RxE5[3] = 1, PMIO 4C[23] = 1
General Purpose Inputs (Continued) Signal Name Pin # I/O Signal Description GPI26 / GPO26 /
SMBDT2 (VSUS33)
AD1 I General Purpose Input 26. Rx95[2] = 1, 95[3] = 0
GPI27 / GPO27 / SMBCK2 (VSUS33)
AC3 I General Purpose Input 27. Rx95[2] = 1, 95[3] = 0
GPI28 / GPO28 AC8 I General Purpose Input 28. RxE5[3] = 1, PMIO 4C[28] = 1
GPI29 / GPO29 / VRDSLP
AB9 I General Purpose Input 29. RxE5[3] = 1, PMIO 4C[29] = 1
Note: Register references above are Device 17 Function 0 unless indicated otherwise. Note: Default pin function is underlined in the signal name column above. Note: Input pin status for the above GPI pins 31-0 is also available on PMIO Rx4B-48[31-0] Note: See also Power Management I/O register Rx50 for input pin change status for GPI16-19 and 24-27 Note: See also Power Management I/O register Rx52 for SCI/SMI select for GPI16-19 and 24-27 Note: See also Power Management I/O register Rx4C. General purpose input pins 20-31 are shared with OD (open drain) general
Programmable Chip Selects Signal Name Pin # I/O Signal Description PCS0# / GPIO20 / ACSDIN2
U1 O Programmable Chip Select 0. RxE4[6]=1, E5[1]=1
PCS1# / GPIO21 / ACSDIN3 / SLPBTN#
V3 O Programmable Chip Select 1. RxE4[6]=1, E5[2]=1
5.3 VIA VT8235CD South Bridge(7)
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General Purpose Outputs Signal Name Pin # I/O Signal Description GPO0 (VSUS33) AA3 O General Purpose Output 0. GPO1 / SUSA#
(VSUS33) AA2 O General Purpose Output 1. Rx94[2] = 1
GPO2 / SUSB# (VSUS33)
AD3 O General Purpose Output 2. Rx94[3] = 1
GPO3 / SUSST1# (VSUS33)
Y3 O General Purpose Output 3. Rx94[4] = 1
GPO4 / SUSCLK (VSUS33)
AB3 O General Purpose Output 4. Rx95[1] = 1
GPO5 / CPUSTP#
AC7 O General Purpose Output 5. RxE4[0] = 1
GPO6 / PCISTP# AD6 O General Purpose Output 6. RxE4[1] = 1 GPO7 / GNT5# R2 O General Purpose Output 7. RxE4[2] = 0
GPO12 / GPI12 / INTE#
D4 O General Purpose Output 12. RxE4[4]=1, 5B[1]=0
GPO13 / GPI13 / INTF#
E4 O General Purpose Output 13. RxE4[4]=1, 5B[1]=0
GPO14 / GPI14 / INTG#
A3 O General Purpose Output 14. RxE4[4]=1, 5B[1]=0
GPO15 / GPI15 / INTH#
B3 O General Purpose Output 15. RxE4[4]=1, 5B[1]=0
GPO20 / GPI20 / ACSDIN2 /
PCS0#
U1 OD General Purpose Output 20. RxE4[6]=1, E5[1]=0
GPO21 / GPI21 / ACSDIN3 /
PCS1# /SLPBTN#
V3 OD General Purpose Output 21. RxE4[6]=1, E5[2]=0
GPO22 / GPI22 / GHI#
R22 OD General Purpose Output 22. RxE5[3]=1, PMIO 4C[22]=1
GPO23 / GPI23 / DPSLP#
P21 OD General Purpose Output 23. RxE5[3]=1, PMIO 4C[23]=1
GPO26 / GPI26 / SMBDT2
(VSUS33ƒ)
AD1 OD General Purpose Output 26. Rx95[2] = 1, 95[3] = 1
GPO27 / GPI27 / SMBCK2
(VSUS33ƒ)
AC3 OD General Purpose Output 27. Rx95[2] = 1, 95[3] = 1
General Purpose Outputs (Continued) Signal Name Pin # I/O Signal Description GPO28 / GPI28 AC8 OD General Purpose Output 28. RxE5[3] = 1, PMIO 4C[28]=1
GPO29 / GPI29 / VRDSLP
AB9 OD General Purpose Output 29. RxE5[3] = 1, PMIO 4C[29]=1
Note: The output state for each of the above general purpose outputs is selectable via Power Management I/O registers Rx4C-48 Note: Default pin functions are underlined in the table above.
Power Management and Event Detection Signal Name Pin # I/O Signal Description PWRBTN# AD2 I Power Button. Used by the Power Management subsystem
to monitor an external system on/off button or switch. Internal logic powered by VSUS33.
SLPBTN# / GPIO21/ ACSDIN3 / PCS1#
V3 I Sleep Button. Used by the Power Management subsystem to monitor an external sleepbutton or switch. RxE4[6] = 1, 80[6] = 1, E5[2] = 0 and PMIO Rx4C[21] = 1
RSMRST# AD4 I Resume Reset. Resets the internal logic connected to the VSUS33 power plane and also resets portions of the internal RTC logic. Internal logic powered by VBAT.
EXTSMI# / GPI2
AA1 IOD External System Management Interrupt. When enabled to allow it, a falling edge on this input causes an SMI# to be generated to the CPU to enter SMI mode. (10K PU to VSUS33 if not used) (3.3V only)
PME# W4 I Power Management Event. (10K PU to VSUS33 if not used)
SMBALRT# AB1 I SMB Alert. When programmed to allow it (SMB I/O Rx8[3]=1), assertion generates an IRQ, SMI, or power management event. (10K PU to VSUS33 if not used)
5.3 VIA VT8235CD South Bridge(8)
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Power Management and Event Detection (Continued) Signal Name Pin # I/O Signal Description LID# / GPI4 AC1 I Notebook Computer Display Lid Open / Closed
Monitor. Used by the Power Management subsystem to monitor the opening and closing of the display lid of notebook computers. Can be used to detect either low-to-high or high-to-low transitions to generate an SMI#. (10K PU to VSUS33 if not used)
INTRUDER# / GPI16
AE1 I Intrusion Indicator. The value of this bit may be read at PMIO Rx20[6]
THRM# / GPI18/ AOLGPI
Y4 I Thermal Alarm Monitor. Rx8C[3] = 1. Rising or falling edges (selectable by PMIORx2C[6]) may be detected to set status at PMIO Rx20[10]. Setting of this status bit may then be used to generate an SCI or SMI. THRM# may also be used to enable duty cycle control of stop-clock (STPCLK#) to automatically limit maximum temperature (see Device 17 Function 0 Rx8C[7-4]).
RING# / GPI3 Y2 I Ring Indicator. May be connected to external modem circuitry to allow the system to be re-activated by a received phone call. (10K PU to VSUS33 if not used)
BATLOW# / GPI5
V4 I Battery Low Indicator. (10K PU to VSUS33 if not used) (3.3V only)
CPUSTP# / GPO5
AC7 O CPU Clock Stop (RxE4[0] = 0). Signals the system clock generator to disable the CPU clock outputs. Not connected if not used.
PCISTP# / GPO6
AD6 O PCI Clock Stop (RxE4[1] = 0). Signals the system clock generator to disable the PCI clock outputs. Not connected if not used.
SUSA# / GPO1 AA2 O Suspend Plane A Control (Rx94[2]=0). Asserted during power management POS, STR, and STD suspend states. Used to control the primary power plane. (10K PU to VSUS33 if not used)
SUSB# / GPO2 AD3 O Suspend Plane B Control (Rx94[3]=0). Asserted during power management STR and STD suspend states. Used to control the secondary power plane. (10K PU to VSUS33 if not used)
SUSC# AF2 O Suspend Plane C Control. Asserted during power management STD suspend state. Used to control the tertiary power plane. Also connected to ATX power-on circuitry. (10K PU to VSUS33 if not used)
Power Management and Event Detection (Continued) Signal Name Pin # I/O Signal Description SUSST1# / GPO3
Y3 O Suspend Status 1 (Rx94[4] = 0). Typically connected to the North Bridge to provide information on host clock status. Asserted when the system may stop the host clock, such as Stop Clock or during POS, STR, or STD suspend states. Connect 10K PU to VSUS33.
SUSCLK AB3 O Suspend Clock. 32.768 KHz output clock for use by the North Bridge (e.g., KT400A, CLE266, or P4X400) for DRAM refresh purposes. Stopped during Suspend-to-Disk and Soft-Off modes. Connect 10K PU to VSUS33.
CPUMISS / GPI17
Y1 I CPU Missing. Used to detect the physical presence of the CPU chip in its socket. High indicates no CPU present. Connect to the CPUMISS pin of the CPU socket. The state of this pin may be read in the SMBus 2 registers. This pin may be used as CPUMISS and GPI17 at the same time.
AOLGPI / GPI18/ THRM#
Y4 I Alert On LAN. The state of this pin may be read in the SMBus 2 registers. This pinmay be used as AOLGPI, GPI18 and THRM# all at the same time.
Strap Pins for VT8235 Version CE Configuration Signal Name Pin # Function Description Note Strap_AUTO AE10 Auto
Reboot L: Enable Auto Reboot
H: Disable Auto Reboot (Default)
SPKR AF8 CPU Frequency Strapping
L: Enable CPU Frequency Strapping H: Disable CPU Frequency Strapping (Default)
KBCS# AF10 Internal Keyboard
Controller
L: Disable internal KBC H: Enable internal KBC (Default)
SDCS1# AF25 Eliminate External LAN EEPROM
L: Enable. Use external EEPROM (Default) H: Disable. Do not use external EEPROM
5.3 VIA VT8235CD South Bridge(9)
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Power and Ground Signal Name Pin # I/O Signal Description VSUS33 AA4,
AB4-6 P Suspend Power. 3.3V ±5%. Always available unless the
mechanical switch of the power supply is turned off. If the ihsoft-offlÉD state is not implemented, then this pin can beconnected to VCC33. Signals powered by or referenced to this plane are: PWRGD, RSMRST#, PWRBTN#, SMBCK1/2, SMBDT1/2, GPO0, SUSA# / GPO1, SUSB# /GPO2, SUSC#, SUSST1# / GPO3, SUSCLK / GPO4, GPI1, GPI2 / EXTSMI#, GPI3 / RING#, GPI4 / LID, GPI5 / BATLOW#, GPI6 / PME#, SMBALRT#
VSUS25 T4, U4 P Suspend Power. 2.5V ±5%. VSUSUSB C24 P USB Suspend Power. 2.5V ±5%. VBAT AF4 P RTC Battery. Battery input for internal RTC (RTCX1,
RTCX2) VLVREF H22 P V-Link Voltage Reference. 0.9V ±5% for 4x transfers and
0.625V ±5% for 8x transfers. VLCOMP J22 AI V-Link Compensation. VCCVK (see pin
list) P V-Link Compensation Circuit Voltage. 2.5V ±5%
MIIVCC D9, E9-11
P LAN MII Power. 3.3V ±5%.Power for LAN Media Independent Interface (interface to external PHY). Connect to VCC33 through a ferrite bead.
MIIVCC25 D12. E12
P LAN MII Suspend Power. 2.5V ±5%.
LANVCC E7 P LAN Power. 2.5V ±5%. Power for LAN. Connect to VCC through a ferrite bead.
LANGND E6 P LAN Ground. Connect to GND through a ferrite bead. USBVCC (see pin
list) P USB 2.0 Differential Output Power. 3.3V ±5%. Power
for USB differential outputs (USBP0+, P0Œ, P1+, P1Œ, P2+, P2Œ, P3+, P3Œ, P4+, P4Œ, P5+, P5Œ). Connect to VSUS33 through a ferrite bead.
USBGND (see pin list)
P USB 2.0 Differential Output Ground. Connect to GND through a ferrite bead.
VCCUPLL A23, B23
P USB 2.0 PLL Analog Voltage. 2.5V ±5%. Connect to VCC through a ferrite bead.
GNDUPLL C23, D23
P USB 2.0 PLL Analog Ground. Connect to GND through a ferrite bead.
PLLVCC T22 P PLL Analog Power. 2.5V ±5%. Connect to VCC through a ferrite bead.
PLLGND U22 P PLL Analog Ground. Connect to GND through a ferrite bead.
Strap Pins for North Bridge Configuration Signal Name Pin # Function Description Note SDCS3# AF26 NB
Configuration
SDCS3# signal state is reflected on signal pinVD[7] during power up for North Bridgeconfiguration.
Check the NorthBridge DS fordetails
SDA2 AE24 NB Configuration
SDA2 signal state is reflected on signal pinVD[6] during power up for North Bridgeconfiguration.
Check the NorthBridge DS fordetails
SDA1 AC22 NB Configuration
SDA1 signal state is reflected on signal pinVD[5] during power up for North Bridgeconfiguration.
Check the NorthBridge DS fordetails
SDA0 AF24 NB Configuration
SDA0 signal states is reflected on signal pinsVD[4] during power up for North Bridgeconfiguration.
Check the NorthBridge DS fordetails
Strap_VD3 AC6 NB Configuration
Strap_VD3 signal state is reflected on signal pinVD[3] during power up for North Bridgeconfiguration.
Check the NorthBridge DS fordetails
Strap_VD2 AD5 NB Configuration
Strap_VD2 signal state is reflected on signal pinVD[2] during power up for North Bridgeconfiguration.
Check the NorthBridge DS fordetails
Strap_VD1 AE5 NB Configuration
Strap_VD1 signal state is reflected on signal pin, VD[1] during power up for North Bridge configuration.
Check the North Bridge DS for details
Strap_VD0 AF5 NB Configuration
Strap_VD0 signal state is reflected on signalpin, VD[0] during power up for North Bridgeconfiguration.
Check the NorthBridge DS fordetails
Note: Internal Pullups are present on pins KBCK, KBDT, MSCK, MSDT, SERIRQ, LAD[3:0] Internal Pulldowns are present on all LAN pins
Power and Ground((((Continued)))) Signal Name Pin # I/O Signal Description VCC33 (see pin
list) P I/O Power. 3.3V ±5%
VCC (see pin list)
P Core Power. 2.5V ±5%. This supply is turned on only when the mechanical switch on the power supply is turned on and the PWRON signal is conditioned high.
GND (see pin list)
P Ground. Connect to primary motherboard ground plane.
5.3 VIA VT8235CD South Bridge(10)
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U6AMD
CLAWHAMMER
U12
North Bridge
K8N800
Internal KB
Touch PadU16KBC
W83L950D
U10AudioCodec
VT1617A
PCI BUS
LPC BUS
J16&J17DIMM-SLOT
U13
AmplifierG1428
U25FWHBIOS
HDD
USB2.0 X6
CD-ROM
U20
South Bridge
VT8235
MDC RJ11
FAN
U26PCMCIAControllerCBI1410
Internal Speaker
Card Bus Socket
J502
HP Jack
U2LAN PHYVT6103L
LCDLCD
CRTRGB
TV
HostBus
V-link
AC Link
Mini PCI Card Socket
J22 U3
InternalMIC
MICJack
ISA BUS
6. System Block Diagram
MII
TVEncoder
U9LVDS
Encoder
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7.1 Introduction
Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can alert you to the problems of your computer.If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs before the display is initialized, then the screen cannot display the error message. Error codes or system beeps are used to identify a post error that occurs when the screen is not available.
The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can determine where the problem occurred by reading the last value written to the port by the debug card plug at MINI PCI slot.
7. Maintenance Diagnostics
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The Mini PCI DOG killer card is a single-step debug tool which utilizes Mini PCI interface (Type III A) and is able to hold a PCI bus cycle so that address, data and control bus states on PCI bus can be inspected. Especially, the tool can help an engineer trace address/data bus for BIOS read cycles as soon as power on and debug open or short circuit problems easily. Usually, this sort of problem will make a PC motherboard fail to boot.
P/N:411906900001Description: PWA-MPDOG;MINI PCI DOGKELLER CARDNote: Order it from MIC/TSSC
7.2 Diagnostic Tool for Mini PCI Slot
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Following is a list of error codes in sequent display on the debug board.
POST (HEX) DESCRIPTION 10H Some Type Of Long Reset 11H Turn off FASTA20 for POST 12H Signal Power On Reset 13H Initialize the Chipset 14H Search For ISA Bus VGA Adapter 15H Reset Counter/Timer 1 16H user register configure through CMOS17H Size Memory 18H Dispatch To RAM Test 19H checksum the ROM 1AH Reset PIC's 1BH Initialize Video Adapter(s) 1CH Initialize Video (6845 Regs) 1DH Initialize Color Adapter 1EH Initialize Monochrome Adapter 1FH Test 8237A Page Registers 20H Test Keyboard 21H Test Keyboard Controller 22H Check If CMOS Ram Valid 23H Test Battery Fail & CMOS X-SUM 24H Test the DMA controllers 25H Initialize 8237A Controller 26H Initialize Int Vectors
POST (HEX) DESCRIPTION 27H RAM Quick Sizing 28H Protected mode entered safely 29H RAM test completed 2AH Protected mode exit successful 2BH Setup Shadow 2CH Going To Initialize Video 2DH Search For Monochrome Adapter 2EH Search For Color Adapter 2FH Signon messages displayed 30H special init of keyboard ctrl 31H Test If Keyboard Present 32H Test Keyboard Interrupt 33H Test Keyboard Command Byte 34H TEST, Blank and count all RAM 35H Protected mode entered safely (2). 36H RAM test complete 37H Protected mode exit successful 38H Update OUTPUT port 39H Setup Cache Controller 3AH Test If 18.2Hz Periodic Working 3BH test for RTC ticking 3CH initialize the hardware vectors 3DH Search and Init the Mouse
7.3 Error Codes-1
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Following is a list of error codes in sequent display on the debug board.
POST (HEX) DESCRIPTION 3EH Update NUMLOCK status 3FH special init of COMM and LPT ports 40H Configure the COMM and LPT ports 41H Initialize the floppies 42H Initialize the hard disk 43H Initialize option ROMs 44H OEM's init of power management 45H Update NUMLOCK status 46H Test For Coprocessor Installed 47H OEM functions before boot 48H Dispatch To Op. Sys. Boot 49H Jump Into Bootstrap Code
7.3 Error Codes-2
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8.2 No Power
8.3 Battery Can not Be Charged
8.4 No Display
8.5 External Monitor No Display
8.6 Memory Test Error
8.7 Keyboard/Touch Pad Test Error
8.9 Hard Disk Driver Test Error
8.10 CD-ROM Driver Test Error
8.8 USB Port Test Error
8.11 Audio Failure
8.12 LAN Test Error
8.13 Modem Test Error
8.14 Mini PCI Test Error
8.15 CardBus & Reader Test Error
8.16 TV Encoder Test Error
8. Trouble Shooting
8.1 Base Work Condition
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P23
Power InPJ1
PWR_VDDINPF1,PL1 PD5
PR4PU1PR3PQ1
ADINP DVMAIN
PD6
PD3
BATT
PF2PL19PQ23PQ24PQ25
PR76PQ14PQ15
P23
P23P23
P24
JS5
PL9,PL10,PQ4+VCC_CORE
P25
+5VSU17
+2.5VS
+5VU35
+5V_PPL15,PR74 JO10 P20P26 R168
+NB_VCCSUSP20
+AVDDADL47
+5V_AMPL52
+3VS+3V_PPU15
P26JO7
P20
L65+3VS_USB
P8
+2.5VS_DDRJO526JS3,PL12,PR49,PU11
+2.5V_PP20P21
PL11,PR53+1.25V_DDR_P
P21
+1.25VTTP20JO5,JO6
(To Next Page)
P18
P18
P20 P6
JO11,JO12PU16,PU17
PL5,PR1
+3VS_LANL33 L32
+3VS_LAN_PLLP16 P16
JO8,JO9PL13,PR73PL14,PU14
PU13,PJL1
JO527,JO528PR51,PU10,PU12,PL7
PQ7,PL3,PL4PU5,PU6,PU7
PL20PL18PD14PU19
Discharge
System Voltage Check
U19PWRIN1
F5+SVDD3
D17+VCC_RTC
+VDD3Q15,Q16
+KBC_VDDAL60
P20
P10
P19
Q36Q31
P20
R408,Q41
+3VR296
P20
Q28,U21(To Next Page)
P20
8.1 Base Work Condition(1)
+KBC_VREFR435
Q12
P20
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System Voltage Check
+1.5V_VCCAGPL502
+1.5V_NB
+1.5VPLL1
L503
L504+1.5V_VCCVL
+1.5VPLL2
L2
L3
P6
P6
P6
P6
P6
+2.5VS_DDRP20
PU4
PL2,PU3
+1.5V_PP22
PU2+1.2V_P
P22
+1.2VLDTAJO1,JO2 P20
+1.5VJO3,JO4
+1.25VSREF_MEMR235,C237,R261
+1.25VSREF_CLAWR184,C150,C159
P2
P2
P20
TV_VDDA1L27
TV_VDDA2
TV_VDD
L29
L99
L42LVDSVCC
L46DVDD
L44I2CVCC
L35PLLVCC
+2.5VP20 P11
P11
P11
P12
P12
P12
P12
U18
+VCCA
+VPPA
P14U27
P14
+2.5VDDAU7
+3V
P3
+NB_AVDD2L7 P6
+3V_TVL30 P11
+NB_AVDD1L24 P6
+3.3VDACVDDL4 P6
P20
8.1 Base Work Condition(2)
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U14
ClockGenerator
ICS950403
+3V
L58120Z/100M
U20
P10
SouthBridge
1 R230 22 14M_SB_IOSCFS0
14M_SB_APICCLKR238 22FS245
U6
P2
CPU
CPUCLK+R245 1537
CPUCLK-R247 1536
C103 3900P
C107 3900P
R132169
CPUCK+
CPUCK-
SB_VCLKR243 228
U12P7
North BridgeK8N800
GUICLK R234 22 FS1 48
66M_AGP R244 33 11
26
25
SMB_DATA0
SMB_CLK0
USB_CLKR258 2228
P8
U10AudioCodec
P18
P15
J22Mini-PCIConnector
31 R253 22 LPC_48MFS3 R255 0 MINI_LPC_CLK
14 R248 27 MINI_PCI_CLK 25
121C24127P
X3
14.318MHZ
3
4
C24627P
U26PCMCIAController
P14
PCI_CARD_CLK R246 27 1321
U16KBC
Controller
P19 21R262 22CLK_KBC70
C28122P
R264 22CLK_LPC33 22
32 ICS_PD# R254 0
+3V
R25110K
D11RLS4148 SUSA#
P9
PCI_SB_CLKR265 3323
R240 22 AUDIO_14M 2
P4
J16&J17
SO_DIMMSLOT
+3V
R34410K
R32410K
+3VS
R34610K
R32910K
Q352N7002
Q372N7002
SMBDATA_DDR
SMBCLK_DDR
C2400.1U
C2650.1U
C2450.1U
C26210U
C26710U
P5
L59 120Z/100M 5,10..
0111
FS2 FS1 FS0
CPU
10
200.40
FS3
11
2,9…
C2710.1U
HTT PCI
66.80 33.40
R25710K
System Clock Check
C27022P
C25922P
C25522P
C24222P
C25722P
C25222P
C28322P
+3V
R31010K
8.1 Base Work Condition(3)
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System Reset Check
P19
U16
KBCController
W83L950D
U38P20
IMP811
KBC_RESET# 225
SW501
JO501POWERBTN#1
P9
U20
SouthBridge
P7
U12NorthBridge
P2
U6
CPU
KBC_PWR_ON18
KBC_RSMRST RSMRST#8
KBC_SB_PWRBTN7
Q20
Q21
SUSB#Q26KBC_SUSB22
+2.5V
PowerModule
+1.2VPG
CPU_PWROK_2.5V
+2.5V
U22D74HCT08_V
ALL_PWROK_2.5V
PWROK_SB
CPU_PCIRST#
CPU_RESET#
+3V
PCI_RST#LPC_RST#
NB_PCIRST#
NB_PCIRST#
TV_PCIRST#
P11
U3TV
Encoder
J22
J14&J21Primary&Secondary
EIDE Connector
MINI_PCIRST#
P15
MINI-PCI Slot
P13
19
+3V
convert to IDE_PCIRST# IDERST# 2,5
26
P14
U26PCMCIAController
CARD_PCIRST# 20,66
To U12
64
U8C74HCT08_V
U8A74HCT08_V
U22C74HCT08_VP20
ALL_PWROK_2.5V
conv
ert t
o
U22
A
P3
3
8
SB_PWRBTN#
AC97_RST#P8
P18
U10AudioCodec
11
J15Modem
Connector
P16
P20
P8
P8
110
25
8.1 Base Work Condition(4)
P17
R3550
SW1
MNRESET
VCCGND
13
245
+SVDD3
C3891U
R4071K
1
3
4
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*1: No power definitionBase on ACPI Spec. We define the no power as while we press the power button, the system can’t leave S5 statusor none the PG signal send out from power supply.
*2: No display definition Base on the digital IC three basic working conditions: working power, reset, Clock. We define the no display as while system leave S5 status but can’t get into S0 status.
Judge condition:
Check whether there are any voltage feedback control to turn off the power. Check whether no CPU power will cause system can’t leave S5 status.
If there are not any diagram match these condition, we should stop analyzing the schematic in power supply sendingout the PG signal. If yes, we should add the effected analysis into no power chapter.
Judge condition:
Check which power will cause no display. Check which reset signal will cause no display. Check which Clock signal will cause no display
Base on these three conditions to analyze the schematic and edit the no display chapter.
S5: Soft Off S0: Working
Keyword:
For detail please refer the ACPI specification
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No power
Please replace the faulty AC adaptor or Battery.
PowerOK?
Yes
No
Yes
Is theNotebook connected
to power (Either AC adaptoror battery)?
NO
Board-levelTrouble shooting
Check following parts and signals:Parts: Signals:
PWR_VDDINDVMAINADEN#I_LIMITLEARNINGADINPBATT
PJ1PF1PL1PL5PU1PD3PD5PD6
Check following parts and signals:Parts: Signals:PJ2PF3PL16PL17PQ15PR75PD6PR76PQ14
AC Power
Battery
PR92PR94PR97RP44PU20PR108PR109PR85PR88
BATT1PWR_VDDINDVMAINADEN#BAT_VBAT_TBAT_CBAT_DKBC_+3VSKBC_CPUCORE
When power button is pressed ,nothing happens ,power indicator does not light up.
WhereFrom Power SourceProblem(First useAC to power it)
Please try another known good batteryor AC adapter.
Connect AC Adaptor or battery
8.2 No Power(1)
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PJ1
P19
U16
KBCController
I_LIMIT76
LEARNING23
PC380.1U
PC401000P
PC390.1U
PL1
PL5
120Z/100M
120Z/100M
PU9P23
RS+RS-OUT
GND1VCC
GND0
456 1
23
G
S
D
23
1678
5
PQ12N7002
PR21M
PR3100K
PU1AO7004
PC1511000P
PC1501000P
PC1520.01U
ADINP
PR54.7K
PR64.7K
SBM10403
21
PD3DVMAINPR1
0.01
PR4470K
PC410.1U
BAV70LT1PD5
BAV70LT1PD6
PF17A/24VDC
PD2BZV55C24V
PWR_VDDIN
G
S
D
2 316 7 85
PQ15AO4407
PR7633K
PR82226K
PQ17DTC144WK
PQ142N7002
To chapter 8.2.2
32
1
32
1
ADEN#
BATT
MAX4073FEUT-T
PR75100K
14
When power button is pressed ,nothing happens ,power indicator does not light up.
PJO3﹐PJO4SPARKGAP_6
PR3110PC44
1U
PC1480.01U
PC21000P
PC1490.1U
8.2 No Power(2)
P23
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P23
7
6
+SVDD3
PJ2
Battery C
onnector
5
4
3
2
1
BAT_V
PR87499K
PR86100K
PC1250.1U
PL16120Z/100M
PL17120Z/100M
PC1290.1U
PR884.99K
PC1300.1U
PR9120K
PR92 0
PR94 0
PR97 0
BAT_T
BAT_D
BAT_C
P19
U16
KBCController
PWR_VDDIN
4
678
23
15
DVMAIN
PQ15AO4407
PR75100K
PR7633K
PQ142N7002
PD6BAV70LT1
ADEN# 14
PF3TR/SFT-10A
RP4433*4
PU20
OUT1
RS1-
RS1+
GND
OUT2
VCC
RS2-
RS2+
1
2
3
45
6
7
8 I_CHG
PC1451U
PC1471U
+SVDD3
PC1460.1U
PR108 10
PR109 10
PR85 0.01 BATT
BATT1
PC1260.1U
I_DISCHG
BAT_DATA
BAT_CLK
3
2
78
77
C3060.1U
C3070.1U
KBC_+3VS
KBC_CPUCORE
75
74
P23
MAX4377
When power button is pressed ,nothing happens ,power indicator does not light up.
BATT1
BAT_VOLT
BAT_TEMP
+SVDD3
D14BAV70LT1
C3010.1U
BATT1
C3020.1U
PC1240.01U
8.2 No Power(3)
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Battery can not Charge
Connect AC adaptor.
No
Yes
No
Yes
Is thenotebook connected
to power (AC adaptor)?
1. Make sure that the battery is good.2. Make sure that the battery is installed properly.
Please replace the faulty Battery.
Battery chargeOK?
Check following parts and signals:
Parts Signal
PF2PL19PQ21PD16PQ23PL20PL18PD14PD17PQ24PQ25PC144
ADINPCHANGING BATT21N+I_CTRLCHARGINGBATT_SELL
PU19PR95PC133PC141PC143PR102PR101PR100PQ20PQ22U16
When the battery is installed but the battery status indicate LED display abnormal.
ReplaceMother board
Board-levelTrouble shooting
8.3 Battery Can not Be Charged(1)
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PU19P24
E1E2C2
C1GND
RT56789
101112
P19
U16KBC
Controller
79 CHARGING
10 I_CTRL
13 BATT_SELL
ADINPFrom chapter 8.2.1
PF2TR/3216FF-3A
PC1340.01U
PC14210U
PC1360.01U
G
S
D
23
1678
5
PC1391000P
PR1054.7K
PR1064.7K
PQ21MMBT2222A
PR103100K
PD17SSA34
PQ23AO4407
PC13710U
PC1400.1U
PC1271000P
PC13110U
PC1280.01U
PR894.7
PC1351U
PR9510K
PC1330.1U
PC1410.01U
PR992.49K
PJS501SHORT-SMT3
PR98124K
PC1440.1U
VCCOUTPUTCTRLREF2IN-2IN+
CTDTC
FEEDBACK1IN-
1IN+ 123413
141516
PC1321000P
PR9010K
PR93100K
PC1380.1U
PR966.19K
PL183.0UH
PL19DEAD_120Z/100M
PD16BAS32L
PL2033UH
PD14SSA34
PC1430.1U
PR10220K
PR10113.7K
PR100249K
PR10423.7K
PQ222N7002
PQ202N7002
PQ252N7002
CHARGINGFrom U16
TL594C
BATT
PQ24DTA144WK
2IN+
2IN+
When the battery is installed but the battery status indicate LED display abnormal.
0PR84
8.3 Battery Can not Be Charged(2)
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Replace monitoror LCD. Board-level
Troubleshooting
Yes
NoMonitoror LCD module
OK?
Make sure that CPU module,DIMM memory are installedProperly.
DisplayOK?
Yes
No
Correct it.Using debug card,depending on the error codes to make sure which parts maybe faulty
ReplaceMotherboard
1.Try another known good CPU module, DIMM module and BIOS.
2.Remove all of I/O device (FDD,HDD, CD-ROM…….) frommotherboard except LCD or monitor.
DisplayOK?
1. Replace faulty part.2. Connect the I/O device to the
M/B one at a time to find outwhich part is causing the problem.
Yes
No
No Display
Using circuit diagram ,check the faulty parts
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good. 8.4 No Display(1)
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P12
U9
LVDSEncoder
DVDD 53,70,79,95
LVDSVCC 30,40,48
12CVCC 68
PLLVCC 10,16
J8
P12
LC
D C
onnector
TXOUT1+
TXOUT1-
TXOUT0+
TXOUT0-
12
14
11
13
TXOUT2+
TXOUT2-
5
7
44
45
46
47
49
50
LCD_ID[0..2]17,19,21
RP110K*4
ENPBLT_NB
U12
NorthBridge
P7
DVMAINL6
120Z/100M29,30
C190.1U
C210.1U
C421000P
C430.1U
PWR_VDDINR32470K
+1.5V
R1020
ENAVDD
Q1DTC144TKA
Q2AO3400
C221000P
6
8
TXCLK+
TXCLK-
18
20
22
+3VRP31K*4
78R188 10K
R19010K
LVDS_VREF+1.5V
LVDS_D[0..23] NB_FPD[00..23]RP7~RP12
22*4
R182LVDS_CLKIN+
R179LVDS_CLKIN-
R199LVDS_HSYNC
R198LVDS_VSYNC
R193LVDS_DE
22
22
22
22
22
L2526
C3150.1U
BLADJ
67+2.5V R197 4.7K
63~65RP13 0*4
72
22
21
12R144 4.7K
LV_A[0..2]
LV_TST1
LV_PD#R141 4.7K
LV_INTRR142 4.7K
LV_RES1
R140 4.7K
R415 4.7K
R143 4.7K
LV_I2SEL
LV_DUAL
LV_EDGE
61
23
18
C440.1U
1,2
120Z/100M
NB_FPCLK+87
88
75
74
76
NB_FPCLK-
NB_FPHS
NB_FPVS
NB_FPDE
1~8,81~86…
41
42
R124 025
+3V
P10
U20SouthBridge
P8P9
11
P19
U16KBC
Controller
R43310K
3
2
1
ENBL_KBC
R4320
BATT_DEAD#
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
+3V
D1BAW56
15
+SVDD3
RP5310K
C4240.1U
8.4 No Display(2)
R43410K
+3V
Q3DTC144TKA
+1.5V
ENPBLT
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DisplayOK?
External Monitor No Display
1. Confirm monitor is good and checkthe cable are connected properly.
2. Try another known good monitor.
Replace faulty monitor.Yes
No
YesRe-soldering.
No
Parts:
U12U20J2Q5Q6R420R423L15U39U40L18
Signals:
Check if J2are cold solder?
CRT_DDDACRT_DDCKCRT_HSYNCCRT_VSYNCCRT_TEDCRT_GREENCRT_BLUECRT_IN#
R421R422L16L17L12L13L14CP1CP2C1
Check following parts and signals:
RP2C410C411C412R12R13R68R69
There is no display or picture abnormal on CRT monitor, but LCD can normally display.
Board-levelTrouble shooting
ReplaceMother board
8.5 External Monitor No Display(1)
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L12 120Z/100MCRT_RED 1
L13 120Z/100MCRT_GREEN 2
L14 120Z/100MCRT_BLUE 3
L15 120Z/100MCRT_DDDA 12
R1310K
33
+3V
Q52N7002
L18 15CRT_DDCK R423Q6
2N7002
L17 120Z/100M 13
L16 120Z/100M 14CRT_VSYNC
R421
5
C1100P
R12
+3V
CRT_IN#U20
SouthBridge
P9
U12
NorthBridge
P7
CRT_HSYNC
+5V
120Z/100M
R420
33P11
J2
External V
GA
Connector
51
R422 51
1K
+3V
R682.2K
R692.2K
RP275*4
C41022P
C41122P
C41222P
6,7,8,10
CP122P*4
CP222P*4
U3974HCT1G126
U4074HCT1G126
There is no display or picture abnormal on CRT monitor, but LCD can normally display.8.5 External Monitor No Display(2)
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Memory Test Error
TestOK?
Replace the faulty SDRAM module.
Yes
No
Parts: Signals:
1.If your system installed with expansionSO-DIMM module then check them forproper installation.
2.Make sure that your SO-DIMM socketsare OK.
3.Then try another known good SO-DIMMmodules.
If your system host bus clockrunning at 100MHZ then makesure that SO-DIMM modulemeet require of DDR 333.
Replace the faulty SDRAM module.
No
Yes
+3V+1.25VTT+2.5VS_DDR+1.25VSREF_MEMCPU_MD[0..63]CPU_DQS[0..7]CPU_DQM[0..7]MEMADD_A/B[0..13]DDR_BAA/B[0,1]DDR_RASA/B[0,1]DDR_WEA/B[0,1]CPU_CS[0..3]#CPU_CKEA/BCPU_CS[0..3]#DDRCLK[0,1,4..7]DDRCLK[0,1,4..7]#SMBCLK_DDRSMBDATA_DDR
Board-levelTroubleshooting
ReplaceMotherboard
U6U20U14J16J17Q35Q37R324R346R329R344RP19
...RP33
Check following parts and signals
Either on board or extend SDRAM is failure or system hangs up.8.6 Memory Test Error(1)
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P4
J16&J17
+1.25VSREF_MEM
+2.5VS_DDR
P2
U6
CPU
CLAWHAMMER
CPU_MD[0..63]
CPU_DQS[0..7]
CPU_DQM[0..7]
RP19~RP3010*8
+1.25VTT
RP[31﹐﹐﹐﹐33﹐﹐﹐﹐34﹐﹐﹐﹐36﹐﹐﹐﹐37﹐﹐﹐﹐39﹐﹐﹐﹐40﹐﹐﹐﹐42]68*8
DDR_CLK[0,1,4..7]
DDR_CLK[0,1,4..7]#
MEMADD_A/B[0..13]
CPU_CKEA/B
DDR_BAA/B[0,1]
DDR_RASA/B#
DDR_WEA/B#
RP14~RP1847*8
CPU_CS[0..3]#
RP4347*4
P5
U14
ICS950403
SMB_DATA0
SMB_CLK0
SMBDATA_DDR
SMBCLK_DDR
DIM
M0 &
DIM
M1
CLK GEN
+3VS +3V
P9
U20
VT8235South Bridge
+3V
SMBDATA1
SMBCLK1
R32410K
R34610K Q35
2N7002
Q372N7002
R32910K
R34410K
26
25
Either on board or extend SDRAM is failure or system hangs up.
RP[32﹐﹐﹐﹐35﹐﹐﹐﹐38﹐﹐﹐﹐41]68*4
R259,R26047
DDR_CASA/B#
8.6 Memory Test Error(2)
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Keyboard or Touch-PadTest Error
Try another known good Keyboard or Touch-pad.
TestOk?
Replace the faulty Keyboard or Touch-Pad
Yes
No
CheckU16, J501,J18for cold solder?
Yes
No
Re-soldering
Parts
U16U20U14J501J18Q17Q27R262SW502SW505SW503SW504
Signals
+KBC_VDDAKBD_CS0+VDD3KI0..KI7KO0..KO15KBC_EXTSMI#KBC_WAKE_UP#CLK_KBCT_DATAT_CLKXINXOUT
Yes
NoCorrect it.
Is K/B orT/P cable connected to
notebookproperly?
ReplaceMotherboard
Check following parts and signals:
L67L69R292RP51C341C303C304X4
Error message of keyboard or touch-pad failure is shown or any key does not work.
Board-levelTroubleshooting
8.7 Keyboard/Touch Pad Test Error(1)
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Keyboard C
onnector
KI0..KI7
KO0..KO15 1~16
17~24
U16
P19
W83L950D
55~62
39~54
SW505KI4 KO0
JO531
SW502KI3 KO0
JO530
C32822P
X4
8MHZ
R292 1M
28
29 XOUT
XIN
C3040.1U
C3030.1U
26
KBD_CS0
U20
SouthBridge
P8
+5V
C3410.1U
1
J18
P13
Touch Pad C
onnector
2T_DATA 120Z/100M
3T_CLK L69
6
SW504
SW503
L67
120Z/100M
4
5
9
6
C32922P
SW_LEFT
SW_RIGHT
CLK_KBC 70U14
P5
CLK GEN
21
ICS950403
22
+VDD3
EXTSMI# KBC_EXTSMI# 5
WAKE_UP# KBC_WAKE_UP#
Q27DTC144TKA
37
To J501 Keyboard Connector
Q17DTC144TKA
R262
J501
P19+KBC_VREF
72
71
25
+3V
RP514.7K
KBD_CS0From U20 South Bridge
R4290
+KBC_VDDA
Error message of keyboard or touch-pad failure is shown or any key does not work.
P9
8.7 Keyboard/Touch Pad Test Error(2)
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USB Test Error
Check if the USB device is installed properly. (Including charge board.)
Re-testOK?
No
Yes
No
YesCorrect it
Replace another known good USBdevice.
ReplaceMother board
Replace the faulty part
TestOK?
Parts: Signals:U20J3J4J9F2F3F4L20L21L22L23
+5VS
USBP0+
USBP0-
USBP1+
USBP1-
USBP2+
USBP2-
USBP3+
USBP3-
Board-level Trouble shooting
USBP4+
USBP4-
USBP5+
USBP5-
USB_OC#[0..5]
Check following parts and signals:
L97L98C32C33C384R10R27R212
An error occurs when a USB I/O device is installed.8.8 USB Port Test Error(1)
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U20
South Bridge
R1110K
R9560K
C101000P
+C3800.1U
C32330U
R1010K
R4560K
C41000P
R29560K
C391000P
+R2810K
C33330U
R2710K
R26560K
C371000P
USB_OC#1USB_OC#0
USB_OC#3USB_OC#2
R224560K
C3851000P
+R19510K
C384330U
R21210K
R353560K
C3861000P
USB_OC#5
USB_OC#4
P8
J3
P17
USB
2.0
J4
P17
USB
2.0
J9
P17
USB
2.0
C3830.1U
C1010.1U
A1,B1
A1,B1
A1,B1
+5VS
+5VS
+5VS
F2 MINISMDC110
F3 MINISMDC110
F4 MINISMDC110
USBP0-
USBP0+A3
41
2 3
4 1
23
USBP1-
USBP1+
L2290Z/100M
L2390Z/100M
B2A2
B3
USBP2-
USBP2+A3
41
2 3
4 1
23
USBP3-
USBP3+
L2090Z/100M
L2190Z/100M
B2A2
B3
USBP4-
USBP4+A3
41
2 3
4 1
23
USBP5-
USBP5+
L9790Z/100M
L9890Z/100M
B2A2
B3
An error occurs when a USB I/O device is installed.
L101
C361U
C341U
C841U
600Z/100M
8.8 USB Port Test Error(2)
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Hard Driver Test Error
Yes
No
Parts: Signals:Re-bootOK? Replace the faulty parts.
1.Check the BIOS setup 2.Replace another good hard driver try again
Check the system driver for proper installation.
No
Re - TestOK?
End
U20J14PR61PR62RP59RP58R325R320R327R331Q32U8
HDD_PDD[0..15]HDD_PDCS[1,3]#HDD_PDA[0,2]HDD_PDDACK#HDD_IRQ14HDD_PDIOW#HDD_PDDREQHDD_PIORDYHDD_PDA1HDD_PDIOR#IDERST#
Yes
Board-levelTroubleshooting
ReplaceMotherboard
Check following parts and signals:
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writingdata to hard disk.
8.9 Hard Disk Driver Test Error(1)
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IDE_PDD[0..15]
J14
HD
D C
onnector
+5V
C2510.1U
C2540.1U
P9
P13
U20
South Bridge
VT8235
PR61,PR620*8 HDD_PDD[0..15]
IDE_PDCS[1,3]#
IDE_PDA[0,2]
IDE_PDDACK#
IDE_PDDREQ
IDE_PDIOW#
IDE_IRQ14
RP590*8
IDE_PDIOR#
IDE_PDA1
IDE_PIORDYRP580*4
26
34
28
22
24
32
30
35,36
37,38
3~18
+3V
R32510K
+3V
R3204.7K
R22610K
R229470
+5V+3V+3V
R32710K
R33110K
Q32DTC144TKA
IDERST#IDE_PCIRST#PCI_RST#
+3V
U8A74HCT08_V
41,42
2
27
HDD_PDCS[1,3]#
HDD_PDA[0,2]
HDD_PDDACK#
HDD_PDDREQ
HDD_PDIOW#
HDD_IRQ14
HDD_PDIOR#
HDD_PDA1
HDD_PIORDY
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writingdata to hard disk.
P8
R29722
8.9 Hard Disk Driver Test Error(2)
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CD-ROM Driver Test Error
Yes
No
Parts: Signals:TestOK?
Correct it
Try another known good compact disk.
Check the CD-ROM driver for proper installation.
No
Re - TestOK?
Replacethe faulty parts.
U20J21PR63PR68RP69RP70R384R398R327R331Q32U8Yes
Board-levelTroubleshooting
ReplaceMotherboard
CD_SDD[0..15]CD_SDCS[1,3]#CD_SDA[0..2]CD_SDDACK#CD_SDIOW#CD_SDDREQCD_SIORDYCD_IRQ15CD_SDIOR#PCI_RST#
Check following parts and signals:
CD-ROM driver can’t run normally,maybe an error message is shown when reading data from CD-ROM.8.10 CD-ROM Driver Test Error(1)
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IDE_SDD[0..15]
J21
CD
-RO
M
Connector
+5V
C3140.1U
C3130.1U
P9
P13
U20
South Bridge
VT8235
PR63,PR680*8 CD_SDD[0..15]
IDE_SDCS[1,3]#
IDE_SDA[0..2]
IDE_SDDACK#
IDE_SDDREQ
IDE_SDIOW#
IDE_IRQ15
RP700*8
IDE_SDIOR#
IDE_SIORDYRP690*4
+3V
R38410K
R3984.7K
R38510K
+5V+3V+3V
R32710K
R33110K
Q32DTC144TKA
IDERST#IDE_PCIRST#PCI_RST#
+3V
U8A74HCT08_V
38~42
5
27
29
24
6~21
35,36
31,33,34
28
25
22
CD_SDCS[1,3]#
CD_SDA[0..2]
CD_SDDACK#
CD_SDIOW#
CD_SDDREQ
CD_IRQ15
CD_SDIOR#
CD_SIORDY
CD-ROM driver can’t run normally,maybe an error message is shown when reading data from CD-ROM.
R297
P8
22
8.10 CD-ROM Driver Test Error(2)
R3642.7K
+3V
SDA2
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Test OK?
Audio Failure
1. Check if speaker cables are connectedproperly.
2. Make sure all the drivers are installed properly.
Try another known good speaker,CD-ROM.
Re-test OK?
Board-levelTroubleshooting
ReplaceMotherboard
YesCorrect it.
Yes
No
No
Parts:
U10U14U26U13J13J21L45L47L48L43R200R191R194R213L62R172R173
Signals:
+AVDDADVREF_OUTMIC1MIC2CDROM_LEFTCDROM_RIGHTCDROM_ROMMAUDIO_14MAC97_SYNCAC97_SDINAC97_SDOUTAC97_RST#AC97_BITCLKSB_SPKRCARDSPK#AOUT_L
Replace thefaulty parts.
Check following parts and signals:
C148R403U11L52R205Q13C235J12L39L41L50L51L53...
L56
AOUT_RAC_GPI3TP534+5V_AMPSHUTDOWNSPKR_ROUT+SPKR_ROUT-SPKR_LOUT+SPKR_LOUT-HP_SENSE
There is trouble with the sound from speaker or completely no sound.8.11 Audio Failure(1)
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P18
U10
Audio Codec
+3VSL45
120Z/100M1,9
2 AUDIO_14MU14
P5
CLKGeneratorICS950403
45R240
R173 330
R172 330
C144
C142
C143
1U
1U
1U
C1332200P
CDROM_LEFT
CDROM_RIGHT
CDROM_COMM
R177100K
C1342200P
R176100K
18
20
19
Second EID
E C
onnector
P13
J21
1
2
3
+AVDDAD
C1880.1U
R20210K
R403100K
C1481U
PCBEEP
R20610K
R39310K
SB_SPKR
CARDSPK#
U11AHC1G86DBV
P14
U26PCMCIAController
12
AC97_SYNC
AC97_SDIN
AC97_SDOUT
AC97_RST#
R192
10
8
5
11
AC97_BITCLK6 R333
P10
SouthBridge
VT8235
R304 22
R305 22
R300 22
22
22
P9
U20
2
1
3
462
22
AOUT_L
AOUT_R
AC_GPI3
35
36
40
To next page
To next page
To next page
SB_GPO0To next page
There is trouble with the sound from speaker or completely no sound
J101K MIC1 21
120Z/100ML62
+
-
R17847K
R21447K
C162270P
R213 MIC2 22
L48600Z/100M
L43600Z/100M
C1351U
C1411U
R194
1K
MicrophoneJack
VREF_OUT1KR200 0R191 28
P18
MIC501P18
D6/H2.2
InternalMicrophone
C201270P
C1860.1U
C1850.1U
C1820.1U
4,7
+5VL47
120Z/100M25,38
+AVDDAD
C19910U
C1900.1U
C1890.1U
26,42
8.11 Audio Failure(2)--Audio In
R43610K
+3V
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P18
U13
TP534 14
+5VL52
120Z/100M7,18,19
+5V_AMP
+C235100U
C2290.1U
C2120.1U
C2130.1U
21
16
4
9
J13L54 120Z/100M 2SPKR_ROUT-
L55 120Z/100M 3SPKR_LOUT+
L53 120Z/100M 1SPKR_ROUT+
L56 120Z/100M 4SPKR_LOUT-
C2130.1U
TPA0212_GND
L41 120Z/100M
L39 600Z/100M
L50600Z/100M
+C227
R2171K
+C236
R22347K
+5V_AMP
R222HP_SENSE
C224100P
R2181K
R2154.7K
C2081U
AC_GPI3
J12100U
100U
L51600Z/100M
15,17
SHUTDOWN 22
+VDD3
R216100K
R205 0SB_GPO0
Q13DTC144TKAFrom front page U20
AOUT_L
AOUT_R
5
6
20
23
C211
C210
C228
C233
1U
1U
1U
1U
From front page U10
From front page U10
From front page U10
C223100P
100K
C2140.1U
C2300.1U
8
2
3
10
C234 1U
R219 100K
R221 100K
C231 1U
C232 1U 11
JACK-5P-R/A-W9.1
P18
P18
InternalSpeaker Connector
AudioAMP
There is trouble with the sound from speaker or completely no sound
C4190.1U
8.11 Audio Failure(3)--Audio Out
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LAN Test Error
Yes
No
TestOK?
Correct it.
Correct it.
No
Check if BIOS setup is ok.
Re-testOK?
Board-levelTroubleshooting
ReplaceMotherboard
Parts: Signals:
1.Check if the driver is installed properly.2.Check if the notebook connect with the
LAN properly.
Yes
U2U4U20J5L26L28X1R36R51R37R52R34R87R92R93
Check following parts and signals:
+3VS+3VS_LAN_PLL+3VS_LANTXD+TXD-RXIN+RXIN-PJTX+PJTX-PJRX+PJRX-LAN_DATAIOLAN_DCLKLAN_MTXCLAN_MRXC
LAN_MTXD[0..3]LAN_MRXD[0..3]LAN_MTXELAN_COLLAN_CRSLAN_MRXDVLAN_MRXERLAN_XILAN_XO
R283R284RP52RP6R59R54R53R74R413R46
...R49C85C87C74
An error occurs when a LAN device is installed.8.12 LAN Test Error(1)
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P16
P10
U2
SouthBridge
LAN PHY
VT6103L
VT8235
R92 22 LAN_DATAIO 43
R93 22 LAN_DCLK 44
R284 22 LAN_MTXC 9MTXC R62 22
RP6 22*4LAN_MRXD[0..3] 45~48
R59 22 LAN_MTXE 10
R54 22LAN_COL 15
R53 22LAN_CRS 16
R283 22 LAN_MRXC 4MRXC R71 22
RP52 22*4 LAN_MTXD[0..3] 11~14
R413 22LAN_MRXER 5
R74 22LAN_MRXDV 3
TD+
TD-
RD+
RD-
TX+
TX-
RX+
RX-
CMT
RXC
RXIN+
RXIN-
27
26
11
9
16
14
PJTX+
PJTX-
PJRX+
PJRX-
1
2
3
6
32
1 4
1
3
C741000P
PJ4
PJ7
R4775
R4675
R4875
R4975
4,5
7,8
L2890Z/100M
32
1 4
TXD+
TXD-
35
34
6
8
L2690Z/100M
7
R36 10K
+3VS_LAN
R51 10K
R37 10K
R52 10K
23ANE
SPEED 21
DUPLEX 22
TEST# 20
+3VS_LAN
R871.5K
25,36,41
+3VS_LAN_PLL32
+3VS 1,7,18
40
39 X125MHZ
C8522P
C8722P
P16
J5
RJ45-8P/RJ11-4P
U20
P16 U4LF_H41S
LAN_XI
LAN_XO
An error occurs when a LAN device is installed.
10
15
R91300
R34 0+3VS_LAN
C500.1U
R76600Z/100M
C750.1UR78
49.9R7749.9
L31120nH
R6649.9
R6149.9
C540.1U
8.12 LAN Test Error(2)
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Modem Test Error
No
TestOK?
No
Replace a known good modem
Re-testOK?
Board-levelTroubleshooting
1.Check if the driver is installed properly.2.Check if the notebook connect with the
phone LAN properly.
Correct it.
ReplaceMotherboard
Signals:
Yes
+5V+3VS+3VMONO_OUTAC97_SDOUTAC97_RST#AC97_SYNCMDC_SDINAC97_BITCLKTIP_1TIPRING_1RING
J15J7U10U20J5R342L19L105R5R867R305R300R304
YesCorrect it. Parts:
Check following parts and signals:
R341R336R334C187C2C3C666C667JS1JS506
An error occurs when run the modem8.13 Modem Test Error(1)
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J15
Modem
Daughter
Board C
onnector
P9
U20
South BridgeVT8235
AC97_SDOUT23 R305 22
AC97_RST#25 R300 22
MDC_SDIN24
AC97_BITCLK30
P16
26
R334 22
R336 22
R341 22
AC97_SYNC22 R304 22
MONO_OUT 1
P18
U10
Audio Codec
37
+3V
16
21
R342 4.7K
+5V 10,18
C3531U
+3VS 17
C1671U
1UC187
P16
J5
RJ45-8P/RJ11-4P
TIP_1 A1
TIP A2
RING A3RING_1 A4
GND1GND2
3 2
15C3
1000P
C21000P
JS1
TIP
RINGR5 0
L19400UH
3 2
14C6661000P
C6671000P
JS506
TIP_1
RING_1R867 0
L105400UH
2314J7
P16
An error occurs when run the modem8.13 Modem Test Error(2)
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Please change the faulty part then end.
Correct it
Please try another known good Mini PCI device.
1.Please check if the Mini PCI device isinstalled properly.
2.Confirm Mini PCI device driver isinstalled ok.
Mini PCI Test Error
TestOK?
Re-testOK?
Yes
No
Yes
No
Parts:
U20U14J22Q10U8R248R255R297R348R267R127R128R300R305R268R476R478
Board-levelTroubleshooting
Please replaceMotherboard
Signals
PCI_AD[0..31]PCI_C/BE# [0..3]MINIPCI_PDPCI_INTC#PCI_GNT2#SERIRQLDRQ0#AC97_SYNCPCI_PERR#PCI_REQ1#CLKRUN#PCI_SERRPCI_INTD#PCI_IRDY#AC97_SDOUTAC97_RST#
AC97_BITCLKMDC_SDINLAD[0..3]PCI_PARPCI_TRDY#PCI_FRAME#PCI_STOP#PCI_DEVSEL#MINI_PCIRST#MINI_PCI_CLKMINI_LPC_CLK
Check following parts and signals:
An error message is shown after Mini PCI device is installed or the Mini PCI device does’t work.8.14 Mini PCI Test Error(1)
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P15
J22
MIN
I-PCI C
onnector
PCI_AD[0..31]
MINIPCI_PD 13,98
PCI_INTC# 17
U20
P8
South Bridge
P9 P10
LDRQ0# 21,112
29,6567,71,103PCI_REQ1#
86,73,59,45PCI_C/BE#[0..3]
PCI_IRDY#
CLKRUN# PCI_SERR#PCI_PERR#
97+5V
C890.1U
AC97_SYNC
105~107,110MDC_SDINAC97_BITCLKR127,R128R305,R300 22
25MINI_PCI_CLKU14
P5
CLK GEN
R248 2714
121MINI_LPC_CLKR255 0LPC_48MR253 2231
93,16,22,36MINI_LPC_AD[0..3]R476,R269R268,R478 0LAD[0..3]
26MINI_PCIRST#R297 22
U8
20,61PCI_INTD#
30PCI_GNT2#
+5VR339330 D508 Q10
DTC144TKA+3V
RP544.7K
R120 100PCI_AD21 48
56,6466,68,72
PCI_PARPCI_FRAME#
PCI_TRDY#PCI_STOP# PCI_DEVSEL#
AC97_SDOUT AC97_RST#
R348,R267 0 MINI_LPC_LDRQ#MINI_PCI_SERIRQSERIRQ
ICS950403
An error message is shown after Mini PCI device is installed or the Mini PCI device does’t work.
123,
8.14 Mini PCI Test Error(2)
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PC Card Slot Failure
1. Check if the PCMCIA CARD device is installed properly.
2. Confirm PCMCIA card driver is installed ok.
TestOK?
Re-testOK?
Yes
No
Yes
No
Change the faulty part then end.
Parts:
U20U26U14J502U27R396R397RP48RP54RP55R297U8R246R382R391
Try another known good PCMCIA card device.
Correct it
Board-levelTroubleshooting
ReplaceMotherboard
Signals
+VCCA+VPPACCLKRUN#CAD[0..31]CCBE#[0..3]CCLKCIRDY#CTRDY#CSTOP#CDEVSEL#CFRAME#CPARCPERR#CSERR#
CGNT#CINT#CREQ#CBLOCK#CRST#R2_D2R2_D14R2_A18CVS[1,2]CCD#[1,2]CARD_PCIRST#PCI_CARD_CLK
Check following parts and signals:
An error occurs when a PC card device is installed.8.15 CardBus & Reader Test Error(1)
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+VCCA
C3680.1U
90,126
PCI_C/BE#[0..3]
PCI_AD[0..31]
PCI_AD20 R387 13100
P14
J502
Card B
us Socket
+VCCA 17,51
+VPPA
U20
SouthBridge
P8
P5
U14
ICS950403CLK GEN
PCI_CARD_CLK13 R246 21
20,66CARD_PCIRST#R297 22
U8
P9 P10
PCI_DEVSEL# 28,2931~36PCI_FRAME#
PCI_IRDY#PCI_TRDY#
PCI_STOP#PCI_PAR
PCI_PERR#PCI_SERR#
PCI_REQ0# 1
PCI_GNT0# 2,60
CLKRUN# 69
SERIRQ 65
P14
U26
PCMCIAController
+3V
R396 67PCI_LOCK#
R397 70
14,18,30..
C3610.1U
C3600.1U
C3660.1U
10K
10K
C3670.1U
CAD[0..31]
CCBE#[0..3]
CCLK
CFRAME#
CIRDY# CTRDY#
CDEVSEL#CSTOP#
CPAR CPERR# CSERR#
CREQ#CGNT# CINT#
CBLOCK#
CCLKRUN#
CRST#
R2_D2 R2_D14 R2_A18
CVS[1,2]
CCD#[1,2]
+VCCA11,12,13
+VPPA10
16+3V
R39110K
C3670.1U
+5V
C3730.1U
+3V
C3690.1U
C3710.1U
VCCEN#[0,1] 1,2
VPPEN[0,1] 14,15
3,4
5,6
C3640.1U
C3740.1U
+3V
RP484.7K*8
RP552.2K
RP544.7K
27
74HCT08_V
P14
U27
CP22117
73,74
71,72
36,6775,137
43,57131,117
32,40,47143,84,100
103,119
136 33
+VCCA
R38247K
76,77,79.. 2,3,4..
88,99.. 7,12..
19,20,53108~110
105,107,111 49,50,54
13,14,59
106,132,123 15,16,60
48,58
C3720.1U
18,52
C3650.1U
An error occurs when a PC card device is installed.
PCI_INTB#
R40110K
CCBE#0
101,104,133
R39410K
CRST#
+3V
8.15 CardBus & Reader Test Error(2)
+VCCA
+VCCA
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TV Fail
1. Check if the TV device is installedproperly.
2. Confirm TV driver is installed ok.
Yes
No
TestOK?
Correct it.
Correct it.Yes
No
Check if BIOS setup is ok.
Re-testOK?
Board-levelTroubleshooting
ReplaceMotherboard
Parts: Signals
TV_VDDTV_VDDA1TV_VDDA2TV_LUMATV_CRMATV_COMPTV_PCIRST#TVD[0..15]TVHSTVVSTVCLKTVCLK1
U3U12U20J1C52R119R381X6C395C396R297U8L9L10L11L1
Check following parts and signals:
R55R79R112R113R94R89RP4C46C47C48C64C66C5C6C7
TV_DSI2C_DATAI2C_CLK
An error occurs when using the computer as TV.8.16 TV Encoder Test Error(1)
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TVD[0..11]
TVHS 23
22TVVS
25TVCLK
TVCLKI 27
TV_DS 29
U12
NorthBridge
P7
I2C_DATA 21
I2C_CLK 20
R119 0
R381 0
U20SouthBridge
P8
R297 22PCI_RST# TV_PCIRST#
U8C
+3V_TV
TV_VDD
26,40,57
18,32,48,59
TV_VDDA164,1
TV_VDDA25,9,13
C52 0.1U 6
R8210K
An error occurs when using the computer as TV.
U3
P11
TV Encoder
L9 4
6
2.7UH
2.7UH
2.7UH 7
L11
L10
TV_LUMA
TV_CRMA
TV_COMP
RP475*4
C46270P
C48270P
C47270P
C6270P
C7270P
C5270P
J1
S-Video
1
3
GND1
GND2L1JP_BEAD_DFS
R55 4.64K
10K
10K
10K
10K
10K
TV_RSET
R112
R113
R79
R94
R89
TV_TE
TVD12
TVD13
TVD14
TVD15
7
C64 10P
10PC66
TV_BCO
TV_VSO
61
60
46
47
50
51
54
14
12
10
2
X614.318MHZ
C39627P
C39527P
3
P11
19
R60 0
R72 0
R121 0
R39 0
+3V_TV
8.16 TV Encoder Test Error(2)
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Part Number Description Location(S)221679920001 CARTON;NON-BRAND,8640C
221679950001 PARTITION;IN CARTON,8640C
221679950002 CARD BOARD;TOP/BTM,PALLET,8640C
221679950003 CARD BOARD;FRAME,PALLET,8640C
221679950004 PARTITION;PALLET,8640C
222600020049 PE BAG;50*70MM,W/SEAL,COMMON
222600020310 PE BAG;70X100MM,W/SEAL,COMMON
222670820003 PE BAG;L560*W345,7521N
222671330003 PE BAG;LCD BRACKET,STINGRAY
222678500002 PE BUBBLE BAG;BATTERY,280*170,MS
224670830002 PALLET;1250*1080*130,7521N
225600000054 TAPE;INSULATING,POLYESTER FILM,1
225600000061 TAPE;ADHENSIVE,DOUBLE-FACE,W20,U
225682900001 CONDUCTIVE TAPE;DC,M/B,8599
227675400003 EPE PAD;K/B,8355
227682900001 END CAP;R,8599
227682900002 END CAP;L,8599
242600000001 LABEL;PAL,20*5MM,COMMON
242600000088 LABEL;BAR CODE,125*65,COMMON
242600000145 LABEL;10*10,BLANK,COMMON
242600000145 LABEL;10*10,BLANK,COMMON
242600000232 LABEL;6*6MM,GAL,BLANK,COMMON
242600000378 LABEL;27*7MM,HI-TEMP 260'C
242600000385 LABEL;27*10,LAN ID BAR CODE
242600000433 LABEL;BLANK,11*5MM,COMMON
Part Number Description Location(S)242600000439 LABEL;25*6,HI-TEMP,COMMON
242600000452 LABEL;BLANK,7MM*7MM,PRC
242600000452 LABEL;BLANK,7MM*7MM,PRC
242664800013 LABEL;CAUTION,INVERT BD,PITCHING
242668300028 LABEL;32*7MM,POLYESTER FILM,HOPE
242669600005 LABEL;LOT NUMBER,RACE
242670800113 BFM-WORLD MARK;WINXP,7521N
242679900005 LABEL;BAR CODE,(25*10MM)*12pcs,8
242684100001 LABEL;AGENCY-GLOBAL,8399
242684100002 LABEL;BATT 11.1V/4AH,LI,PANA,839
245600010007 FLOW CARD;M/B,WHITE
271002000301 RES;0 ,1/10W,5% ,0805,SMT R431
271002100301 RES;10 ,1/10W,5% ,0805,SMT PR17,PR28
271002331301 RES;330 ,1/10W,5% ,0805,SMT FR3,FR4,R14,R15
271002472301 RES;4.7K ,1/10W,5% ,0805,SMT PR5,PR6
271035012711 RES;.012,1W,1%,2010,LR2010,IRC,S PR73
271044060301 RES;.006 ,1.5W,5% ,2512,SMT
271045107101 RES;.01 ,1W ,1% ,2512,SMT PR1,PR85
271045127102 RES;.012,1W,1%,2512,SMT PR74
271046068101 RES;.006 ,1.5W ,1% ,2512,SMT;PWR RM4
271061000002 RES;0 ,1/16W,0402,SMT R102,R105,R119,R121,R129,R134
271061101103 RES;100 ,1/16W,1% ,0402,SMT R120,R181,R184,R235,R24,R261,R
271061102105 RES;1K ,1/16W,1% ,0402,SMT R12,R166,R217,R218
271061102303 RES;1K ,1/16W,5% ,0402,SMT R1,R194,R200,R213,R288,R296,R3
271061103102 RES;10K ,1/16W,1% ,0402,SMT R10,R11,R195,R212,R27,R28
9. Spare Part List(1)
MiTac Secret
Confidentia
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83998399 N/B MaintenanceN/B Maintenance
134
Part Number Description Location(S)271061103501 RES;10K ,1/16W,5% ,0402,SMT R112,R113,R117,R13,R145,R146,R
271061104501 RES;100K ,1/16W,5% ,0402,SMT R176,R177,R216,R219,R221,R222
271061105501 RES;1M ,1/16W,5% ,0402,SMT R292
271061106501 RES;10M ,1/16W,5% ,0402,SMT R345
271061121501 RES;120 ,1/16W,5% ,0402,SMT R183,R186,R207,R208,R209,R210
271061152501 RES;1.5K ,1/16W,5% ,0402,SMT R87
271061203102 RES;20K ,1/16W,1% ,0402,SMT R289
271061220501 RES;22 ,1/16W,5% ,0402,SMT R127,R128,R179,R182,R192,R193
271061222501 RES;2.2K ,1/16W,5% ,0402,SMT R68,R69
271061300131 RES;300 ,1/16W,5% ,0402,SMT R91
271061302101 RES;3K ,1/16W,1% ,0402,SMT R170,R448
271061330501 RES;33 ,1/16W,5% ,0402,SMT R241,R244,R265,R420,R423
271061331304 RES;330 ,1/16W,5% ,0402,SMT R154,R172,R173,R225,R227,R228
271061361101 RES;360 ,1/16W,1% ,0402,SMT R165,R315,R350,R445
271061401101 RES;402,1/16W,1%.0402,SMT R450
271061464112 RES;4.64K ,1/16W,1% ,0402,SMT R55
271061470501 RES;47 ,1/16W,5% ,0402,SMT R259,R260
271061471501 RES;470 ,1/16W,5% ,0402,SMT R229,R323
271061472501 RES;4.7K ,1/16W,5% ,0402,SMT R108,R109,R110,R111,R130,R137
271061473501 RES;47K ,1/16W,5% ,0402,SMT R178,R214,R223,R382,R386
271061474501 RES;470K ,1/16W,5% ,0402,SMT R123,R211,R32
271061499012 RES;49.9 ,1/16W,1% ,0402,SMT R101,R107,R61,R66,R77,R78
271061512102 RES;5.1K ,1/16W,1% ,0402,SMT R67
271061562501 RES;5.6K ,1/16W,5% ,0402,SMT R328,R356
271061564101 RES;560K ,1/16W,1% ,0402,SMT R224,R26,R29,R353,R4,R9
Part Number Description Location(S)271061604011 RES;60.4 ,1/16W,1% ,0402,SMT R81,R90
271061619211 RES;6.19K,1/16W,1% ,0402,SMT R287
271061649212 RES;6.49K,1/16W,1% ,0402,SMT R70
271061681501 RES;680 ,1/16W,5% ,0402,SMT R131,R135,R138,R139,R148,R150
271061753101 RES;75,1/16W,1%,0402,SMT R46,R47,R48,R49
271061821101 RES;820 ,1/16W,1% ,0402,SMT R114,R118
271061822501 RES;8.2K ,1/16W,5% ,0402,SMT R290,R411
271061900101 RES;90.9,1/16W,1%.0402,SMT R14
271071000002 RES;0 ,1/16W,5% ,0603,SMT L36,L37,L57,PR10,PR12,PR13,PR
271071000002 RES;0 ,1/16W,5% ,0603,SMT R42,X38
271071100302 RES;10 ,1/16W,5% ,0603,SMT PR108,PR109,PR18,PR31,PR34,P
271071101301 RES;100 ,1/16W,5% ,0603,SMT R11,R12,R13,R17,R18,R35,R36
271071102102 RES;1K ,1/16W,1% ,0603,SMT PR37,PR52
271071102302 RES;1K ,1/16W,5% ,0603,SMT R11
271071103101 RES;10K ,1/16W,1% ,0603,SMT PR16,PR62,PR90,PR95
271071103302 RES;10K ,1/16W,5% ,0603,SMT PR22,R376,R433
271071103302 RES;10K ,1/16W,5% ,0603,SMT R1,R37,R38
271071104101 RES;100K ,1/16W,1% ,0603,SMT R2,R3
271071104302 RES;100K ,1/16W,5% ,0603,SMT R7
271071104302 RES;100K ,1/16W,5% ,0603,SMT PR103,PR3,PR57,PR72,PR75,PR9
271071104701 RES;100K ,1/16W,.1%,0603,SMT PR86
271071105301 RES;1M ,1/16W,5% ,0603,SMT PR2,PR49,PR56,R303
271071105301 RES;1M ,1/16W,5% ,0603,SMT R16,R39
271071107311 RES;107K ,1/16W,1% ,0603,SMT PR21,PR69
271071111101 RES;110 ,1/16W,1% ,0603,SMT R156
9. Spare Part List(2)
MiTac Secret
Confidentia
l Docum
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83998399 N/B MaintenanceN/B Maintenance
135
Part Number Description Location(S)271071124311 RES;124K ,1/16W,1% ,0603,SMT PR98
271071131101 RES;130 ,1/16W,1% ,0603,SMT R14A
271071137271 RES;13.7K,1/16W,.1%,0603,SMT PR101
271071143112 RES;14K,1/16W,1%,0603,SMT PR15
271071151103 RES;15 ,1/16W,1% ,0603,SMT R245,R247
271071169011 RES;169 ,1/16W,1% ,0603,SMT R132
271071202102 RES;2K ,1/16W,1% ,0603,SMT PR60
271071202301 RES;2K ,1/16W,5% ,0603,SMT R12
271071203101 RES;20K ,1/16W,1% ,0603,SMT PR61,PR68,PR9,PR91
271071203701 RES;20K ,1/16W,.1%,0603,SMT PR102
271071204101 RES;200K ,1/16W,1% ,0603,SMT PR66,PR67
271071220101 RES;22 ,1/16W,1% ,0603,SMT R168
271071224301 RES;220K ,1/16W,5% ,0603,SMT R41
271071226311 RES;226K ,1/16W,1% ,0603,SMT PR82
271071228301 RES;2.2 ,1/16W,5% ,0603,SMT PR48,PR65,PR70
271071243211 RES;24.3K,1/16W,1% ,0603,SMT PR104
271071249111 RES;2.49K,1/16W,1% ,0603,SMT PR99
271071249311 RES;249K ,1/16W,1% ,0603,SMT PR100
271071270301 RES;27 ,1/16W,5% ,0603,SMT R246,R248
271071272301 RES;2.7K ,1/16W,5% ,0603,SMT R366,R367,R372,R373,R374,R375
271071301311 RES;301K ,1/16W,1% ,0603,SMT R13,R3
271071302101 RES;3K ,1/16W,1% ,0603,SMT PR30,PR33
271071330302 RES;33 ,1/16W,5% ,0603,SMT R157,R169
271071333301 RES;33K ,1/16W,5% ,0603,SMT R2
271071333301 RES;33K ,1/16W,5% ,0603,SMT PR76
Part Number Description Location(S)271071348111 RES;3.48K,1/16W,1% ,0603,SMT PR29
271071348812 RES;34.8 ,1/16W,1%,0603,SMT R174,R180
271071402111 RES;4.02K,1/16W,1% ,0603,SMT PR50
271071432111 RES;4.32K,1/16W,1% ,0603,SMT R10
271071432211 RES;43.2K,1/16W,1% ,0603,SMT R1
271071442113 RES;44.2 ,1/16W,1% ,0603,SMT R100,R30
271071472302 RES;4.7K ,1/16W,5% ,0603,SMT PR105,PR106
271071473101 RES;47K ,1/16W,1% ,0603,SMT PR11
271071474301 RES;470K ,1/16W,5% ,0603,SMT PR4
271071478301 RES;4.7 ,1/16W,5% ,0603,SMT PR89
271071499111 RES;4.99K,1/16W,1% ,0603,SMT PR32,PR88
271071499311 RES;499K ,1/16W,1% ,0603,SMT PR87
271071499811 RES;49.9 ,1/16W,1% ,0603,SMT R19,R25
271071510301 RES;51 ,1/16W,5% ,0603,SMT R421,R422
271071563101 RES;56K ,1/16W,1% ,0603,SMT R6
271071619111 RES;6.19K,1/16W,1% ,0603,SMT PR96
271071634211 RES;63.4K,1/16W,1% ,0603,SMT PR59
271071753301 RES;75K ,1/16W,5% ,0603,SMT R8
271071806812 RES;80.6 ,1/16W,1% ,0603,SMT R151
271071822301 RES;8.2K ,1/16W,5% ,0603,SMT R256,R388
271071866111 RES;8.66K,1/16W,1% ,0603,SMT PR51
271071887111 RES;8.87K,1/16W,1% ,0603,SMT R133
271071909101 RES;9.09K,1/16W,1% ,0603,SMT PR8
271072383011 RES;383 ,1/10W,1% ,0603,SMT R319,R352
271072474101 RES;470K ,1/10W,1% ,0603,SMT R4,R5,R9
9. Spare Part List(3)
MiTac Secret
Confidentia
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83998399 N/B MaintenanceN/B Maintenance
136
Part Number Description Location(S)271571000301 RP;0*8 ,16P ,1/16W,5% ,1606,SM RP59,RP61,RP62,RP63,RP68,RP7
271571100301 RP;10*8 ,16P ,1/16W,5% ,1606,SM RP19,RP21,RP22,RP24,RP25,RP2
271571470301 RP;47*8 ,16P ,1/16W,5% ,1606,SM RP14,RP15,RP16,RP17,RP18
271571680302 RP; 68*8 ,16P,1/16W,5% ,1606,SM RP31,RP33,RP34,RP36,RP37,RP3
271586026101 RES;.02 ,2W,1%,2512,SMT PR107
271591000701 RP;0*4,8P,1/16W,.1%,0804,SMT RP13,RP58,RP69
271591220301 RP;22*4,8P,1/16W,5%,0804,SMT RP10,RP11,RP12,RP52,RP6,RP7,R
271591470301 RP;47*4,8P,1/16W,5%,0804,SMT RP43
271591471301 RP;470*4,8P,1/16W,5%,0804,SMT RP72,RP73
271611100301 RP;10*4 ,8P ,1/16W,5% ,0612,SMT RP20,RP23,RP26,RP29
271611102301 RP;1K*4 ,8P ,1/16W,5% ,0612,SMT RP3
271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP1,RP45,RP57
271611153301 RP;15K*4 ,8P ,1/16W,5% ,0612,SMT RP46,RP49,RP50
271611330301 RP;33*4 ,8P ,1/16W,5% ,0612,SMT RP44
271611680301 RP;68*4 ,8P ,1/16W,5% ,0612,SMT RP32,RP35,RP38,RP41
271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP2,RP4
271621103302 RP;10K*8 ,10P,1/32W,5% ,1206,SMT RP47,RP53,RP56,RP60,RP66,RP6
271621222301 RP;2.2K*8,10P,1/16W,5% ,1206,SMT RP55
271621472302 RP;4.7K*8,10P,1/32W,5% ,1206,SMT RP48,RP51,RP54,RP64,RP65,RP7
272001105403 CAP;1U ,10%,10V ,0805,X7R,SMT PC145,PC147,PC44
272001106702 CAP;10U,6.3V,+- 20%,0805,X5R,SMT C115,C125,C126,C127,C128,C132
272001106703 CAP;10U,10V,+80-20%,0805,Y5V,SMT C100,C105,C12,C120,C158,C164,C
272001475403 CAP;4.7U,10V,10%,0805,X5R,SMT C122,C140,C202,C204,C243,C260
272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y C342,C351,C421,C96
272002105701 CAP;1U ,CR,16V ,-20+80%,0805,Y5 PC135,PC23,PC33
Part Number Description Location(S)272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y C420
272005104401 CAP;.1U ,CR,50V,10%,0805,X7R,IN PC19,PC34
272005104404 CAP;.1U,CR,50V,10%,0805,SMT PC111,PC80,PC93
272005104705 CAP ;1U CR 50V +80-20% 0805 Y5V C17,C18
272011106407 CAP;10U,10V,+/-10%,1206,X5R,SMT, PC10,PC110,PC13,PC3,PC6,PC68
272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S PC103,PC70
272011475401 CAP;4.7U ,10%,10V ,1206,X7R,SMT C41
272012105401 CAP;1U ,CR,16V ,10%,1206,X7R,S C14A,C14B
272012106701 CAP;10U ,16V ,+80-20%,1206,Y5U, PC48
272021226701 CAP;22U ,10V,+80-20%,1210,Y5V,S PC97
272023106002 CAP;10U,25V,M,1210,T2.8MM,X5R,SM PC131,PC137,PC142
272023106501 CAP;10U ,25V ,20%,1210,Y5U,SMT PC11
272023106502 CAP;10U,25V,M,1210,T2.5MM,X5R,SM PC24,PC30,PC43,PC49,PC5,PC51
272023475401 CAP;4.7U ,25V ,10%,1210,X5R,SMT C1
272030102301 CAP;100P,3KV,5%,1808,NPO,SMT,PWR C20
272030102405 CAP;1000P,CR,3KV,10%,1808,X7R,TU C2,C3,C666,C667,C74
272071105403 CAP;1U ,10V ,10%,0603,X5R,SMT C10,C4
272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 C311,C375
272071225401 CAP;2.2U ,CR,6.3V ,10%,0603,X5R, C282,C336
272071332401 CAP;.33U ,10V ,10%,0603,X7R,SMT C2
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM C12,C17,C6
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM C339,PC138
272072104702 CAP;.1U ,16V,+80-20%,0603,Y5V,S PC20,PC22,PC28,PC31,PC47,PC6
272072224402 CAP;.22U ,16V ,10%,0603,X7R,SMT C108,C131,C136,C15,C156,C16,C2
272072224701 CAP;.22U ,16V ,+80-20%,0603,Y5V, C116,C117,C402,C403,C404,C405
9. Spare Part List(4)
MiTac Secret
Confidentia
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83998399 N/B MaintenanceN/B Maintenance
137
Part Number Description Location(S)272072473402 CAP;.047U,16V ,10%,0603,X7R,SMT C266
272072683404 CAP;.068U ,16V ,10%,0603,X7R,SMT C16
272073180401 CAP;18P ,CR,25V ,10%,0603,NPO,S C355,C356
272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S C9
272073392401 CAP;3900P,50V,10%,0603,X7R,SMT C103,C107
272073472301 CAP;4700P,CR,50V ,5% ,0603,X7R,S C15A
272075102402 CAP;1000P,CR,50V,10%,0603,X7R,IN PC105,PC109,PC75,PC92
272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SM PC1,PC123,PC127,PC132,PC139,P
272075102501 CAP;1000P,CR,50V ,20%,0603,X7R,S PC108
272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S PC21,PC36,PC84
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S C11,C13,C3,C8
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S PC102,PC116,PC117,PC128,PC14
272075103403 CAP;.01U ,50V,10%,0603,X7R,SMT PC90
272075103408 CAP ;0.1U CR 50V 10% 0603 X7R S C15,C16,C35,C37,C39
272075103702 CAP;.01U ,50V,+80-20%,0603,Y5V,S PC119,PC124,PC134,PC136,PC14
272075103706 CAP; 0.1U CR 50V +80-20% 0603 Y C28,C30,C31,C32,C33,C34
272075104701 CAP;.1U ,50V,+80-20%,0603,Y5V,S C344,C425,PC107,PC113,PC118,P
272075181301 CAP;180P ,50V ,5% ,0603,NPO,SMT PC104,PC98
272075220301 CAP;22P ,50V ,5% ,0603,COG,SMT C85,C87
272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT C5
272075222701 CAP;2200P,50V ,+/-20%,0603,X7R,S C133,C134
272075223702 CAP; 0.22U CR 50V +80-20% 0603 C29,C40,C41
272075330401 CAP;33P ,CR,50V ,10%,0603,X7R,S PC32
272075470401 CAP;47P ,50V ,10%,0603,COG,SMT PC100,PC101
272075471401 CAP;470P ,50V,10%,0603,X7R,SMT C36
Part Number Description Location(S)272075471409 CAP; 0.0047U CR 50V 10% 0603 X7 C19
272075472701 CAP;4700P,50V ,+ -20%,0603,X7R,S PC37
272075822401 CAP;8200P,CR,50V,10%,X7R,0603,SM PC106
272102100401 CAP;10P ,50V ,+-10%,0402,NPO,SM C321,C64,C66
272102104401 CAP;.1U ,CR,10V,10%,0402,X5R,SM C102,C104,C106,C124,C13,C130,C
272102105701 CAP;1U ,CR,6.3V ,80-20%,0402,Y C110,C111,C118,C121,C135,C141
272102224701 CAP;.22U ,10V ,+80-20%,0402,Y5V, C137,C225,C264,C278
272102334701 CAP;.33U ,CR,10V ,+80-20%,0402,Y C139
272105059401 CAP;5P ,50V,+-10%,0402,SMT C283
272105101401 CAP;100P ,50V ,5%,0402,COG,SMT C1,C223,C224
272105101402 CAP;100P ,50V ,+ -10%,0402,NPO,S C114,C129,C206,C261
272105102408 CAP;1000P,CR,50V,10%,0402,X7R,SM C10,C138,C180,C22,C250,C37,C38
272105102501 CAP;1000P,50V ,+/-20%,0402,X7R,S C123
272105103402 CAP;.01U ,CR,25V ,10%,0402,X7R,S C150,C152
272105103702 CAP;.01U ,50V,+80-20%,0402,SMT C112,C119,C154,C175,C179,C25,C
272105104701 CAP;.1U ,16V,+80-20%,0402,SMT C101,C109,C113,C155,C169,C173
272105220402 CAP;22P ,50V ,+ -10%,0402,NPO,S C242,C249,C252,C255,C257,C259
272105221403 CAP;220P ,CR,50V ,10%,0402,X7R,S C406
272105222501 CAP;2200P,50V ,+/-20%,0402,X7R,S C99
272105270303 CAP;27P ,50V ,5%,0402,COG,SMT C241,C246,C395,C396
272105271403 CAP;270P ,50V,+-10%,0402,X7R,SMT C162,C172,C174,C201,C357,C378
272105332402 CAP;3300P,50V,10%,0402,SMT C80
272431227402 CAP;220U,2V,-35/+10%,H1.9,S,SP-C PC35,PC64
272431227503 CAP;150U ,POLY,6.3V,20%,7243,SMT PC7,PC77,PC9
272602107501 EC;100U,16V,M,6.3*5.5,-55+85'C,S C227,C235,C236
9. Spare Part List(5)
MiTac Secret
Confidentia
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83998399 N/B MaintenanceN/B Maintenance
138
Part Number Description Location(S)272625220401 CP;22P*4 ,8P,50V ,10%,1206,NPO,S CP1,CP2
272990100301 CAP;10P,3000V,+- 5%,NPO,SMT C19
273000130001 FERRITE CHIP;120OHM/100MHZ,1608, L52
273000130006 FERRITE CHIP;600OHM/100MHZ,.2A,1 L100,L101,L43,L48,L50,L501,L5
273000130019 FERRITE CHIP;120OHM/100MHZ,1608, L10,L11,L12,L13,L14,L15,L16,L1
273000130038 FERRITE CHIP;600OHM/100MHZ,1608, L38,L39,L40,L49,L57,R124
273000130062 INDUCTOR;120nH,10%,0603,SMT L31
273000150002 FERRIET CHIP;120OHM/100MHZ,2012, L2,L24,L27,L29,L3,L30,L32,L33,
273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L58,PL1,PL10,PL11,PL12,PL14,P
273000150313 CHOKE COIL;90OHM/100MHZ,20%,2012 L20,L21,L22,L23,L26,L28,L97,L9
273000500092 CHOKE COIL;2.2UH ,20%,16A,3.5MM PL7
273000500115 CHOKE COIL;400uH MIN,120mΩ MAX; L105,L19
273000990018 INDUCTOR;10uH,CDRH125,SUMIDA,SMT PL13,PL15
273000990021 INDUCTOR;33uH,CDRH124,SUMIDA,SMT PL20
273000990127 INDUCTOR;IHLP5050CE-01-0.68uH,VI PL3,PL4
273000990186 INDUCTOR;3.0UH,30%,CDRH6D28,H2.8 PL18
273001050028 XSFORMER;10/100 BASE,LF-H41S,SMT U4
273001050127 XFMR;CI8.5,30T/2150T ,300mH,SMT,o T1
274011431414 XTAL;14.318MHZ,32PF,50PPM,8*4.5, X3,X6
274013276103 XTAL;32.768KHZ,20PPM,12.5PF,CM20 X5
281101015001 IC;MP1015EM-Z,CCFL CTRL,TSSOP20, U1
282574186002 IC;74AHCT1G86,SINGLE,XOR,SOT23,S U11
282607408001 IC;74HCT08PW,2-INPUT AND GATE,TS U22,U8
282607408002 IC;SN74HCT08PW,2-INPUT AND GATE,
282674112601 IC;74HCT1G126GW,NON-INVERTING BU U39,U40
Part Number Description Location(S)282674112602 IC;SN74AHCT1G126DCK,NON-INVERTIN
282674244004 IC;74HCT244D,OCT TRI-ST BUF,SOIC U23,U24
283467540001 IC;EEPROM,M24C02-WMN6T,2K,SO8,SM IC6
283467540002 IC;EEPROM,M93C46-WMN6T,64*16 BIT U15
283480404001 IC;FLASH,256K*8-70,PLCC32,A29002
284500781001 IC;G781,TEMPERATURE MTR,SO8 U5
284501617005 IC;VT1617A,AUDIO CODEC,TQFP,48P U10
284501622003 IC;VT1622AM,TV ENCODER,PQFP,64P, U3
284506103009 IC;VT6103L,LAN-PHY,LQFP,48P,SMT U2
284508235007 IC;VT8235,0340CD,SOUTH BRIDGE,BG U20
284508800006 IC;VIA K8N800CE,N.B.,BGA578,SMT U12
284516310001 IC;VT1631,LVDS TRANSMITTER,TQFP, U9
284583950002 IC;W83L950D-Ver.C,LPC_KBC,LQFP,8
284595040301 IC;ICS950403,TIMING CTL HUB FOR U14
286101428001 IC;G1428,AMPLIFIER,TSSOP,24P,SMT U13
286104073001 IC;MAX4073F,I-SENSE AMP,SOT23,6P PU9
286300338001 IC;SC338,FET CTRL,SC,MSOP-10 PU3
286300594001 IC;TL594C,PWM CONTROL,SO,16P PU19
286301410002 IC;CB1410Q_B0,PCI/CARDBUS,LQFP,1 U26
286301414001 IC;MM1414,PROTECTION,TSOP-20A,PR IC7
286301470001 IC;SC1470,PWM CTRL,TSSOP,14P,SMT PU11
286302211006 IC;CP2211,POWER DISTRI SW,REV.C1 U27
286302996001 IC;G2996,DDR,GMT,SOP8FD,SMT PU13
286303107001 IC;AMS3107C,3.3V,1%,VOL REGULATO U19
286303728002 IC;LTC3728LX,PWM CTRL,LTC,5X5 QF PU14
9. Spare Part List(6)
MiTac Secret
Confidentia
l Docum
ent
83998399 N/B MaintenanceN/B Maintenance
139
Part Number Description Location(S)286304377001 IC; MAX4377F,I-SENSEAMP ,MSOP8,S PU20
286306207001 IC;ISL6207CB,PWM DRIVER,SO8,SMT PU5,PU7
286306559002 IC;ISL6559,MULTI-PHASE PWM CTL,S PU6
286308800007 IC;AME8800DEFT,VOL REG.,SOT89,3P U17
286308804002 IC;AME8804AEEY,ADJ,0.3A,LDO,SOT2 U7
286329513001 IC;AMS2951CS-3.3,3.3V,150MA VLOT U28
286369229301 IC;G692L293T ,RESET CIRCUIT,2.93V U38
286387506001 IC;S-875061EUP VOLT DETECTOR S IC5
288100014010 DIODE;SS14,40V,1A,SMA,VISHAY PD11
288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D12,PD16
288100034004 DIODE;SSA34,40V,3A,SMA PD14,PD17,PD7,PD8
288100054002 DIODE;BAT54C,SCHOTTKY DIODE,SOT2 D17
288100056003 DIODE;BAW56,70V,215mA,SOT-23 D1
288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM ZD3,ZD4
288100056017 DIODE;BAW56LT1,70V,215MA,SOT-23, PD12
288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 D14,PD5,PD6
288101040006 DIODE;SBM1040,10A,SCHOTTKY,POWER PD3
288104148001 DIODE;RLS4148,200MA,500MW,MELF,S D11
288105524003 DIODE;BZV55-C24,ZENER,5%,SOD-80, PD2
288110355001 DIODE;1SS355,80V,100mA,SOD-23,SM D3
288111544001 DIODE; 1SR-154-400 400V 1.0A D4
288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23 Q8
288200144008 TRANS;DTA144EKA,PNP,SMT Q8
288200301001 TRANS;FDV301N,N-CHANNEL,SOT23 Q20
288200416001 TRANS;AOB416,30V/110A,.0065OHM,N PQ2,PQ5
Part Number Description Location(S)288200420001 TRANS;AOB420,30V/110A,.010OHM,N- PQ4,PQ7
288200717001 DIODE;RB717F,SCHOTTKY,40V,SOT323 SD2
288202222001 TRANS;MMBT2222AL,NPN,TO236AB PQ21
288202237002 TRANS;MUN2237T1,NPN,SOT-23,SMT,O PQ17,Q26,Q31
288202240001 TRANS;MUN2240T1,NPN,SOT-23,ON Q1,Q10,Q13,Q16,Q17,Q22,Q23,Q2
288203400001 TRANS;AO3400,N-MOSFET,SOT-23 Q2
288203403001 TRANS;AO3403,P-MOSFET,SOT-23,ALP Q11,Q9
288203413001 TRANS;AO3413,P-MOSFET,SOT-23 Q15,Q36
288204403008 TRANS;AO4403,P-MOSFET,46mOHM (VG U21,U35
288204407001 TRANS;AO4407,P-MOS,.01OHM,SO8,SM PQ15,PQ23,PU1
288204409001 TRANS;AO4409,P-MOSFET,SO-8P,MSL, Q10,Q14
288204410010 TRANS;AO4410,N-MOSFET,ID=18A,0.0 PU10
288204422001 TRANS;AO4422,24mOHM,N-MOSFET,SOI PU12,PU17,PU2,PU4,U18
288204832001 TRANS;SI4832DY,N-MOSFET,.028OHM, PU16
288204912001 TRANS;AO4912,24mOHM ,SMT PU15
288221371002 TRANS;MUN2137T1,PNP,SMT,ON PQ24
288227002001 TRANS;2N7002LT1,N-CHANNEL FET,SO Q18,Q19,Q21,Q29,Q35,Q37,Q5,Q6
288227002006 TRANS;2N7002LT1,N-CHANNEL FET,ES PQ1,PQ10,PQ11,PQ12,PQ13,PQ1
291000000203 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM J2
291000000708 CON;BATTERY,7P,FM,2.5MM,BTG-07AR CON1
291000013016 CON;HDR,MA,15P*2,1MM,H4.25,ST ,SM J8
291000020204 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM
291000020222 CON;HDR,MA,2P*1,1.25MM,H4.2,ST ,S J11,J20,J6
291000020415 CON;HDR,MA,4P*1,1.25MM,ST,SMT,38 J13,J7
291000143011 CON;FPC/FFC,15P*2,.8MM,BD/BD,ST , J15
9. Spare Part List(7)
MiTac Secret
Confidentia
l Docum
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83998399 N/B MaintenanceN/B Maintenance
140
Part Number Description Location(S)291000150606 CON;FPC/FFC,6P,0.5MM,R/A,SMT J18
291000152614 CON;FPC/FFC,26P,1MM,H=2.0,R/A,SM J501
291000611255 MINIPCI SOCKET;124P,0.8MM,H=9.2, J22
291000616807 CON;PCMCIA CARD,68P,929100000140 J502
291000617542 IC SOCKET;AMD K8 BGA-PGA754-SKT, U6
291000622010 DIMM SOCKET; DDR,200P,REVERSE TY J16
291000622011 DIMM SOCKET; DDR,200P,H=9.2mm,SM J17
291000810818 CON;PHONE JACK,12P,R/A,RJ45,RJ11 J5
294011200016 LED;GREEN,H0.8,0603,CL-190G,SMT D501,D502,D503,D504,D505,D50
294011200200 LED;GREEN/RED,H0.8,W1.9,19-22SRV D510
295000010008 FUSE;1.1A,POLY SWITCH,1812,SMT F2,F3,F4
295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT PF1
295000010102 FUSE;FAST,3A,32V,1206,SMT,CERAMI PF2
295000010116 FUSE;FAST, 10A, 86VDC, 6125,SMT PF3
295000010154 FUSE;FAST,1.25A,63V,1206,SMT,043 F1
295000100004 FUSE;FAST,1A,63V,1206,THIN FILM F5
297030100015 SW;TOGGLE,SPST,5V/1mA,4P,SMT,TAI SW506
297040105010 SW;PUSH BUTTOM,5P,SPST,12V/50MA, SW1,SW501,SW502,SW503,SW50
310111103013 THERMISTOR;10K,1%,RA,DISK,103AT- RT2
310111103025 THERMISTOR;10K,1%,RA,DISK,103AT-
310111103031 THERMISTOR;10K,1%,150MM,BN35-3H1
312272263511 EC;22U,25V,20%,RA,8*10.5,105,O PC112,PC115,PC27,PC52,PC54,P
312273361501 EC;330U ,6.3V ,RA,M,6.3*7,+105C C32,C33,C384
312276806151 EC;680U ,6.3V,20%,D10,105'C,OS-C PC114
312278206151 EC;820U ,4V,+-20%,100*10.5,SP.OS PC82,PC94
Part Number Description Location(S)312278206161 EC;820U ,2.5V,+-20%,8X12.5,OS-CO PC25,PC29,PC53,PC58
314100250502 XTAL;25MHZ,30PPM,20PF,49S,11.5*3 X1
314149800402 XTAL;8MHZ,30PPM,HC-49/S,6B080002 X4
316678100001 PCB;PWA-INVERTER BD (DA-1A10-A); R0C
316684100001 PCB;PWA-8399-M BD R02
316684500001 PCB;PWA-Tarzan/BATT ,PR AND GA
323768410001 DDR SODIMM MODULE;256MB,PC3200,7
324180786803 IC;CPU,AMD-Athlon 64 3200+,OPGA,
331000000303 CON HOLDER;PCMCIA,331000000071,A
331000007038 CON;BAT,7P,2.5mm,OCT,tBTD-007001 PJ2
331000008091 CON;USB,MA,ST,4P*2,SMT,1-1470748 J3,J4,J9
331000050004 CON;CD-ROM,50P,0.8MM,H-10.4,R/A, J21
331030044021 CON;HDR,FM,22P*2,2.0MM,SMT,C1783 J14
331678100001 CONNECTOR;7 PIN,1.25mm,SMT,ACES, J1
331720015071 CON;D,FM,15P,2.29,R/A,SUYIN J2
331840005013 CON;STEREO JACK,5P,R/A,28MF60-07 J10
331840005014 CON;STEREO JACK,5P,R/A,28MF60-05 J12
331870007010 CON;MINI DIN,7P,R/A,W/GROUND,030 J1
331910002006 CON;POWER JACK,2P,20VDC,5A,DIP PJ1
332110020097 WIRE;#20,UL1007,74MM,BLACK,YIYI; CN6
332110020175 WIRE;#20,UL1007,L=103MM,RED, PWR CN10
332110020176 WIRE;#20,UL1007,70.5MM,BLACK,YIY VL-VL
332110026097 WIRE;#26,UL1007,55MM,BLACK,PRC CN8
332110026155 WIRE;26#,UL1061,L=115MM,YELLOW, CN9
332810000212 PWR CORD;125V/7A,2P,BLACK, AMERI
9. Spare Part List(8)
MiTac Secret
Confidentia
l Docum
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83998399 N/B MaintenanceN/B Maintenance
141
Part Number Description Location(S)333020000008 SHRINK TUBE;600V,125,Φ2.5mm,L
333025000004 SHRINK TUBE;300V,125,I.D=2.5,T=0
333050000120 SHRINK TUBE;600V,105'C,D0.8*9MM,
335152000044 CFM-BAT;FUSE THERMAL 98'C
335152000085 FUSE; 128 DC-7A/50V 139only UC F2
335152000094 FUSE;LR4-900,POLY SWITCH
335152000100 FUSE; THERMAL,SF91E-1/94,10A/2
338536010006 BATTERY;LI,3.6V/2.0AH,18650,PANA
339115000046 MICROPHONE;-62dB+-2dB,D6.0*H2.7, MIC501
340682900001 HOUSING ASSY;LCD,8599
340682900002 COVER ASSY;LCD,8599
340682900003 HINGE;R,8599
340682900004 HINGE;L,8599
340682900005 HINGE;R,SZS,8599
340682900006 HINGE;L,SZS,8599
340682900009 BRACKET ASSY;TOUCH-PAD,8599
340682900010 SPEAKER ASSY; 28*4.3,2W,FENG-CHI
340682900011 SPEAKER ASSY; 28*4.3,2W,VECO,859
340682900015 HOUSING ASSY;BOTTOM,8599
340682900017 COVER ASSY;CPU,8599
340682900018 COVER ASSY;MINIPCI,8599
340682900021 SHIELDING ASSY;HDD,8599
340682900022 DVD+RW BEZEL ASSY;SDW-041,8599
340684100001 COVER ASSY;TOP,8399
340684100003 SHIELDING ASSY;BOTTOM,8399
Part Number Description Location(S)340684100004 HEATSINK ASSY;CPU,K8 HAMMER,MPT,
340684100005 HEATSINK ASSY;CPU,K8 HAMMER,AVC,
340684100006 HAETSINK ASSY;SYSTEM,M/B,MPT,839
340684100007 HAETSINK ASSY;SYSTEM,M/B,AVC,839
341675300008 STANDOFF;CPU,8080 MTG501,MTG502
341682900003 BRACKET;LCD,R,8599
341682900004 BRACKET;LCD,L,8599
342502900001 CONTACT PLATE;W4L27T0.15,7068
342503200003 CONTACT PLATE;W4L18T0.15,7521/GR
342503400005 CONTACT PLATE;W5L24T0.13,7170LI,
342503400005 CONTACT PLATE;W5L24T0.13,7170LI,
342673100024 CONTACT PLATE;W5L62T0.13 ,1/3T,8
342682900009 BRACKET;ROM,8599
342682900010 CONTACT PLATE;W5L28T0.15MM,BATTE
344503100304 DUMMY;D18L65,BATT ASSY,7521C
344672300025 DUMMY CARD;PCMCIA,MANGUSTA
344682900012 COVER;HINGE,8599
344682900016 COVER;BATTERY,8599
344682900017 HOUSING;BATTERY,8599
345668900016 SPONGE;BIOS BATT,M722
345675400023 RUBBER;DOWN LCD,8355
345682900005 SPONGE;DUAL DDR,M/B,8599
345682900006 SPONGE;SPSPEND SWITCH,M/B,8599
345682900009 SPONGE;HINGE COVER,8599
346502800004 INSULATOR;BATT ASSY,BATT+,BATT-,
9. Spare Part List(9)
MiTac Secret
Confidentia
l Docum
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83998399 N/B MaintenanceN/B Maintenance
142
Part Number Description Location(S)346503100001 INSULATOR;BATT ASSY,THERMAL FUSE
346503100005 INSULATOR;5,BATTERY ASSY,7521Li
346503200202 INSULATOR;BATT ASSY,ONE ROUND,BL
346503400503 INSULATOR;BATT ASSY,W7L13,8175
346673420003 MYLAR;15*10*0.8,8640P
346677300001 INSULATOR;FIBER,UL94V-0,D=17.5mm
346678600005 INSULATOR;FIBER,UL94V-0,64X15,T=
346682900007 NYLON;BATTERY PULL,8599
346682900009 AL-FOIL;T /P BRACKET,8599
346682900010 AL-FOIL;T /P SWITCH,MB,8599
346682900013 SPONGE;M/B,8599
346682900014 INSULATOR;AL-FOIL,INVERTER,8599
346684100002 INSULATOR;CARD BUS,8399
346684100003 INSULATOR;SOUTH BRIDGE,8399
346684100004 TUBE;M/B,FOR ANTENNA,8399
346684400002 INSULATOR;RIBRE,63*15*0.25MM,BAT
347104030012 GASKET;1,04,030,012
347104030030 GASKET;1,04,030,030
347104045125 GASKET;1,04,045,125
347105020090 GASKET;1,05,020,090
347105060030 GASKET;1,05,060,030
347105060060 GASKET;1,05,060,060
347108010012 GASKET;1,08,010,012
347108080090 GASKET;1,08,080,090
347108150024 GASKET;1,08,150,024
Part Number Description Location(S)347110020025 GASKET;1,10,020,025
347110035035 GASKET;1,10,035,035
347110040012 GASKET;1,10,040,012
347110080025 GASKET;1,10,080,025
361200001018 CLEANNER;YC-336,LIQUID,STENCIL/P
361200003047 SOLDER PASTE;NO CLEAN,RMA,CK3000
361400003005 ADHESIVE;HEAT,TRANSFER,HTA-48(W)
361400003021 SOLDER CREAM;NOCLEAN,P4020870980
361400003030 ADHESIVE;ABS+PC PACK,G485,CEMIDA
370102010205 SPC-SCREW;M2L2(t0.3),N/W/WLK
370102010256 SPC-SCREW;M2L2.5,K-HD(t0.5) NLK,
370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK
370102611001 SPC-SCREW;M2.6L10,NIB,K-HD,NY
370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3
370103010414 SPC-SCREW;M3L4,KHD,NIW/NLK,D5.3,
370103010604 SPC-SCREW;M3L6,NIB,K-HD,t0.8,NYL
371102010310 SCREW;M2L3,K-HD(+),D3.8,t=0.75,N
371102010310 SCREW;M2L3,K-HD(+),D3.8,t=0.75,N
371102010610 SCREW;M2L6,K-HD(+),t0.75,NIB
371102610308 SCREW;M2.6L3,D3.5,t=0.5,K-HD,NIW
371102610406 SCREW;M2.6L4,K-HEAD(+),NIB
371102610607 SCREW;M2.6L6,K-HEAD(+),NIB
373101712351 T-SCREW;B,M1.7,L2.35,K-HD,2,NIB
377102650901 S-STANDOFF;M2.6DP3.5H9L1.1,NIW MTG3,MTG4
377102651002 S-STANDOFF;M2.6DP5H12.5L4,NIW,NY
9. Spare Part List(10)
MiTac Secret
Confidentia
l Docum
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83998399 N/B MaintenanceN/B Maintenance
143
Part Number Description Location(S)377244010002 STANDOFF;#4-40DP3.5H5L5.5,NIW
411678100001 PWA;PWA-INVERTER BD,DA-1A10-A,PW
411678100002 PWA;PWA-INVERTER BD,SMT,DA-1A10-
411684110001 PWA;PWA-8399-MAX,MOTHER BD
411684110002 PWA;PWA-8399-MAX,MOTHER BD,T /U
411684110003 PWA;PWA-8399-MAX,MOTHER BD,SMT
411684430001 PWA;PWA-BATT,PCB BD,LI,4.0Ah,BL4
411684430002 PWA;PWA-BATT,PCB BD,SMT,4.0Ah,BL
412681400001 PCB ASSY;WIRELESS LAN CARD,MINI
412684100001 CFM-Medion; PCB ASSY;FAX MODEM 5
412684110001 FAX MODEM KIT ;Creatix,8399-MAX I
413000020433 LCD;LTN150XB- L03,15",XGA,SAMSUN
416268411001 LT PF;15",XGA,SAMSUNG,8399-MAX I
421675400012 WIRE ASSY;BIOS,BATTERY,8355
421682900001 WIRE ASSY;LTN150XB-L03,8599
421682900011 WIRE ASSY;LTN150XB-L03,GREATLAND
421684100003 WIRE ASSY,MDC-MODEM,4-4PIN,8399
421684100005 WIRE ASSY;ANTENNA,WHA-YU,8399
421684110001 ANTENNA OPTION;8399 ID1
422682900001 FFC ASSY;TOUCH-PAD,TENN-RICH,859
422682900002 FFC ASSY;TOUCH-PAD,HONG-FU,8599
422682900003 FFC ASSY;TOUCH-PAD,CEI,8599
431684110001 CASE KIT;Creaxtix,8399-MAX
441684110001 LCD ASSY;15",XGA,SAMSUNG,8399 ID
441684400003 BATT ASS'Y;11.1V,4.0Ah,LI,BL-424
Part Number Description Location(S)441684400006 CONTACT PLATE ASSY;PTC,S-TUBE,BL
441684400010 CONTACT PLATE ASSY;W5L45T0.13,FU
441684430003 BATT ASSY;11.1V,4.0Ah,LI,CASE CL
441684430004 BATT ASSY;11.1V,4.0Ah,LI,CORE PA
442678800002 CFM Medion AC ADPT ASSY;19V,4.74
442680900051 TOUCHPAD MODULE;SYNAPTICS,TM42PU
451682900001 HDD ME KIT ;8599
451682900002 LCD ME KIT;15",XGA,SAMSUNG,8599
451682900005 ROM ME KIT;8599
451684110002 HOUSING KIT;8399 ID1
451684110004 LABEL KIT;N-B,8399
461677400001 PACKING KIT ;DA-1A05-A;PWR
461682900002 PACKING KIT ;COMPACT,N-B,8599
481684100002 F/W ASSY;KBD CTRL,8399 U16
481684110001 F/W ASSY;SYS/VGA BIOS,8399-MAX U25
523405320072 HDD DRIVE,40GB,2.5",IC25N040ATMR
523430061910 DVD+RW DRIVE;SDW-041,QSI
523468290001 DVD+RW ASSY;SDW-041,8599
523468290004 HDD ASSY;Hitachi,IC25N040ATMR04,
526268411004 LTXNX;8399/5SHE/40N/1UIX/B2X2A/X
531020237940 KBD;88,UI,K011818G1,8599
600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC
600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC
600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC
624200010140 LABEL;5*20,BLANK,COMMON
9. Spare Part List(11)
MiTac Secret
Confidentia
l Docum
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83998399 N/B MaintenanceN/B Maintenance
144
Part Number Description Location(S)624200010140 LABEL;5*20,BLANK,COMMON
P/N:526268411004
9. Spare Part List(12)
MiTac Secret
Confidentia
l Docum
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MiTac Secret
Confidentia
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN FOR EVT
18
Cardbus Controller
TAPEOUT DAY
NB VIA_K8N800 (1/2)
HISTORY
DIMM-SLOT & Termination
8
3V/5V(LTC3728)
+1.5V&+1.2V(SC338)
DESIGN
19
NB VIA_K8N800 (2/2)
4ClawHammer_Power plane(2/2) 3
26
SB VIA_VT8235CD (1/3)
15
Page
9
USB2.0 & Flash ROM
SB VIA_VT8235CD (2/3)
ClawHammer_HT&DDR(1/2)
16
POWER ON PERPHERIAL CIRCUIT
24
COVER SHEET & SCREW HOLE
MODEL : 8399
Charging (TL594C)ADINP & Discharge
2003/01/03
7
KBC(W83L950D)
23
+1.25V(LP2996)&+2.5V(RT9202)
R00
LVDS Encoder & connector
17
20
11
CPU core ( ISL6559 )
Contexts
LAN PHY
REVISION
1
SB VIA_VT8235CD (3/3)
13
25
22
Title
Revision 03
2
CHECK
21
6
Mini PCI Interface
10
DRAWN
Clock Generator
14
Audio CODEC
TV Encoder & VGA Interface
5
12
ISSUES
For CPU
For PCMCIA
For MDC
For 2nd FAN
HDD & CD_ROM Conntor
R03 2004/05/201.Connect CPU AF_18 to VDDIO ba se on Errata 108.2.Change LDTSTOP pull high resistor location.3.Add level shift circuit for ENPBLT from K8N800.4.Add R436 pull high resistor for VT8235CD hardwar e strap pin SPKR.5.Change R287 from 6.19K to 5.6K for USB2.0 eye pattern fail issue .6.Remove AMS2951 but add a MOSFET between AMS3107 and +SVDD3 for costissue.
R02 1.Add AMS2951 for KBC_VREF to solve battery not accuracy issue.
411684100001 R03
<Title>
C
1 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
GND_MDC
GND_USB
AGND
GND_USB
TP527TOUCHPAD_METAL12
1
MTG502ID4.5/OD7.0
456
7 9
10
1238
111213
MTG20ID3.0/OD7.0
MTG118_RD30X12MTG118-RD276-30X12
456
7 9
10
1238
111213
MTG3MTG/ID2.1/OD5.0
456 7 9 10
1238
FD502FIDUCIAL-MARK
1
MTG10ID3.2/OD8.0/IN4.5
1
TP503TOUCHPAD_METAL12
1FD503FIDUCIAL-MARK
1
MTG12ID3.2/OD8.0
1
MTG13ID3.2/OD8.0
1
FD2FIDUCIAL-MARK
1
FD504FIDUCIAL-MARK
1
MTG14ID3.0/OD7.0
456
7 9
10
1238
1112
FD501FIDUCIAL-MARK
1
MTG11ID3.2/OD8.0/IN4.5
1
FD4FIDUCIAL-MARK
1
MTG7ID3.0/OD7.0
MTG118_RD30X12MTG118-RD276-30X12
456
7 9
10
1238
111213
MTG16ID3.0/OD5.2
4
5 6
7
12
3 8
9
MTG6ID3.0/OD7.0
MTG118_RD30X12MTG118-RD276-30X12
456
7 9
10
1238
111213
MTG19ID3.0/OD7.0
MTG118_RD30X12MTG118-RD276-30X12
456
7 9
10
1238
111213
MTG501ID4.5/OD7.0
456
7 9
10
1238
111213
TP504TOUCHPAD_METAL12
1
MTG5ID3.0/OD7.0
MTG118_RD30X12MTG118-RD276-30X12
456
7 9
10
1238
111213
FD1FIDUCIAL-MARK
1
MTG9ID3.0/OD7.0
MTG118_RD30X12MTG118-RD276-30X12
456
7 9
10
1238
111213
MTG8ID3.0/OD7.0
MTG118_RD30X12MTG118-RD276-30X12
456
7 9
10
1238
111213
TP502TOUCHPAD_METAL12
1
FD3FIDUCIAL-MARK
1
MTG15ID3.0/OD7.0
456
7 9
10
1238
1112
MTG4MTG/ID2.1/OD5.0
456 7 9 10
1238
MTG18ID3.0/OD7.0
456
7 9
10
1238
1112
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
R335不能離開CPU超過 0.5inch
Place thesecapacitors close toprocessor pins
E14-RESERVEMEMADDB15
width:20/8/5/8/20
C12-RESERVEMEMADDA14
resistor mustno more than1000mil fromprocessor and5mils trace and10mil spacing
Change to 34.8 Ohm
ClawHammer-HT&DDR(1/2)
E13-RESERVEMEMADDA15
width:20/5/5/5/20
須用NPO
D12-RESERVEMEMADDB14
HDT USE
HDT USE
Remove resistors
<Doc> R03
<Title>
C
2 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
L0_CADIN_H14
BP2
L0_CADIN_H0
CPU_THERMTRIP#
L0_CTLIN_H1
NC_AF22L0_CADIN_L1
L0_CADOUT_H13
L0_CADIN_H[0..15]
NC_AE23
L0_REF1
L0_CADOUT_H14
L0_CADIN_H12
DDR_CLK5
DDR_CLK4#
L0_CADIN_H3
NC_AE23
CPU_PWROK_2.5V
TDO
L0_CTLIN_H0
CPUCK-
L0_CADIN_H10
CPU_THERMTRIP#
L0_CADIN_L13
BP0
DDR_CLK4
CPU_THERMDA
L0_CADIN_H6
CPU_CKEA
L0_CADOUT_H15
L0_CADOUT_H5
DDR_WEA#
MEMZN
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_H2DDR_CLK6
CPU_RESET#
L0_CADIN_H8
L0_CADOUT_L6
L0_CADIN_L3
L0_CADOUT_H8
L0_CTLOUT_H0
L0_CADOUT_L15
DDR_CLK7#
L0_CADOUT_H6
L0_CADOUT_L2
CPUCK+
CPUCK-
DDR_CLK0
L0_CADOUT_H2
L0_CADOUT_H0
DDR_CLK0#
L0_CADOUT_H10
DDR_CLK1#
TMS
CPU_CS3#
L0_CTLOUT_H1
TDI
NC_AF21
L0_CTLIN_L0
CPU_PWROK_2.5V
L0_CADIN_H1
SCANEN
DDR_CLK3
BPSCLK+
L0_CADOUT_H7
CPU_CKEB
L0_CADIN_H4
L0_CADOUT_L9
L0_CADOUT_L7
DDR_CLK6#
L0_CADIN_H7
L0_CADOUT_H11
CPU_CS0#
L0_CADIN_H11
BPSCLK+
L0_CADIN_L14L0_CADIN_L15
L0_CTLIN_L1
SINCHN
L0_CADIN_H15
DDR_CLK0#
BPSCLK-
L0_CADIN_L11
L0_CLKIN_H1
L0_CADOUT_L11
L0_CADIN_L[0..15]
DDR_CLK4#
MEMRESET_LL0_CADOUT_L4
L0_CADIN_H13
L0_CADIN_L2
BPSCLK-
L0_CADIN_L10
L0_CADOUT_H3
L0_CADIN_L12
L0_CADOUT_H12
DDR_CLK1
SCANCLK2
CPUCK+
L0_CLKOUT_L1
DBRDY
L0_CADOUT_L[0..15]
L0_CADOUT_H[0..15] DDR_CLK1SCANSHENA
CPU_RESET#
L0_CTLIN_H1
DDR_CLK7
L0_CADOUT_L13
L0_CLKOUT_L0
CPU_MD[0..63]
DDR_CLK5#
L0_CADOUT_L3
L0_CADIN_L5
BRN#
REFB_HL0_CLKIN_L0
L0_CLKOUT_H1
SINCHN
REFB_L
LDTSTOP1#
DDR_CLK7#
SCANCLK2
L0_REF0
L0_CTLOUT_L0
SCANEN
L0_CADOUT_L8
L0_CTLOUT_L1
L0_CADOUT_L14
SCANSHENB
DDR_CLK2
TCK
L0_REF0
L0_CADIN_L0
CPU_CS2#
NC_AF23
CPU_CS1#
L0_CLKOUT_H0
DDR_CLK6#
BP1
BP0
L0_CADOUT_H9
L0_CADIN_H9
TRST#
NC_AF22NC_AF23
BP3
L0_CLKIN_H0
BRN#
MEMZP
CPU_THERMDC
L0_CADOUT_L1
SCANSHENB
DDR_RASA#
DDR_CLK1#
DDR_CLK5
SCANCLK1
L0_CADIN_L8L0_CADIN_L7
L0_CADOUT_L12
L0_CADIN_L4
SCANCLK1
DDR_CLK7
L0_CADOUT_L5
L0_CADOUT_L0
L0_CADOUT_L10
L0_CADOUT_H4
L0_CTLIN_L1
NC_AF21
BP1
L0_CADIN_L9
DDR_CLK0
DDR_CLK2#
DDR_CLK5#
DDR_CLK6
L0_REF1
DDR_CLK3#
L0_CADOUT_H1
DBREQ#
SCANSHENA
DDR_CLK4
L0_CLKIN_L1
CPU_MD38
CPU_MD19
CPU_MD17
CPU_DQM5
CPU_MD44
CPU_MD58
CPU_MD33
CPU_MD11
CPU_MD62
CPU_MD56
CPU_MD49
CPU_MD45
CPU_MD18
CPU_MD14
CPU_MD3
CPU_MD34
CPU_MD27
CPU_MD16
CPU_MD0
MEMADD_A9
CPU_DQM7
CPU_MD4
MEMADD_A8
MEMADD_A3
CPU_DQS6CPU_DQS5CPU_DQS4
CPU_MD57
CPU_MD30
CPU_MD12MEMADD_A12
CPU_DQS3
MEMADD_A10
CPU_DQS7
CPU_MD43
CPU_MD9
CPU_MD2
CPU_MD23
CPU_MD55
CPU_MD6
CPU_MD52
MEMADD_A2
MEMADD_A0
CPU_MD5
CPU_MD28
CPU_MD22
CPU_MD8
CPU_MD32
MEMADD_A4
CPU_MD10
CPU_DQM1CPU_DQM0
CPU_MD47
CPU_MD41CPU_MD42
CPU_MD25
CPU_MD37
CPU_MD7
CPU_MD1
MEMZP
MEMADD_A7
CPU_MD61
CPU_MD24
CPU_MD60CPU_MD59
MEMADD_A[0..13]
CPU_DQS[0..7]
CPU_MD15
CPU_MD35
CPU_MD51
CPU_MD46
CPU_DQM2
CPU_DQS2
CPU_DQM3
CPU_MD36
MEMADD_A6
CPU_MD40
CPU_DQM4
MEMADD_A1
CPU_MD20
CPU_MD50
MEMADD_A5
CPU_MD29
CPU_DQS1
CPU_MD39
CPU_MD63
CPU_MD48
CPU_MD31
MEMADD_A11
MEMADD_A13
CPU_MD26
CPU_DQM6
CPU_MD13
CPU_DQS0
CPU_MD54CPU_MD53
CPU_MD21
MEMZN
MEMADD_B12
MEMADD_B2
MEMADD_B7
MEMADD_B5
MEMADD_B13
MEMADD_B[0..13]
MEMADD_B1
MEMADD_B4
MEMADD_B10MEMADD_B9
MEMADD_B0
MEMADD_B3
MEMADD_B11
MEMADD_B6
MEMADD_B8
DDR_RASB#
DDR_WEB#
TMS
DBREQ#
TRST#TDI
DBRDY
TDO
TCK
LDTSTOP1#
+2.5VS_DDR
GND
GND
GND
+2.5VS_DDR
GND
GND
GND
GND
GND
+2.5V
+1.2VLDTB
+2.5VS_DDR
+1.25VSREF_MEM
GND
+1.2VLDTA
+1.25VSREF_CLAW
GND
+2.5VS_DDR
+2.5V
+1.25VSREF_CLAW
+1.25VSREF_CLAW
GND
GND
+2.5V
+2.5VS_DDR
+2.5VS_DDR
+2.5VS_DDR
R118 820 04021%1 2
R148 680 04021 2
C1520.01U0402
50V10%
12
R26110004021%
12
R209 120 04025%1 2
R150 680 04025%1 2
TP506 1
TP5211
C103 3900P0603
1 2
R18110004021%
12
C1510.1U0402
16V10%
12
TP5181
R10044.2
0603
1%1 2
C107 3900P0603
1 2
R114 820 04021%1 2
R851470/NA06031%
12
TP5261
R18034.8
0603
1%1 2
R147 0 04021 2
TP5091
R125 680/NA 04021 2
R207 120 04025%1 2
TP536 1
R139 680 04025%1 2
C140 4.7U0805
1 2
R101 49.9 04021%1 2
TP525 1
C137 0.22U0402
1 2
R107 49.9 04021%1 2
C1381000P0402
50V10%
12
R131 680 04025%1 2
TP520 1
C40 1000P0402 50V 10%
1 2
C2580.1U0402
16V10%
12
TP516 1
R167 680 04025%1 2
R96 0/NA 04021 2
R135 680 04021 2
R854470/NA06031%
12
R849470/NA06031%
12
R210 120 04025%1 2
TP4 1
C1500.01U0402
50V10%
12
TP5141
TP5281
TP5071
R104 680/NA 04021 2
TP5151
TP5081
TP5381
TP5331
TP5301
R138 680 04025%1 2
TP5171
TP513 1
R155 680 04025%1 2
TP5291
R848470/NA06031%
12
TP51
R17434.8
0603
1%1 2
TP5311
R161 680 04021 2
R183 120 04025%1 2
R160 0 04021 2
R97 680 04021 2
TP5221
R13216906031%
12
C2370.1U0402
16V10%
12
C2501000P0402
50V10%
12
C1590.1U0402
16V10%
12
R152 680 04025%1 2
R103 680/NA 04021 2
C82 1000P0402 50V 10%
1 2
TP511 1
R850470/NA06031%
12
U6A
CLAWHAMMERBGA754_SKT291000617542BGA754_SKT
AJ21AH21
B23A23A24
AH17
AJ28A28
AE19AH19AJ19
AD27AD29AB27AB29
Y29V27V29T27
AD25AC27AB25AA27W27V25U27T25
AD28AC29AB28AA29W29V28U29T28
AC25AC26AA25AA26W26U25U26R25
E29F28G29H28K28L29
M28N29E26E25G26G25J25L26L25N26
F29F27H29H27K27M29M27P29E27F25G27H25K25L27
M25N27
Y27Y25Y28W25J29J26K29J27T29R27R29R26P28N25P27P25
AE26AF27AJ27
A19A25AA2AA3AE21AE22AE23AE24AE9AF18AF21AF22AF23AF24AG17AG18AG2AG4AG6AG7AG9AH1AH18AH23AJ18AJ23B13B18B19B7C1C12C15C18C19C20C21C22C23C24C3C6C9D12D18D20D22D3E13E14F3J3K1R2R3
E17A21A22A26A27A20E20B21AE18AF20
CLKIN_HCLKIN_LCORE_SENSECOREFB_HCOREFB_LDBRDY
KEY0KEY1
DBREQ_LFBCLKOUT_HFBCLKOUT_L
L0_CADIN_H[0]L0_CADIN_H[1]L0_CADIN_H[2]L0_CADIN_H[3]L0_CADIN_H[4]L0_CADIN_H[5]L0_CADIN_H[6]L0_CADIN_H[7]L0_CADIN_H[8]L0_CADIN_H[9]L0_CADIN_H[10]L0_CADIN_H[11]L0_CADIN_H[12]L0_CADIN_H[13]L0_CADIN_H[14]L0_CADIN_H[15]
L0_CADIN_L[0]L0_CADIN_L[1]L0_CADIN_L[2]L0_CADIN_L[3]L0_CADIN_L[4]L0_CADIN_L[5]L0_CADIN_L[6]L0_CADIN_L[7]L0_CADIN_L[8]L0_CADIN_L[9]L0_CADIN_L[10]L0_CADIN_L[11]L0_CADIN_L[12]L0_CADIN_L[13]L0_CADIN_L[14]L0_CADIN_L[15]
L0_CADOUT_H[0]L0_CADOUT_H[1]L0_CADOUT_H[2]L0_CADOUT_H[3]L0_CADOUT_H[4]L0_CADOUT_H[5]L0_CADOUT_H[6]L0_CADOUT_H[7]L0_CADOUT_H[8]L0_CADOUT_H[9]L0_CADOUT_H[10]L0_CADOUT_H[11]L0_CADOUT_H[12]L0_CADOUT_H[13]L0_CADOUT_H[14]L0_CADOUT_H[15]
L0_CADOUT_L[0]L0_CADOUT_L[1]L0_CADOUT_L[2]L0_CADOUT_L[3]L0_CADOUT_L[4]L0_CADOUT_L[5]L0_CADOUT_L[6]L0_CADOUT_L[7]L0_CADOUT_L[8]L0_CADOUT_L[9]L0_CADOUT_L[10]L0_CADOUT_L[11]L0_CADOUT_L[12]L0_CADOUT_L[13]L0_CADOUT_L[14]L0_CADOUT_L[15]
L0_CLKIN_H[0]L0_CLKIN_H[1]L0_CLKIN_L[0]L0_CLKIN_L[1]
L0_CLKOUT_H[0]L0_CLKOUT_H[1]L0_CLKOUT_L[0]L0_CLKOUT_L[1]
L0_CTLIN_H[0]L0_CTLIN_H[1]L0_CTLIN_L[0]L0_CTLIN_L[1]
L0_CTLOUT_H[0]L0_CTLOUT_H[1]L0_CTLOUT_L[0]L0_CTLOUT_L[1]
L0_REF0L0_REF1
LDTSTOP_L
NC_A19NC_A25NC_AA2NC_AA3
NC_AE21NC_AE22NC_AE23NC_AE24NC_AE9
NC_AF18NC_AF21NC_AF22NC_AF23NC_AF24NC_AG17NC_AG18NC_AG2NC_AG4NC_AG6NC_AG7NC_AG9NC_AH1
NC_AH18NC_AH23NC_AJ18NC_AJ23NC_B13NC_B18NC_B19NC_B7NC_C1
NC_C12NC_C15NC_C18NC_C19NC_C20NC_C21NC_C22NC_C23NC_C24NC_C3NC_C6NC_C9
NC_D12NC_D18NC_D20NC_D22NC_D3
NC_E13NC_E14
NC_F3NC_J3NC_K1NC_R2NC_R3
TCKTDI
TDOTHERMDATHERMDC
THERMTRIP_LTMS
TRST_LPWROK
RESET_L
R159 680 04025%1 2
U6B
CLAWHAMMERBGA754_SKT
N5T3T5V5Y3
AB4Y5
AD3AB5AE5M5
AF3AE6E10
M3T4U5
W5Y4
AB3AA5AD4AC5AD5M4
AF4AF6
E9
H3K3J5L5
D4F5
U2U1P1N2V1U3N1N3
AE8AE7
P3R5K5V3
AF10AF8E12D10
P4P5K4V4
AE10AG8E11C10
E5C4E6D6E7E8C8D8
AJ16AJ14AJ12AG11AJ15AH15AJ11AH11AJ10AJ9AH5AG5AH9AJ7AJ6AJ5AJ3AH3AF1AE2AJ4AG3AE3AE1AD1AC2Y1W2AC3AC1W3W1M1L2J2G3L1L3G1G2F1E3B3A3E1E2A4C5B5A5A9C11A6C7B9A10A11C13A15A17B11A12B15A16
AJ13AJ8AJ2AB1J1D1A8A14T1AH13AH7AG1AA1H1C2A7A13R1
H5H4
AG10AG12
G5F4
D14C14
MEMADDA[0]MEMADDA[1]MEMADDA[2]MEMADDA[3]MEMADDA[4]MEMADDA[5]MEMADDA[6]MEMADDA[7]MEMADDA[8]MEMADDA[9]MEMADDA[10]MEMADDA[11]MEMADDA[12]MEMADDA[13]
MEMADDB[0]MEMADDB[1]MEMADDB[2]MEMADDB[3]MEMADDB[4]MEMADDB[5]MEMADDB[6]MEMADDB[7]MEMADDB[8]MEMADDB[9]MEMADDB[10]MEMADDB[11]MEMADDB[12]MEMADDB[13]
MEMBANKA[0]MEMBANKA[1]MEMBANKB[0]MEMBANKB[1]
MEMCASA_LMEMCASB_L
MEMCHECK[0]MEMCHECK[1]MEMCHECK[2]MEMCHECK[3]MEMCHECK[4]MEMCHECK[5]MEMCHECK[6]MEMCHECK[7]
MEMCKEAMEMCKEBMEMCLK_H[0]MEMCLK_H[1]MEMCLK_H[2]MEMCLK_H[3]MEMCLK_H[4]MEMCLK_H[5]MEMCLK_H[6]MEMCLK_H[7]
MEMCLK_L[0]MEMCLK_L[1]MEMCLK_L[2]MEMCLK_L[3]MEMCLK_L[4]MEMCLK_L[5]MEMCLK_L[6]MEMCLK_L[7]
MEMCS_L[0]MEMCS_L[1]MEMCS_L[2]MEMCS_L[3]MEMCS_L[4]MEMCS_L[5]MEMCS_L[6]MEMCS_L[7]
MEMDATA[0]MEMDATA[1]MEMDATA[2]MEMDATA[3]MEMDATA[4]MEMDATA[5]MEMDATA[6]MEMDATA[7]MEMDATA[8]MEMDATA[9]
MEMDATA[10]MEMDATA[11]MEMDATA[12]MEMDATA[13]MEMDATA[14]MEMDATA[15]MEMDATA[16]MEMDATA[17]MEMDATA[18]MEMDATA[19]MEMDATA[20]MEMDATA[21]MEMDATA[22]MEMDATA[23]MEMDATA[24]MEMDATA[25]MEMDATA[26]MEMDATA[27]MEMDATA[28]MEMDATA[29]MEMDATA[30]MEMDATA[31]MEMDATA[32]MEMDATA[33]MEMDATA[34]MEMDATA[35]MEMDATA[36]MEMDATA[37]MEMDATA[38]MEMDATA[39]MEMDATA[40]MEMDATA[41]MEMDATA[42]MEMDATA[43]MEMDATA[44]MEMDATA[45]MEMDATA[46]MEMDATA[47]MEMDATA[48]MEMDATA[49]MEMDATA[50]MEMDATA[51]MEMDATA[52]MEMDATA[53]MEMDATA[54]MEMDATA[55]MEMDATA[56]MEMDATA[57]MEMDATA[58]MEMDATA[59]MEMDATA[60]MEMDATA[61]MEMDATA[62]MEMDATA[63]
MEMDQS[0]MEMDQS[1]MEMDQS[2]MEMDQS[3]MEMDQS[4]MEMDQS[5]MEMDQS[6]MEMDQS[7]MEMDQS[8]MEMDQS[9]
MEMDQS[10]MEMDQS[11]MEMDQS[12]MEMDQS[13]MEMDQS[14]MEMDQS[15]MEMDQS[16]MEMDQS[17]
MEMRASA_LMEMRASB_LMEMRESET_LMEMVEF1MEMWEA_LMEMWEB_LMEMZNMEMZP
R18410004021%
12
C2660.047U
16V0603
10%
12
R416 0 04021 2
TP5101
R153 680 04025%1 2
R151 80.60603 1%
12
TP537 1
TP5321
R852470/NA06031%
12
R186 120 04025%1 2
R3044.2
0603
1%1 2
TP5191
J503
FPC/FFC-12P/0.5MM/NA6239-012-001-800
CONN_ELCO6239_12291000151201
123456789
101112
123456789101112
C1390.33U0402
16V+80-20%
12
R208 120 04025%1 2
TP512 1
R23510004021%
12
R853470/NA06031%
12
R126 680/NA 04021 2
COREFB_H25COREFB_L25
L0_CADIN_H[0..15]6
L0_CADIN_L[0..15]6
L0_CADOUT_H[0..15]6
L0_CADOUT_L[0..15]6
L0_CLKIN_H0 6L0_CLKIN_H1 6L0_CLKIN_L0 6L0_CLKIN_L1 6L0_CLKOUT_H0 6L0_CLKOUT_H1 6L0_CLKOUT_L0 6L0_CLKOUT_L1 6L0_CTLIN_H0 6
L0_CTLIN_L0 6
L0_CTLOUT_H0 6
L0_CTLOUT_L0 6
LDTSTOP# 6,10
CPU_RESET# 3CPU_PWROK_2.5V 20
CPU_THERMTRIP# 20CPU_THERMDC 5CPU_THERMDA 5
MEMADD_A[0..13]4
DDR_BAA04DDR_BAA14
DDR_CASA#4
CPU_CKEA4CPU_CKEB4
DDR_CLK54DDR_CLK64DDR_CLK74
DDR_CLK4#4DDR_CLK5#4DDR_CLK6#4DDR_CLK7#4
CPU_CS3#4
CPU_CS1#4CPU_CS2#4
CPU_CS0#4
CPU_MD[0..63] 4
CPUCLK+ 5
CPUCLK- 5
CPU_DQS[0..7] 4
CPU_DQM[0..7] 4
DDR_RASA#4
DDR_WEA#4
MEMADD_B[0..13]4
DDR_BAB04DDR_BAB14
DDR_CASB#4
DDR_RASB#4
DDR_WEB#4
DDR_CLK44
LDTSTOP_NB# 6
DDR_CLK14DDR_CLK04
DDR_CLK1#4DDR_CLK0#4
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MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Near CPU within in VLDT pour*4
Place HTbypass capson topsidenearunconnectedClawhammerHT link
Near NB within1 inch*4
ClawHammer-Power plane(2/2)
Place these capacitors near socket
<Doc> R03
<Title>
C
3 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
PG_+1.25VS_P
PG_+1.25VS_P
GND
+2.5VDDA
+1.2VLDTB
GND
+3V
GND
+1.2VLDTA
+VCC_CORE
GND
+1.2VLDTA
+VCC_CORE
GND
GND
GND
+3V
+1.2VLDTA
GND
+2.5VDDA
GND
GND
+VCC_CORE
+2.5VS_DDR
+1.25VTT
+1.25VTT
+3VS
GNDGNDGND
+3V
GND
+2.5V
+2.5V
GND
+VCC_CORE
DS
Q72N7002G
DS
C964.7U0805+80-20%
12
C672 10U6.3V 0805
1 2
R417 0 04021 2
U7
AME8804AEEYSOT26
1
2
3
4 5
6VIN
GN
D
EN
PG ADJ
VOUT
R1 Q8DTC144TKA
2
13
U22A
74HCT08_VTSSOP14
1
23
147
R38647K04025%
12
R1338.87K06031%
12
C114100P0402
50V+/-10%
12
R171 0 04021 2
C673 10U6.3V 0805
1 2
C116 0.22U16V 0603
1 2
R175 0 04021 2
C91 0.22U16V 060310%,X7R
12
R370 0 04021 2
C108 0.22U16V 060310%,X7R
12
C97 0.22U16V 060310%,X7R
12
C90 0.22U16V 060310%,X7R
12
C403 0.22U16V 0603
1 2
C405 0.22U16V 0603
1 2
C402 0.22U16V 0603
1 2
R3888.2K0603
12
C115 10U6.3V 0805
1 2
TP5241
R4118.2K04025%
12
C404 0.22U16V 0603
1 2
C3751U0603
12
TP5231
C10010U080510V+80-20%
12
R383 0/NA 04021 2
R187 0 04021 2
C126 10U6.3V 0805
1 2
C117 0.22U16V 0603
1 2
C414.7U120610%
12
C31 0.22U16V 060310%,X7R
12
C830.22U
16V
060310%,X7R
12
L34120Z/100M2012
12
C15 0.22U16V 060310%,X7R
12
C95 0.22U16V 060310%,X7R
12
C127 10U6.3V 0805
1 2
C16 0.22U16V 060310%,X7R
12
C125 10U6.3V 0805
1 2
R36910K04025%
12
U6C
CLAWHAMMERBGA754_SKT
B20B24D24E19E21E23E28F18F20F22F24F26G11G13G15G17G19G21G23H10H12H14H16H18H20H22H24
J9J11J13J15J17J19J21J23J28K8
K10K12K14K16K18K20K22K24K26
L7L9
L21L23M8
M10M20M22M24
N7N9
N21N23N28
P8P10P20P22P24P26R7R9
R21R23
T8T10T20T22T24U7U9
U21U23U28
V8V10V20V22V24V26W7W9
W21W23
Y8Y10Y12Y14Y16Y18Y20Y22Y24AA9
AA11
AA13AA15AA17AA19AA21AA23AA28AB10AB12AB14AB16AB18AB20AB22AB24AB26AC11AC13AC15AC17AC19AC21AC23AD18AD20AD22AD24AE17AE25AE27AG19AH24
AH25AJ25
D5D7D9D11D13D15E4F6F8F10F12F14F16G4G7G9H6H8J4J7K6L4M6N4P6R4T6U4V6W4Y6AA4AA7AB6AB8AC4AC7AC9AD6AD8AD10AD12AD14AD16AE4AF11AF13AF5AF7AF9
AE12AF12
AE11
B27B29C26C28D25D27D29AF25AE28AF29AG26AG28AH27AH29
AE15AF15AG14AF14AG13
VDD_0VDD_1VDD_2VDD_3VDD_4VDD_5VDD_6VDD_7VDD_8VDD_9VDD_10VDD_11VDD_12VDD_13VDD_14VDD_15VDD_16VDD_17VDD_18VDD_19VDD_20VDD_21VDD_22VDD_23VDD_24VDD_25VDD_26VDD_27VDD_28VDD_29VDD_30VDD_31VDD_32VDD_33VDD_34VDD_35VDD_36VDD_37VDD_38VDD_39VDD_40VDD_41VDD_42VDD_43VDD_44VDD_45VDD_46VDD_47VDD_48VDD_49VDD_50VDD_51VDD_52VDD_53VDD_54VDD_55VDD_56VDD_57VDD_58VDD_59VDD_60VDD_61VDD_62VDD_63VDD_64VDD_65VDD_66VDD_67VDD_68VDD_69VDD_70VDD_71VDD_72VDD_73VDD_74VDD_75VDD_76VDD_77VDD_78VDD_79VDD_80VDD_81VDD_82VDD_83VDD_84VDD_85VDD_86VDD_87VDD_88VDD_89VDD_90VDD_91VDD_92VDD_93VDD_94VDD_95VDD_96VDD_97VDD_98VDD_99VDD_100
VDD_101VDD_102VDD_103VDD_104VDD_105VDD_106VDD_107VDD_108VDD_109VDD_110VDD_111VDD_112VDD_113VDD_114VDD_115VDD_116VDD_117VDD_118VDD_119VDD_120VDD_121VDD_122VDD_123VDD_124VDD_125VDD_126VDD_127VDD_128VDD_129VDD_130VDD_131VDD_132
VDDA1VDDA2
VDDIO_0VDDIO_1VDDIO_2VDDIO_3VDDIO_4VDDIO_5VDDIO_6VDDIO_7VDDIO_8VDDIO_9
VDDIO_10VDDIO_11VDDIO_12VDDIO_13VDDIO_14VDDIO_15VDDIO_16VDDIO_17VDDIO_18VDDIO_19VDDIO_20VDDIO_21VDDIO_22VDDIO_23VDDIO_24VDDIO_25VDDIO_26VDDIO_27VDDIO_28VDDIO_29VDDIO_30VDDIO_31VDDIO_32VDDIO_33VDDIO_34VDDIO_35VDDIO_36VDDIO_37VDDIO_38VDDIO_39VDDIO_40VDDIO_41VDDIO_42VDDIO_43VDDIO_44VDDIO_45VDDIO_46VDDIO_47VDDIO_48VDDIO_49
VDDIOFB_HVDDIOFB_L
VDDIO_SENSE
VLDT0_A0VLDT0_A1VLDT0_A2VLDT0_A3VLDT0_A4VLDT0_A5VLDT0_A6VLDT0_B0VLDT0_B1VLDT0_B2VLDT0_B3VLDT0_B4VLDT0_B5VLDT0_B6
VID[0]VID[1]VID[2]VID[3]VID[4]
U6D
BGA754_SKTCLAWHAMMER
B2B4B6B8
B10B12B14B16B22B25B26B28C25C27C29D2
D16D19D21D23D26D28E15E16E18E22E24
F2F7F9
F11F13F15F17F19F21F23G6G8
G10G12G14G16G18G20G22G24G28
H2H7H9
H11H13H15H17H19H21H23H26
J6J8
J10J12J14J16J18J20J22J24K2K7K9
K11K13K15K17K19K21K23
L6L8
L10L20L22L24L28M2M7M9
M21M23M26
N6N8
N10N20N22N24
P2P7P9
P21P23R6R8
R10R20R22R24R28
T2T7T9
T21T23T26
U10U20U22U24V2V7V9V21V23W6W8W10W20W22W24W28Y2Y7Y9Y11Y13Y15Y17Y19Y21Y23Y26AA6AA8AA10AA12AA14AA16AA18AA20AA22AA24AB2AB7AB9AB11AB13AB15AB17AB19AB21AB23AC6AC8AC10AC12AC14AC16AC18AC20AC22AC24AC28AD2AD7AD9AD11AD13AD15AD17AD19AD21AD23AD26AE14AE16AE20AE29AF2AF17AF19AF26AF28AG20AG21AG22AG23AG24AG25AG27AG29AH2AH4AH6AH8AH10AH12AH14AH20AH22AH26AH28AJ20AJ22AJ24AJ26
A18B17C16C17D17AF16AG15AG16AH16AJ17
AE13
U6U8VSS_0
VSS_1VSS_2VSS_3VSS_4VSS_5VSS_6VSS_7VSS_8VSS_9VSS_10VSS_11VSS_12VSS_13VSS_14VSS_15VSS_16VSS_17VSS_18VSS_19VSS_20VSS_21VSS_22VSS_23VSS_24VSS_25VSS_26VSS_27VSS_28VSS_29VSS_30VSS_31VSS_32VSS_33VSS_34VSS_35VSS_36VSS_37VSS_38VSS_39VSS_40VSS_41VSS_42VSS_43VSS_44VSS_45VSS_46VSS_47VSS_48VSS_49VSS_50VSS_51VSS_52VSS_53VSS_54VSS_55VSS_56VSS_57VSS_58VSS_59VSS_60VSS_61VSS_62VSS_63VSS_64VSS_65VSS_66VSS_67VSS_68VSS_69VSS_70VSS_71VSS_72VSS_73VSS_74VSS_75VSS_76VSS_77VSS_78VSS_79VSS_80VSS_81VSS_82VSS_83VSS_84VSS_85VSS_86VSS_87VSS_88VSS_89VSS_90VSS_91VSS_92VSS_93VSS_94VSS_95VSS_96VSS_97VSS_98VSS_99VSS_100VSS_101VSS_102VSS_103VSS_104VSS_105VSS_106VSS_107VSS_108VSS_109VSS_110VSS_111VSS_112VSS_113VSS_114VSS_115
VSS_118VSS_119VSS_120VSS_121VSS_122VSS_123VSS_124VSS_125VSS_126VSS_127VSS_128VSS_129VSS_130VSS_131VSS_132VSS_133VSS_134VSS_135VSS_136VSS_137VSS_138VSS_139VSS_140VSS_141VSS_142VSS_143VSS_144VSS_145VSS_146VSS_147VSS_148VSS_149VSS_150VSS_151VSS_152VSS_153VSS_154VSS_155VSS_156VSS_157VSS_158VSS_159VSS_160VSS_161VSS_162VSS_163VSS_164VSS_165VSS_166VSS_167VSS_168VSS_169VSS_170VSS_171VSS_172VSS_173VSS_174VSS_175VSS_176VSS_177VSS_178VSS_179VSS_180VSS_181VSS_182VSS_183VSS_184VSS_185VSS_186VSS_187VSS_188VSS_189VSS_190VSS_191VSS_192VSS_193VSS_194VSS_195VSS_196VSS_197VSS_198VSS_199VSS_200VSS_201VSS_202VSS_203VSS_204VSS_205VSS_206VSS_207VSS_208VSS_209VSS_210VSS_211VSS_212VSS_213VSS_214VSS_215VSS_216VSS_217VSS_218
VTT_A0VTT_A1VTT_A2VTT_A3VTT_A4VTT_B0VTT_B1VTT_B2VTT_B3VTT_B4
VTT_SENSE
VSS_116VSS_117
C1600.1U/NA0402
50V+80-20%
12
C803300P0402
50V10%
12
R41210K04025%
12
+2.5VDDA_PG20
VID025VID125VID225VID325VID425
ALL_PWROK_2.5V7,9,20
CPU_RESET# 2
NB_LDTRST#6
CPU_PCIRST#8
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MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place between the processor andnearest SO-DIMM, and Net lengthto the processor should be500-1000mil
Locate close to CPU socket
DIMM-SLOT & Termination
Place on 10uF capacitor oneach end of the VTT island
Place a cap every 1inch on VTT tracebetween Clawhammer andDDR
Locae close to DIMMs
Bypass capacitor
BOT
X7R
X7R
OS-CON OR X7R
bulk-capacitors
Place alternating caps to GND and +2.5VDIMM in asingle line along VTT island.
X7R
DIMM1DIMM0
Net lengths tothe SO-DIMM shouldbe 200-500mils
Sec soure 331660020005 Sec soure 291000622007
<Doc> R00
<Title>
C
4 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
DDR_CKEA
DDR_CS1#
DDR_CS0#
DDR_CS2#
DDR_CS3#
DDR_CKEB
MD36
DDR_CLK5
DQS0
MEMADD_A2
MD37
MD52
DDR_CLK0#
MD42
MEMADD_A10
MD28
MD20
DQM5
DDR_CLK7#
MD10
MD48
DQM3
MEMADD_A1
DDR_CLK5#
MD3
MD6
MD63
DQM0
SMBDATA_DDR
MD49
MD8
DQS4
MD53
MD58
DDR_CS0#
DQS5
MD2
MD5MD4
MD51
MD18
MD16
MD57
DQM6
DDR_RASA#
MD39
MD21
MD12
DQS1
MD25
MD50
MD32
MD41
MD9
MD61
DDR_CASA#
MD14
DQM2
MD0
MD11
DDR_CLK7
DDR_BAA1
MD30
MD40
MD23
MD43
DQS2
MD26
MD60
DQS7
MD62
DQM1
MEMADD_A9
MD54
MEMADD_A7
MEMADD_A13
MD19
MEMADD_A6
MD1
DQS3
MD44
MD7
MEMADD_A8
MEMADD_A0
DDR_CKEA
MD22
MD27
DQS6
MD34
MD33
DDR_BAA0
MD47
MD56
MEMADD_A4
DDR_CLK0
SMBCLK_DDR
DDR_CS1#
MD15
MD17
MD24
MD29
MEMADD_A5
DDR_CKEA
MD45
MD38
MD31
MEMADD_A11
MD59
MD35
MD46
DDR_WEA#
MEMADD_A3
MD13
MEMADD_A12
DQM7
DQM4
MD55
DDR_CLK5
DDR_CLK6
SMBDATA_DDR
DDR_CLK4
SMBCLK_DDR
DDR_CLK7#
DDR_CLK0#
DDR_CLK4#
DDR_CLK0
DDR_CLK1
DDR_CLK7
DDR_CLK6#
DDR_CLK1#
DDR_CLK5#
MEMADD_A3
DDR_CS0#
MEMADD_A5
MEMADD_A0
MEMADD_A10
DDR_CASA#
MEMADD_A12
DDR_WEA#
DDR_BAA1
MEMADD_A2
DDR_CS3#
MEMADD_A6
DDR_BAA0
MEMADD_A13
DDR_CS1#
MEMADD_A7
DDR_WEB#
MEMADD_A8
MEMADD_A9
DDR_CS2#
MEMADD_A4
MEMADD_A1
MEMADD_A11
MD5
MD41
MD24
DQS6
MD33
DQM5
MD52
MD58MD58
MD21
DQM0
CPU_DQM2
MD55
MD44
MD50
MD42
MD61
MD22
MD9 MD9
MD5
MD6
MD40
DQM6MD53
CPU_DQM6
DQM3
CPU_DQS4
MD51
MD52
DQM6
MD21
MD49
MD26
MD34
CPU_DQS0
MD8
MD15
MD20
MD14
DQS4
MD57
MD24
MD31
CPU_MD[0..63]
DQM5
MD16MD17
MD10
MD59
MD7
MD46
DQS1
MD47
MD59
MD2
MD30
DQS3
MD14
CPU_DQM7
CPU_DQM3
MD0
DQM7
MD56
MD16
MD51
CPU_DQS5
MD23
CPU_DQM5
MD41
MD37
MD12
MD44
MD53
DQS2
MD11
DQS6
MD20
CPU_DQM0
DQS5
DQS2
DQM1
DQM2
MD63
MD54
MD42
MD38
CPU_DQS2
MD33
MD49
MD1
MD61
MD47
MD8
MD36
MD35
MD56
DQM7
MD18
MD63
MD27
MD29
MD15
MD22
MD7
MD25
MD19
DQM1
MD0
MD57
MD1
MD4
CPU_DQM1
MD10
DQS4
MD12
MD19
DQS7
MD25
MD26
MD60
DQM4
DQS5
MD60
MD4
DQS1
MD2
CPU_DQS3
MD27
MD32
MD3
MD11
DQM2
MD55
MD62
MD48
MD35
MD39
MD17
CPU_DQS1
MD54
MD38
MD36
DQS7
MD45
DQM0
MD39
MD6
MD28
MD13
MD3
DQS0
MD34
DQS3
MD23
MD62
MD29
MD13
MD43
MD31
MD43
MD28
MD18
DQM3
MD37
CPU_DQS7
DQM4
MD40
MD32
DQS0
MD48
MD30
MD46
MD45
MD50
CPU_DQS6
MD16 MD20
MEMADD_B10
MD44
DQM0
MD1
MEMADD_B12
MEMADD_B2
MD41
DDR_WEB#
MEMADD_B4
DDR_CLK4
DDR_CS2#
DDR_BAB0
MEMADD_B7
DDR_CLK1
DDR_CLK6DDR_CLK6#
DDR_CKEB
MD31
MD6
MD59
MD57
MEMADD_B13
MD27
MD25
MD19
MD52
MD45
MD37
DQM1
MD8
MD35
MEMADD_B3
DQS3
MD54
MD21
MD48
MD42
MEMADD_B8
MD28
DQM2
MD14MD11MD10
MD3
MD0
MD49
MD40
MEMADD_B10
MD29
MD15
MEMADD_B5
MEMADD_B11
MD43
DQS4
MD18
MEMADD_B6
MD23
MD5
MEMADD_B8
MEMADD_B9
MD34
MD62
DQM7
MD60
DQM4
MD36
DDR_CASB#DDR_RASB#
MD13DQS1
SMBDATA_DDR
DDR_CKEB
MD63
DQM6
DQS5
MD46
MD58
MD55
DQM5
MD12MD7
DDR_CLK4#
MD9
MD50DQS6
MEMADD_B5
MD38
MD2
MD24
MD17
MD53
MEMADD_B2
MD30
MD22
MEMADD_B1
MEMADD_B6
MEMADD_B7
MD33
MEMADD_B1
DQS2
MD47
DDR_CS3#
DQM3
MD4
DQS0
MEMADD_B0
SMBCLK_DDR
MD56MD51
MD32
MEMADD_B9
DDR_CLK1#
MD61
DDR_BAB1
MEMADD_B3MEMADD_B4
DQS7
MEMADD_B12
MD26
MD39
MEMADD_B0
MEMADD_B11
CPU_DQM4
CPU_MD60
CPU_MD25
CPU_MD52
CPU_MD36
CPU_MD1
CPU_MD55CPU_MD51
CPU_MD24
CPU_MD18
CPU_MD43
CPU_MD12
CPU_MD40
CPU_MD22
CPU_MD42
CPU_MD11
CPU_MD53
CPU_MD37
CPU_MD14
CPU_MD54
CPU_MD13
CPU_MD9
CPU_MD30
CPU_MD3
CPU_MD0
CPU_MD39
CPU_MD7
CPU_MD33
CPU_MD21
CPU_MD20
CPU_MD17
CPU_MD19
CPU_MD2
CPU_MD62
CPU_MD15
CPU_MD4
CPU_MD29
CPU_MD31
CPU_MD5
CPU_MD49
CPU_MD61
CPU_MD44CPU_MD41
CPU_MD32
CPU_MD63
CPU_MD6
CPU_MD47
CPU_MD38
CPU_MD34
CPU_MD46
CPU_MD26
CPU_MD45
CPU_MD59
CPU_MD56
CPU_MD27
CPU_MD16
CPU_MD10
CPU_MD8
CPU_MD50
CPU_MD28
CPU_MD23
CPU_MD57
CPU_MD48
CPU_MD58
CPU_MD35
MEMADD_A9
MEMADD_A1MEMADD_A0
MEMADD_A6
MEMADD_A10
MEMADD_A4MEMADD_A5
MEMADD_A8
MEMADD_A11
MEMADD_A3
MEMADD_A7
MEMADD_A12
MEMADD_A2
MEMADD_A13
MEMADD_B13
DDR_CASB#
DDR_RASB#
DDR_RASA#DDR_BAB0
DDR_BAB1MEMADD_B0
MEMADD_B8
MEMADD_B1
MEMADD_B3
MEMADD_B5
MEMADD_B10
MEMADD_B2
MEMADD_B6MEMADD_B7
MEMADD_B4
MEMADD_B12MEMADD_B13
MEMADD_B11
MEMADD_B9
DDR_CKEBDDR_CKEA
GND
+2.5VS_DDR
+2.5VS_DDR
GND
+1.25VTT
+2.5VS_DDR
+1.25VTT
+1.25VTT
GND
GND
GND
+1.25VTT+1.25VTT
GND
GND
+2.5VS_DDR
+1.25VTT
+2.5VS_DDR
+1.25VSREF_MEM
+1.25VTT
GND
+1.25VSREF_MEM
GND
+2.5VS_DDR+1.25VSREF_MEM
+2.5VS_DDR
+2.5VS_DDR
+1.25VTT
+1.25VTT
C295 0.1U0402 10%
1 2
RP3568*41206
1234
8765
C296 0.1U0402 10%
1 2
C129 100P0402 +/-10%
1 2
C292 0.1U0402 10%
1 2
R259 47 04021 2
C128 10U6.3V 0805
1 2
C1560.22U 16V 0603
X7R1 2
C221 0.1U0402 10%
1 2
C166 0.1U0402 10%
1 2
C195 0.1U0402 10%
1 2
C149 0.1U0402 10%
1 2
C274 0.1U0402 10%
1 2
C279 0.1U0402 10%
1 2
RP3368*8RPX8
123456789
10111213141516
C285 0.1U0402 10%
1 2
C218 0.1U0402 10%
1 2
RP4168*41206
1234
8765
RP3968*8RPX8
123456789
10111213141516
C1310.22U 16V 0603
X7R1 2
C197 0.1U0402 10%
1 2
C203 0.1U0402 10%
1 2
C165 0.1U0402 10%
1 2
C215 0.1U0402 10%
1 2
C244 0.1U0402 10%
1 2
R260 47 04021 2
C275 0.1U0402 10%
1 2
RP3468*8RPX8
123456789
10111213141516
C2760.22U 16V 0603
X7R1 2
C2160.22U 16V 0603
X7R1 2
C206 100P0402 +/-10%
1 2
RP1910*8RPX8
12345678 9
10111213141516
RP2010*41206
1234
8765
C293 0.1U0402 10%
1 2
C2090.22U 16V 0603
X7R1 2
C288 0.1U0402 10%
1 2
C225 0.22U0402 16V
1 2
RP2110*8RPX8
123456789
10111213141516
RP1547*8RPX8
12345678 9
10111213141516
C299 0.1U0402 10%
1 2
RP4068*8RPX8
123456789
10111213141516
RP1647*8RPX8
12345678 9
10111213141516
C196 0.1U0402 10%
1 2
RP1747*8RPX8
12345678 9
10111213141516
C124 0.1U0402 10%
1 2
C261 100P0402 +/-10%
1 2
C286 0.1U0402 10%
1 2
C1360.22U 16V 0603
X7R1 2
RP3768*8RPX8
123456789
10111213141516
RP3668*8RPX8
123456789
10111213141516
RP2510*8RPX8
123456789
10111213141516
C122 4.7U0805
1 2
RP3168*8RPX8
123456789
10111213141516
RP4347*40804
1234
5678
C253 0.1U0402 10%
1 2
RP2710*8RPX8
123456789
10111213141516
RP2610*41206
1234
8765
C268 0.1U0402 10%
1 2
RP3010*8RPX8
123456789
10111213141516
C132 10U6.3V 0805
1 2
RP2810*8RPX8
123456789
10111213141516
RP1447*8RPX8
12345678 9
10111213141516
RP2910*41206
1234
8765
C290 0.1U0402 10%
1 2
RP4268*8RPX8
123456789
10111213141516
RP3868*41206
1234
8765
C2390.22U 16V 0603
X7R1 2
C278 0.22U0402 16V
1 2
C289 0.1U0402 10%
1 2
C330 0.1U0402 10%
1 2
C168 0.1U0402 10%
1 2
R2568.2K0603
12
C205 0.1U0402 10%
1 2
C305 0.1U0402 10%
1 2
C243 4.7U0805
1 2
C217 0.1U0402 10%
1 2
RP1847*8RPX8
12345678 9
10111213141516
C260 4.7U0805
1 2
C2260.22U 16V 0603
X7R1 2
C294 0.1U0402 10%
1 2
C280 0.1U0402 10%
1 2
C220 0.1U0402 10%
1 2
C202 4.7U0805
1 2
C291 0.1U0402 10%
1 2
C123 1000P0402 +/-20%
1 2
C277 4.7U0805
1 2
C2560.22U 16V 0603
X7R1 2
C204 4.7U0805
1 2
C222 0.1U0402 10%
1 2
C198 0.1U0402 10%
1 2
C264 0.22U0402 16V
1 2
C287 0.1U0402 10%
1 2
C238 0.1U0402 10%
1 2
C298 0.1U0402 10%
1 2
C2480.22U 16V 0603
X7R1 2
C297 0.1U0402 10%
1 2
RP3268*41206
1234
8765
RP2210*8RPX8
123456789
10111213141516
C247 0.22U0603D
1 2
RP2310*41206
1234
8765
RP2410*8RPX8
123456789
10111213141516
C272 4.7U0805
1 2
C284 0.1U0402 10%
1 2
C273 0.1U0402 10%
1 2
J17
0.6MM/200P/H9.2TYCO 1-1470800-2
13579
111315171921232527293133353739
246810121416182022242628303234363840
4244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144146148150152154156158160162164166168170172174176178180182184186188190192194196198200
414345474951535557596163656769717375777981838587899193959799
101103105107109111113115117119121123125127129131133135137139141143145147149151153155157159161163165167169171173175177179181183185187189191193195197199
C194 0.1U0402 10%
1 2
J16
0.6MM/200P/H5.2TYCO1470431-1
13579
111315171921232527293133353739
246810121416182022242628303234363840
4244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144146148150152154156158160162164166168170172174176178180182184186188190192194196198200
414345474951535557596163656769717375777981838587899193959799
101103105107109111113115117119121123125127129131133135137139141143145147149151153155157159161163165167169171173175177179181183185187189191193195197199
C263 0.1U0402 10%
1 2
C300 0.1U0402 10%
1 2
C219 0.1U0402 10%
1 2
CPU_CKEA2
CPU_CKEB2
CPU_CS0#2
CPU_CS1#2
CPU_CS2#2
CPU_CS3#2
DDR_CLK42
DDR_CLK02DDR_CLK0#2
DDR_CLK5#2DDR_CLK52
DDR_CLK72DDR_CLK7#2
DDR_CLK12DDR_CLK1#2
DDR_CLK4#2
DDR_CLK62DDR_CLK6#2
SMB_CLK05,9SMB_DATA05,9
DDR_BAB12
DDR_CASA#2
DDR_RASA#2
DDR_WEA#2DDR_WEB#2
DDR_BAA12
DDR_BAA02
CPU_DQM32
CPU_DQM62
CPU_DQS22
CPU_DQM12
CPU_DQS62
CPU_DQM22
CPU_DQM52
CPU_DQS42
CPU_DQS02
CPU_DQS72
CPU_DQM02
CPU_DQM72
CPU_DQS32
CPU_DQS52
CPU_DQS12
CPU_MD[0..63] 2
CPU_DQM42
MEMADD_A[0..13]2
DDR_CASB#2
DDR_RASB#2
DDR_BAB02
MEMADD_B[0..13]2
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
須用 1%
CHANGE VALUE
CHANGE VALUE
HTT
MODE B
66MHZ
270.00
0
1
1
01
33.480
66MHZ
233.33
1
0
00
DEFAULT33.34
75.00
1
Pin6
33MHZ
CPU
240.00
MODE C
1
1
0
1
33.38
33.00
1
Pin7
66MHZ
67.27
0
1
0 0
66.6733.33
0
Pin8
210.00
1
1
33.00
Pin23
Mhz
60.00
01
66.67
0
166.70
0
66MHZ
1
1
Pin24
166.75
1
0 33.40
Pin11
202.00
1
180.00
66MHZ
1
1
33.40
33.75
033.67
0
168.00
MODE A
300.00
33MHZ
100.90
0
1
0
33.60
Mhz0
133.50
266.67
33MHZ
0
PCICLK6
1
0
1
10 60.00
FS0
200.40150.00
33MHZ
INPUT
1
PCI_STOP#
1
1
00
Mhz
67.50
0
67.33
33MHZ
ONLY
MODE FUNCTIONALITY TABLES
1
0
0
1
66.80
66.95
33MHZONLY
100.20
1
01
1
37.50
1
67.68
FS1
67.20
33MHZINPUT
133.90
30.000
1
1
0
60.00
FS2
0
66.80
33MHZ
MODE A
0
35.00
0
10
033.63
PCI
MODE A
66MHZ
FS3
1 33.33
0
70.00
4~15
2. Series resistors less than 1
3. PCI_SB_CLK is 3 more than thelongest PCI clock2. Series resistors less than 1
5~12
1~12
5~12
AGP Clock Signal
CHANGE VALUEAGP Clock Signal
3. GCLK_NB & SB_VCLK is 4 longerthan 66M_AGP
CHANGE VALUE
1~8
1. 6 : 24
1~12
1. 6 : 24
CLOCK GENERATOR(ICS950405)
PN:284500781001
ON:for ISC950403 OFF:for RTM360803
R810
R811ON:for RTM360803 OFF:for ISC950403
R809ON:for ISC950403 OFF:for RTM360803
R415ON:for RTM360803 OFF:for ISC950403
<Doc> R00
<Title>
C
5 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
FS3
FS1
FS2
FS0
CLK_LPC33
PCI_SB_CLK
PCI_CARD_CLKMINI_PCI_CLK
SB_VCLK
66M_AGP
GUICLK
SB_VCLK
CLK_LPC33
PCI_CARD_CLK
PCI_SB_CLK
MINI_PCI_CLK
LPC_48M
GCLK_NB
66M_AGP
FS1
GCLK_NB
ICS_PD#
RTL_PD#
ICS_PD#
RTL_PD#
ICS_PD#
FS2
FS0
LPC_48MFS3
GUICLK
+3V
GND
GND
GND
GND
GND GNDGND
GND
GND
GND
GND
+3V
GND
+3V
+3V
+3V
+3V+3V
GND
C26710U
6.3V0805
12
R240 22 04021 2
C283 5P0402 +/-10%
1 2
R231 10K/NA 04021 2
R241 330402/NA1 2
U5
G781SO8
1234 5
678VDD
D+D-T_CRIT_A GND
ALERTSMBDATA
SMBCLK
C249 22P0402 +/-10%
1 2
C24627P04025%
12
C2650.1U0402+80-20%
12
R236 10K 04021 2
R238 22 04021 2
L59 120Z/100M 16081 2
R254 0 04021 2
C24127P04025%
12
C2400.1U0402+80-20%
12
R262 22 04021 2D11RLS4148
A K
R250 0/NA 08051 2
R230 22 04021 2
C259 22P0402 +/-10%
1 2
R237 10K/NA 04021 2
C2710.1U0402+80-20%
12
R246270603 1 2R248270603 1 2
R264 22 04021 2
R242 0/NA 04021 2
R233 10K/NA 04021 2
C281 22P0402 +/-10%
1 2
C1090.1U0402
50V+80-20%
12
C257 22P0402 +/-10%
1 2
R252 10K/NA 04021 2
R24927/NA0603 1 2
R253 22 04021 2
C255 22P0402 +/-10%
1 2
R257 10K 04021 2
C2450.1U0402+80-20%
12
X3
14.318MHZ274011431414
1 2
R239 10K/NA 04021 2
C270 22P0402 +/-10%
1 2
C99
2200P040250V+/-20%
12
R232 22/NA 04021 2
R247150603 1 2
R243 22 04021 2
R265 3304021 2
R245150603 1 2
C242 22P0402 +/-10%
1 2
R25110K0402
12
U14
ICS950405SSOP48
1
3
4
67
81112
131417182122
23
24
2
91619
29
32
3538
43
46
2526
28
31
44
4548
510152027303334394247
3637
4041
*FS0/REF0
X1
X2
*MODEA/HTTCLK0~*MODEB/PCICLK7/HTTCLK1
~PCICLK8/HTTCLK2~PCICLK9/HTTCLK3
PCICLK10
PCICLK0PCICLK1
~PCICLK2~PCICLK3
PCICLK4PCICLK5
~*PCICLK_F
~PCICLK6
VDDREF_0
VDDPCI_0VDDPCI_1VDDPCI_2
AVDD48
PD#*
VDDCPU_0VDDCPU_1
VDDA
VDDREF_1
SCLKSDATA
24_48MHZ/SEL24_48#*~
48MHZ/FS3**
RESET#
REF2/FS2*REF1/FS1*
GND0GND1GND2GND3GND4GND5GND6GND7GND8GND9GND10
CPUCLK8C1CPUCLK8T1
CPUCLK8C0CPUCLK8T0
R14610K04025%
12
R244 3304021 2
C252 22P0402 +/-10%
1 2R14510K04025%
12
C26210U
6.3V0805
12
R234 22 04021 2
R258 22 04021 2
L58
120Z/100M2012
1 2
CPUCLK- 2
PCI_CARD_CLK 14
CPUCLK+ 2
MINI_PCI_CLK 15
CLK_KBC 19
SB_VCLK 10
PCI_SB_CLK 8
66M_AGP 7
SMB_DATA0 4,9SMB_CLK0 4,9
THRM_DATA 19
SUSA# 9
THERN_ALERM#20
THRM_CLK 19
CPU_THERMDC2
CPU_THERMDA2
14M_SB_APICCLK10AUDIO_14M18
USB_CLK8LPC_48M15
GUICLK7
14M_SB_IOSC10
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NB VIA_K8N800 (1/2)
是否能改為+2.5VS_DDR
<Doc> R00
<Title>
C
6 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
L0_CADOUT_H14
L0_CADOUT_H9
L0_CADOUT_H0
L0_CADOUT_H3
L0_CADOUT_H10
L0_CADOUT_H[0..15]
L0_CADOUT_H13
L0_CADOUT_H11
L0_CADOUT_H2
L0_CADOUT_H12
L0_CADOUT_H4L0_CADOUT_H5
L0_CADOUT_H15
L0_CADOUT_H1
L0_CADOUT_H8
L0_CADOUT_H6L0_CADOUT_H7
L0_CADOUT_L10
L0_CADOUT_L7
L0_CADOUT_L12L0_CADOUT_L13
L0_CADOUT_L15
L0_CADOUT_L6
L0_CADOUT_L8
L0_CADOUT_L3L0_CADOUT_L2
L0_CADOUT_L9
L0_CADOUT_L4
L0_CADOUT_L1
L0_CADOUT_L14
L0_CADOUT_L5
L0_CADOUT_L11
L0_CADOUT_L0L0_CADOUT_L[0..15]
L0_CADIN_H10
L0_CADIN_H4L0_CADIN_H5
L0_CADIN_H3
L0_CADIN_H9
L0_CADIN_H2
L0_CADIN_H6
L0_CADIN_H1
L0_CADIN_H7
L0_CADIN_H13L0_CADIN_H12
L0_CADIN_H14
L0_CADIN_H8
L0_CADIN_H0
L0_CADIN_H15
L0_CADIN_H11
L0_CADIN_H[0..15]
L0_CADIN_L7
L0_CADIN_L10
L0_CADIN_L5L0_CADIN_L4
L0_CADIN_L1
L0_CADIN_L3
L0_CADIN_L12
L0_CADIN_L9L0_CADIN_L8
L0_CADIN_L15
L0_CADIN_L2
L0_CADIN_L14
L0_CADIN_L6
L0_CADIN_L13
L0_CADIN_L11
L0_CADIN_L0L0_CADIN_L[0..15]
RPCOMPRNCOMPRTCOMP
RTCOMP
RPCOMP
RNCOMP
+1.2VLDTA
GND
+1.2VLDTA
+1.2VLDTA+NB_AVDD2
+NB_AVDD2
GNDGND
GND
GND
GND
+NB_VCCSUS +1.5V_VCCAGP
+NB_AVDD1
GND
+1.5VPLL1
+1.5VPLL2
+3.3VDACVDD
+1.5V_VCCVL
+1.5V_NB
+3V
+1.5V
+3V
+1.2VLDTA
+NB_AVDD1 +1.5V +1.5VPLL2
+1.5VPLL1+1.5V
+3V +3.3VDACVDD
+3V +3.3VDACVDD+3V
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
+1.2VLDTA
+NB_VCCSUS
GNDGND
+2.5VS
+1.5V
GND
+1.5V_NB +1.5V_VCCVL+1.5V
GND
+1.5V_VCCAGP+1.5V
GND
GND
+1.5V_NB
GND
+1.5V_VCCVL
GND
+1.5V_VCCAGP
GND
GND
C104 0.1U0402 10%
1 2
C6600.01U0402
50V+80-20%
12
C72 0.1U0402 10%
1 2
C651 0.1U0402 10%
1 2
U12C
K8N800BGA451_110_26
AB12
T2T3T4T5T8T9U2U3U4U5U8U9
AC25
B7C7
D5A5C5B5
A6B6
B2
C3
A4
B4
AB11
AB7
V10V11V12V13V2V3V4V8
W2W3W4W9
AA21AA22AA23AA24AA25AA26
AB22AB23AB24AB25AB26
H11H12H15H16
K19L19M19P8R19R8T19
V18V19W10W11
Y21Y22Y23Y24Y25Y26
AB19AB20AC18AC19AC20AC21
V14V15V16V17
W15W16W17W18
AE17AE20AE22AE25
AA4AA5
AB8
AB21
AB13AB14
V9
AE8AE11AE14
U19
D4
E26E25
R16
R21R25T10T11T12T13
T15T16T17
U11
R17
T14
U10
AB16
AC24AE2AE5
U12U13U14U15U16U17
V5W5
W21
W19Y20
W22W23W24W25W26AB2
F9H10
H9
Y4Y3
Y5
H8
J8
W12W13W14
AB17AB18
AB3AB4
M8N8
AB5AB6AB9
AB10AB15
AC8AC22AC23
VCCAGP
VCCAGPVCCAGPVCCAGPVCCAGPVCCAGPVCCAGPVCCAGPVCCAGPVCCAGPVCCAGPVCCAGPVCCAGP
VCCSUS
GNDGND
VCCPLL1VCCPLL2GNDPLL1GNDPLL2
VCCPLL3GNDPLL3
VCCDAC
GNDDAC
VCCRGB
GNDRGB
VCCAGP
VCCAGP
VCCAGPVCCAGPVCCAGPVCCAGPVCCAGPVCCAGPVCCAGPVCCAGP
VCCAGPVCCAGPVCCAGPVCCAGP
VCCVCCVCCVCCVCCVCC
VCCVCCVCCVCCVCC
VCCVCCVCCVCC
VCCVCCVCCVCCVCCVCCVCC
VCCVCCVCCVCC
VCCVCCVCCVCCVCCVCC
VCCVLVCCVLVCCVLVCCVLVCCVLVCCVLVCCVLVCCVLVCCVLVCCVLVCCVLVCCVLVCCVLVCCVL
GNDGNDGNDGND
VCCAGPVCCAGP
VCCAGP
VCC
VCCAGPVCCAGP
VCCAGP
GNDGNDGND
VCC
GNDDAC
GNDARXVCCARX
GND
GNDGNDGNDGNDGNDGND
GNDGNDGND
GND
GND
GND
GND
GND
GNDGNDGND
GNDGNDGNDGNDGNDGNDGNDGNDGND
VCCVCC
GNDGNDGNDGNDGNDGND
VCCVCC
VCC
VCCAGPVCCAGP
VCCAGP
VCC
VCC
VCCVCCVCC
VCCVLVCCVL
GNDGND
VCCAGPVCCAGP
GNDGNDGNDGNDGND
GNDGNDGND
C380.01U0402
50V+80-20%
12
C250.01U0402
50V+80-20%
12
C77 0.1U0402 10%
1 2
C1210U080510V+80-20%
12
C24 0.1U0402 10%
1 2
C654 0.1U0402 10%
1 2
R168 22 06031 2
C81 0.1U0402 10%
1 2
C657 0.1U0402 10%
1 2
L3120Z/100M
20121 2
L7120Z/100M
20121 2
C1190.01U0402
50V+80-20%
12
R25 49.9 06031%1 2
C6630.01U0402
50V+80-20%
12
C3510U080510V+80-20%
12
C655 0.1U0402 10%
1 2
L502120Z/100M
20121 2
C58 0.1U0402 10%
1 2
C418
0.1U040210%
12
C66410U080510V+80-20%
12
C78 0.1U0402 10%
1 2
C13 0.1U0402 10%
1 2
C130 0.1U0402 10%
1 2
C102 0.1U0402 10%
1 2
C658 0.1U0402 10%
1 2
C652 0.1U0402 10%
1 2
C649 0.1U0402 10%
1 2
C910U080510V+80-20%
12
C417
0.1U040210%
12
L24120Z/100M
20121 2
C1110U/NA080510V+80-20%
12
C656 0.1U0402 10%
1 2
R418 0 04021 2
C14 0.1U0402 10%
1 2
C300.01U0402
50V+80-20%
12
C45 0.1U0402 10%
1 2
C23 0.1U0402 10%
1 2
C49 0.1U0402 10%
1 2
R169330603
12
C106 0.1U0402 10%
1 2
C76 0.1U0402 10%
1 2
L4120Z/100M
20121 2
C65910U080510V+80-20%
12
L503120Z/100M
20121 2
R24 100 04021%1 2
C6650.01U0402
50V+80-20%
12
C270.01U/NA0402
50V+80-20%
12
C653 0.1U0402 10%
1 2
C280.01U0402
50V+80-20%
12
C60 0.1U0402 10%
1 2
C17 0.1U0402 10%
1 2
C290.01U0402
50V+80-20%
12
C16410U080510V+80-20%
12
C98 0.1U0402 10%
1 2
L2120Z/100M
20121 2
C650 0.1U0402 10%
1 2
U12A
K8N800BGA451_110_26
A10
A24
A25
A26
A9
B10
C22
B11
T26P24P26M24K24K26H24H26R24R22N24N22L22J24J22
G24
M26L24
F24
R26P25N26M25K25J26H25G26R23P22N23M22K22J23H22G23
L26L23
F25
A12
D25D26C26
K12
A8
B15
B21
D6
D18
D20
F13
F14
F17
F18
F26
G25
H1
H23
J2C21
J21
J25
K4
G1
K10
B12A13B14A15A17B18A19B20E12D13E14D15D17E18D19E20
B16E16
A21
C12A14C14A16A18C18A20C20E13C13E15C15C17E19C19D21
C16E17
A22
K16
K17
K23
H2
L10
L11
L13
E5
E6
E8
F7 F8 F12
K15
K13
K14
L12
U24U25U26
D12
K11
V21V22V23V24V25V26
A23
J3B22
C8
D8
B8
B13
B17
B19
D14
D16
L14
L15
B23
B24
B25
B26
B9
C10
C11
C23
C24
C25
C9
D10
D11
D22
D23
D24
D9
E10
E11
E21
E22
E23
E24
E9
F10
F11
F15
F16
F19
F20
F21
F22
F23
G21
G22
H21
J11
J12
J13
J14
J15
J16
J17
K18
K21
L18
L21M18N18N21P18P21R18T18T21T22T23T24T25U18U21U22U23
J10
J18
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CA
TX
HTRST#
RCAD0RCAD1RCAD2RCAD3RCAD4RCAD5RCAD6RCAD7RCAD8RCAD9RCAD10RCAD11RCAD12RCAD13RCAD14RCAD15
RCLK0RCLK1
RCTL
RCAD0#RCAD1#RCAD2#RCAD3#RCAD4#RCAD5#RCAD6#RCAD7#RCAD8#RCAD9#RCAD10#RCAD11#RCAD12#RCAD13#RCAD14#RCAD15#
RCLK0#RCLK1#
RCTL#
HTSTP#
RPCOMPRNCOMPRTCOMP
GN
D
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
GN
DG
ND
GN
D
GN
D
GN
DA
TX
GN
DG
ND
GN
D
GN
D
GN
D
TCAD0TCAD1TCAD2TCAD3TCAD4TCAD5TCAD6TCAD7TCAD8TCAD9
TCAD10TCAD11TCAD12TCAD13TCAD14TCAD15
TCLK0TCLK1
TCTL
TCAD0#TCAD1#TCAD2#TCAD3#TCAD4#TCAD5#TCAD6#TCAD7#TCAD8#TCAD9#
TCAD10#TCAD11#TCAD12#TCAD13#TCAD14#TCAD15#
TCLK0#TCLK1#
TCTL#
GN
DG
ND
GN
D
GN
D
GN
DG
ND
GN
D
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
GN
DG
ND
GN
D
VCCHTVCCHTVCCHT
GN
D
GN
D
VCCHTVCCHTVCCHTVCCHTVCCHTVCCHT
GN
D
GN
D
GN
DG
ND
GN
D
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VC
CH
TV
CC
HT
VCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHTVCCHT
VC
CH
T
GN
D
C18 0.1U0402 10%
1 2
C12010U080510V+80-20%
12
L504120Z/100M
20121 2
C66210U080510V+80-20%
12
L5120Z/100M/NA
20121 2
C810U080510V+80-20%
12
R19 49.9 06031%1 2
L0_CADOUT_H[0..15]2
L0_CADOUT_L[0..15]2
L0_CADIN_H[0..15] 2
L0_CADIN_L[0..15] 2
L0_CLKOUT_L12
L0_CLKOUT_H12
L0_CLKOUT_L02
L0_CLKOUT_H02L0_CLKIN_H1 2L0_CLKIN_H0 2
L0_CLKIN_L0 2L0_CLKIN_L1 2
L0_CTLOUT_H02 L0_CTLIN_H0 2
L0_CTLOUT_L02 L0_CTLIN_L0 2
LDTSTOP#2,10NB_LDTRST#3LDTSTOP_NB#2
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
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5
5
4
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3
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2
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D D
C C
B B
A A
NB VIA_K8N800 (2/2)
<Doc> R00
<Title>
C
7 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
NB_FPD10NB_FPD11
NB_FPD09NB_FPD08NB_FPD07NB_FPD06NB_FPD05AGP_AD8
NB_FPD01NB_FPD23NB_FPD00NB_FPD22NB_FPD21NB_FPD20NB_FPD18NB_FPD17NB_FPD16NB_FPDENB_FPD14NB_CLK+NB_FPD13NB_FPD15
NB_FPCLK-
NB_FPHS
NB_FPVS
NB_FPD02
NB_FPD03
NB_FPD04
NB_FPD12
NB_FPD19
FPD0FPD1FPD2
FPD4FPD5FPD6FPD7FPD8
FPD10
PCI_INTA#
VAD7
VAD[0..7]
VAD2VAD3VAD4VAD5
VAD0
VAD6
VAD1
LVREF_NB
LVREF_NB
LCOMPP
RSET
BISTIN
DEBUG
TESTIN
DISPDCLKODISPDCLKI
SP_MRASP_SR1
SP_SSON
SP_SR0
DISPDCLKI
DISPDCLKO
AGP_ADSTBS1
AGPPCOMPAGPNCOMP
AGP_VREF
AGP_VREF
ENAVDDENAVEE
ENPBLT_NB
SUSST1#
AGP_8XDE#FPD6
FPD5
FPD4
FPD7
FPD10
AGP_GD31
RSET
BISTIN
AGP_ADSTBS1
AGP_8XDE#
AGP_AD8
SP_SR1
AGPNCOMP
DEBUG
LCOMPPSP_SSON
AGP_GD31
AGPPCOMP
SP_SR0
I2C_CLK
TESTIN
SP_MRA
I2C_DATA
SUSST1#
FPD8
ENPBLT_NB
+3V +1.5V
GND
GND
+2.5V
GND
+3V
GND
GND
+1.5V
GND
+3V
+1.5V
GND
+2.5V
+3VS
+3V
GND
+1.5V +3V
GND
R414 4.7K 04021 2
R314 10K/NA 04021 2
R39 0 04025%1 2
R158 0 04025%1 2
R3 0NA 04021 2
R1
Q3
DTC114TKA
2
1 3
R40 1K 04021 2
R105 0 04021 2
R1703K04021%
12
R165 360 04021%1 2
R58 0/NA 04021 2
C4260.1U/NA0402
50V+80-20%
12
R2 0 04021 2
R33 0/NA 04021 2
R72 0 04021 2
C1211U0402
10V+80-20%
12
R14 90.9 04021%1 2
R108 4.7K 04021 2
R109 4.7K 04021 2
R137 4.7K 04021 2
R99 10K 04021 2
R43410K04025%
12
R121 0 04025%1 2
R7 22/NA 04021 2
R62204025%
12
R42 0 04025%1 2
C1181U0402
10V+80-20%
12
R157330603
12
R86 4.7K 04021 2
R164 10K 04021 2
R90 60.4 04021%1 2
R130 4.7K 04021 2
R31 4.7K 04021 2
U1
P2040/NASO8
1234 5
678CLKIN
MRASR1VSS SSON
MODOUTSR0VDD
R110 4.7K 04021 2
R162 0 04021 2
R81 60.4 04021%1 2
U12B
K8N800BGA451_110_26
AD20AD21AF24AE24AE19AF20AD24AF25
AE21AF19
AE23AF23
AF22AD22
AF26AD23
AF21
AD19
AE26
AD25
AC26
AD26
B3A3A2
C4
C6
E7D3
P2C2P1C1
N2D2
U1
AF18AD18AE18AF17AD17AD16AE16AF16AF14AD14AD13AE13AF13AD12AF12AE12AD10AE10AF10AD9AF9AF8AE9AD8AF6AD7AE6AD5AF5AF4AE4AD4
AD15AF11AD11AC7
AF15AE15
AF7AE7
AC9AC10AC14AC11AC12AC16AD6AC1Y1AA3AC15
AC2AC3AD1AD2AF2AD3AE3AF3
AE1AF1
AA2AA1AB1
V1W1
AC13AC6
Y2
AC4AC5
T1
M5
K8
M9
L8 N9
P9
R9
AC17F1 K
5
E4
E2
E3
F6F2 F5E1
F4F3 N5
J1K2K3L4K1L2L3
M4L1
M2M3M1
P4N1N4N3
P3
D1
L5K9
L9
M10
L17
L25
M11
A1B1
A11
M12
M13
M14
M15
M16
M17
M21
M23
G2
G3
G4
G5
H3
H4
H5
J4 J5 J9
N10
N11
N12
N13
N14
N15
N16
N17
N25
P5
P10
P11
P12
P13
P14
P15
P16
P17
P23
R1
R2
R3
R4
R5
R10
R11
R12
R13
R14
R15
L16
A7D7
VAD0VAD1VAD2VAD3VAD4VAD5VAD6VAD7
VBE#VPAR
UPSTBUPSTB#
DNSTBDNSTB#
UPCMDDNCMD
VLVREF
VLPCOMP
PWROK
RESET#
TESTIN
SUSST#
ARAGAB
RSET
XIN
INTA#BISTIN
SPCLK1SPCLK2SPDAT1SPDAT2
GPO0GPOUT
VC
CQ
Q
GD0/DP3D10GD1/DP3D11GD2/DP3CLKGD3/DP3D09GD4/DP3D08GD5/DP3D07GD6/DP3D06GD7/DP3D05GD8/DP3DET
GD9/DP3HSGD10/DP3D01GD11/DP2D11GD12DP3D00
GD13/DP2D10GD14/DP2D09GD15/DP2D08GD16/DP2D06GD17/DP2D05GD18/DP2D04GD19/DP2DE
GD20/DP2D02GD21/DP2CLKGD22/DP2D01GD23/DP2D03GD24/DP1D09
GD25GD26/DP1D10
GD27GD28/DP1D07GD29/DP1D06GD30/DP1D08GD31/DP1DET
GBE0/DP3D03GBE1/SBDAT
GBE2/DP2D07GBE3/DP1D11
GDS0S/GDS0#/DP3D02GDS0F/GDS0/DP3D04
GDS1S/GDS1#/DP2DETGDS1F/GDS1/DP2D00
GFRE/DP2HSGIRDY/SBCLK
GTRDYGDSEL/DP2VS
GSTOP/DP3CLK#GPAR/DP3VS
GRBFGWBF/DP2CLK#GREQ/DDCCLKGGNT/DDCDATGSERR/DP3DE
SBA0#/DP1VSSBA1#/DP1DE
SBA2#/DP1D00SBA3#/DP1HS
SBA4#/DP1D05SBA5#/DP1D03SBA6#/DP1CLK
SBA7#/DP1CLK#
SBSS/SBS#/DP1D02SBSF/SBS/DP1D01
ST0ST1/DP1D04
ST2
AGPPCOMPAGPNCOMP
AGPVREF_0AGPVREF_1
AGP8XDT#
GDBILGDBIH/GPIPE#
GN
DQ
Q
VC
CG
FX
VC
CG
FX
VC
CG
FX
VC
CG
FX
VC
CG
FXV
CC
GFX
VC
CG
FX
DEBUGV
CC
GFX
VC
CG
FX
VC
CG
FX
VC
CG
FXV
CC
GFX
VC
CG
FX
VC
CG
FX
VC
CG
FX
VC
CG
FX
VC
CG
FXV
CC
GFX
VC
CG
FXTVD00/DP0D00/STRAPTVD01/DP0D01/STRAPTVD02/DP0D02/STRAPTVD03/DP0D03/STRAPTVD04/DP0D04/STRAPTVD05/DP0D05/STRAPTVD06/DP0D06/STRAPTVD07/DP0D07/STRAPTVD08/DP0D08TVD09/DP0D09TVD10/DP0D10/STRAPTVD11/DP0D11
TVCKI/DP0DETTVDE/DP0DETVHS/DP0HSTVVS/DVP0VS/NC
TVCLK/DP0CLK
VC
CG
FX
VC
CG
FXV
CC
GFX
VC
CG
FX
GN
D
GN
DG
ND
GN
D
HSYNCVSYNC
GCLK
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
VC
CG
FXV
CC
GFX
VC
CG
FXV
CC
GFX
VC
CG
FXV
CC
GFX
VC
CG
FXV
CC
GFX
VC
CG
FXV
CC
GFX
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
DCLKODCLKI
R163 0 04021 2
R8 0 04021 2
R60 0 04021 2
R1661K04021%
12
R15611006031%
12
R1 1K 04021 2
R111 4.7K 04021 2
NB_FPD11 12
NB_FPHS 12
NB_FPD07 12
NB_FPD16 12
NB_FPD22 12
NB_FPD12 12
NB_FPD01 12
NB_FPD18 12
NB_FPD14 12
NB_FPD08 12
NB_FPCLK- 12
NB_FPD04 12
NB_FPD21 12
NB_FPD10 12
NB_FPD00 12
NB_FPD17 12
NB_FPCLK+ 12
NB_FPD06 12
NB_FPD13 12
NB_FPD03 12
NB_FPD23 12
NB_FPD09 12
NB_FPVS 12
NB_FPDE 12
NB_FPD19 12
NB_FPD15 12
NB_FPD05 12
NB_FPD02 12
NB_FPD20 12
TVD1111TVD1011
TVD311
TVD111
TVD411
TVD711TVD811
TVD211
TVD611TVD511
TVD011
TVD911
TVVS11TVHS11
CRT_BLUE11CRT_GREEN11CRT_RED11
CRT_HSYNC11CRT_VSYNC11
PCI_INTA#8
VAD[0..7]10
DNCMD10
DNSTB#10
VPAR10
DNSTB10
UPCMD10
VBE#10
UPSTB#10UPSTB10
NB_PCIRST#8,11,19
GUICLK5
ALL_PWROK_2.5V3,9,20
ENAVDD 12ENAVEE 12
66M_AGP 5
SUSST1#9
TV_DS11
AGP_8X# 10
I2C_CLK11
I2C_DATA11CRT_DDCK11
CRT_DDDA11
I2C_CLK_LVDS 12
I2C_DATA_LVDS 12
TVCLK11
TVCLKI11
ENPBLT 12
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D D
C C
B B
A A
SB VIA_VT8235CD (1/3)
<Doc> R00
<Title>
C
8 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
PCI_FRAME#PCI_DEVSEL#PCI_IRDY#PCI_TRDY#PCI_STOP#PCI_SERR#PCI_PAR#PCI_PERR#
PCI_REQ#0PCI_REQ#1
PCI_GNT#0PCI_GNT#1
PCI_INTA#PCI_INTB#PCI_INTC#
USBP4+USBP4-USBP5+USBP5-
USBP0+USBP0-USBP1+USBP1-USBP2+USBP2-USBP3+USBP3-
USBP0-USBP1+USBP1-
USBP2-
USBP3-USBP3+
USBP5+USBP5-
USBP4+
USBP0+
USBP4-
USBP2+
SB_KA20GSB_KBRCSB_IRQ1SB_IRQ12
KBD_CS0
KBD_CS1SB_GPIO12SPKR_MUTE#MB_ID0MB_ID1
MB_ID0 MB_ID1
PCI_AD[0..31]PCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5PCI_AD6PCI_AD7PCI_AD8PCI_AD9PCI_AD10PCI_AD11PCI_AD12PCI_AD13PCI_AD14PCI_AD15PCI_AD16PCI_AD17PCI_AD18PCI_AD19PCI_AD20PCI_AD21PCI_AD22PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27PCI_AD28PCI_AD29PCI_AD30PCI_AD31
PCI_INTD#
PCI_GNT#2PCI_GNT#3PCI_GNT#4PCI_GNT#5
PCI_REQ#2PCI_REQ#3PCI_REQ#4PCI_REQ#5
PCI_GNT#4PCI_GNT#5
PCI_GNT#3
PCI_GNT#1PCI_GNT#2
PCI_GNT#0
PCI_REQ#5PCI_REQ#4
PCI_REQ#2PCI_REQ#1PCI_REQ#0
PCI_REQ#3
SPKR_MUTE#SB_GPIO12
KBD_CS0KBD_CS1PCI_INTB#
PCI_INTC#
PCI_INTA#
PCI_INTD#
PCI_PERR#
PCI_STOP#
PCI_PAR#PCI_SERR#
PCI_TRDY#PCI_IRDY#
PCI_FRAME#PCI_DEVSEL#
PCI_RST#
PCI_RST#
PCI_RST#
PCI_RST#
SB_KBRC
SB_IRQ12SB_IRQ1
SB_KA20G
+3V +3VS_USB
GND
GND
+2.5V
GND
+3V
GND
+3V
GNDGND
+3V +3V
GND
+3V
+3V
GND
GND
+3V
GND GND
+3VS +3V
GND
+3V
+3VS_USB
+2.5VS
GND
C3270.1U0402+80-20%
12
RP55
2.2K*8 1206
12345 6
78910
C31710U080510V+80-20%
12
R28210K/NA04025%
12
L65120Z/100M
20121 2
U20A
VT8235BGA451_36_1MM
H3J2H2J1
G3H1G2G1G4F2F1E1F3E2E3D2B5A5C6B6K1J3K2K3L2L3
M2M1M3N1N3N2
F4D1A4L1
B4B3C4A3C3C1D3
A21B21E21D21
B1
B2
E9
P1P2P3R1
D6C5D4H4L4
E6D5E4J4
M4
A19B19E19D19A17B17E17D17
E15
E14
A15B15C15
V3V2W2W1
F12
F13
F16
F17
L5 M5
P5
P21
R5
R21
W5
Y5
E5
F5 F7 F8 Y21
AA
21A
B6
R22
G5
E16
E23
C2
N4
P4
R2
D8D7C7A6A7B8C8B7
H23
H25
AB
7A
B10
AB
11A
B14
AB
15A
B20
AB
21A
C18
AC
19
D24
A24
A25
A26
B24
B25
B26
C24
C25
C26
D23
C23
E25
A1
A2
A16
A18
A20
A22
B16
B18
B20
B22
C16
C17
C18
C19
C20
C21
C22
D16
D18
D20
E18
E20
F18
F19
F21
F20
K4
L11
AC
9A
C8
D14
T4U4
D15
D22A23
B23E22
AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31
CBE0#CBE1#CBE2#CBE3#
FRAME#DEVSEL#IRDY#TRDY#STOP#SERR#PAR
USBP0+USBP0-USBP1+USBP1-
GN
DG
ND
GN
D
INTA#INTB#INTC#INTD#
REQ0#REQ1#REQ2#REQ3#REQ4#
GNT0#GNT1#GNT2#GNT3#GNT4#
USBP2+USBP2-USBP3+USBP3-USBP4+USBP4-USBP5+USBP5-
USBOC3#
USBOC5#
USBOC0#USBOC1#USBOC2#
KBCK/KA20GKBDT/KBRCMSCK/IRQ1
MSDT/IRQ12
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
PCICLK
GN
D
GN
DG
ND
PERR#
REQ5#
GNT5#
PCIRST#
IPBTDFR/GPI14/GPO14IPBRDFR/GPI10/GPO10IPBTDCK/GPI15/GPO15IPBRDCK/GPI11/GPO11IPBOUT0/GPI12/GPO12IPBOUT1/GPI13/GPO13
IPBIN0/GPI8/GPO8IPBIN1/GPI9/GPO9
GN
DG
ND
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
US
BV
DD
US
BV
DD
US
BV
DD
US
BV
DD
US
BV
DD
US
BV
DD
US
BV
DD
US
BV
DD
US
BV
DD
US
BV
DD
USBCLK
USB REXT
GN
D
GN
DG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
US
BG
ND
GN
DG
ND
GN
DG
ND
USBOC4#
VSUS25VSUS25
USBSUS25
PLLVDDAPLLVDDA
PLLGNDAPLLGNDA
C32210U080510V+80-20%
12
RP51
4.7K*8 1206
12345 6
78910
C3480.1U0402+80-20%
12
U8C
74HCT08_VTSSOP14
9
108
147
L63120Z/100M
20121 2
RP50 15K*4 12061234
8765
C30910U080510V+80-20%
12
R27910K04025%
12
L61120Z/100M
20121 2
C3120.1U0402
50V+80-20%
12
RP54
4.7K*8 1206
12345 6
78910
U8A
74HCT08_VTSSOP14
1
23
147
RP46 15K*4 12061234
8765
R27810K/NA04025%
12
C3380.1U0402
50V+80-20%
12
R287 5.6K 0402 1%1 2
C3424.7U0805+80-20%
12
C3250.1U0402+80-20%
12
RP57 10K*4 12061234
8765
RP49 15K*4 12061234
8765
R28110K04025%
12
R297 22 04021 2
U8B
74HCT08_VTSSOP14
4
56
147
L68120Z/100M2012
12
RP48
4.7K*8 1206
12345 6
78910
C3160.1U0402+80-20%
12
C39110U0805+80-20%
12
PCI_C/BE#114,15PCI_C/BE#014,15
PCI_C/BE#214,15PCI_C/BE#314,15
PCI_PERR#14,15
PCI_STOP#14,15
PCI_PAR14,15
PCI_IRDY#14,15
PCI_SERR#14,15
PCI_GNT0#14
PCI_FRAME#14,15
PCI_TRDY#14,15
PCI_DEVSEL#14,15
PCI_REQ0#14
PCI_GNT1#15
PCI_REQ1#15
PCI_INTA#7PCI_INTB#14PCI_INTC#15
PCI_SB_CLK5
USBP4- 17USBP4+ 17
USBP5- 17USBP5+ 17
USBP3- 17USBP3+ 17USBP2- 17USBP2+ 17USBP1- 17USBP1+ 17USBP0- 17USBP0+ 17
USB_OC#0 17
USB_OC#5 17USB_OC#4 17USB_OC#3 17USB_OC#2 17USB_OC#1 17
USB_CLK 5
A20G 19KBRC# 19
CARD_PCIRST# 13,14,15
MINI_PCIRST# 13,14,15
LPC_RST# 7,11,19
NB_PCIRST# 7,11,19
TV_PCIRST# 7,11,19
ENBL_SB 12KBD_CS0 19MPCIACT# 15
PCI_AD[0..31]14,15
PCI_INTD#15
IDE_PCIRST# 13,14,15
LCD_ID2 12
CPU_PCIRST# 3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3V
+3VS
GPIO14
+3V
GPIO30
GPO7
U2
PME#
RESERVE
AB1
SB_GHI#
SEE STRAP TABLE
+3V
+3V
+3V
GPIO31
GPI16
GPI2
AC7
RESERVE
SEE STRAP TABLE
AC1
+3V+3VS
GPI17
GPI3
GPIO13
SCI#
P4
RESERVE
SEE STRAP TABLE
D8
W4RESERVE
+3V+3VS
+3V
GPI18
GPI4
GPIO15
AF11
RESERVE
SB_SLP#
R24
AD3RESERVE
+3V
+3V
VCC_RTC
GPI19
GPI5
GPIO21
AE11
AE3
MB_ID0
P26
Y1LCD_ID0
+3V
+3V
GPI6
GPIO27
A8
MB_ID1
AE5
RESERVE
LCD_ID1
+3V
+3V
GPI7
+3V
GPIO20
GPO17
N4
KBD_CS0
AD1
AD11
AGP_8X#
RESERVE
+3V
+3VGPO0
+3V
GPIO22
GPO16
Y4
KBD_CS1
AE1
AC11
RESERVE
SUSA#
+3V
+3VSGPO1
+3V
GPIO26
GPO19
AD10
P24
C8
CRT_IN#
SUSB#+3VS
GPIO25
GPO18
AD6
B7
MINIPCI_PD
SB_SUSST#
VCC_RTC+3VS
RESERVE
+3VS
+3V
GPIO24
GPIO8
GPO2
AC6
A6
SPKR_MUTE#
RESERVE
THRM#
AA3
RESERVE
+3VS
+3V
GPIO23
GPIO9
GPO3
P25
D7
PINOUT
RESERVE
EXTSMI#
AA2
ENBL_SB
+3VS
+3V
+3VS
GPIO10
GPO4
A7
AC3VAKE_UP#
AF2
MPCIACT#
+3V
+3VS
GPIO11
GPIO29
GPO5
C7
AA1RESERVE
AE6
Y3
RESERVE
RESERVE
+3V
+3VS
GPIO12
GPI1GPI0
+3V
GPIO28
GPO6
B8
Y2MII_PWRDWN
V1
AF6
RESERVE
SEE STRAP TABLE
00 - 200MHz (Default)11 - 800MHz
SA[17:16]==>LDT Frequency10 - 600MHz01 - 400MHz
SDA0 ==> LDT Trasmit Timing control
1 - Ensable
SDA2 ==> ROMSIP Select0 - Disable (Default)
1 - Exteral EEPROM (On-board)(Default)1 - Ensable LPC (Default)0 - Disable (Default)1 - Ensable
0 - Disable LPC 0 - BIOS Porting - ACRROMCS# ==> LPC Interface Select SDCS1# ==> EEPEOM Select SDCS3# ==> Test Mode Select
SA[19]==>Fast command
1 - Ensable0 - Disable (Default) 0 - 8-Bit (Default)
SA[18]==>LDT Width
1 - 16-Bit0 - Disable (Default)1 - Ensable
SDA1 ==> Extermal loop test mode
SOE# ==> Auto Reboot Mode1 - Dnsable(default)0 - Ensable
SB VIA_VT8235CD (2/3)
<Doc> R00
<Title>
C
9 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
IDE_PDD0IDE_PDD1IDE_PDD2IDE_PDD3IDE_PDD4IDE_PDD5IDE_PDD6IDE_PDD7IDE_PDD8IDE_PDD9IDE_PDD10IDE_PDD11IDE_PDD12IDE_PDD13IDE_PDD14IDE_PDD15
IDE_SDD0IDE_SDD1IDE_SDD2IDE_SDD3IDE_SDD4IDE_SDD5IDE_SDD6IDE_SDD7IDE_SDD8IDE_SDD9IDE_SDD10IDE_SDD11IDE_SDD12IDE_SDD13IDE_SDD14IDE_SDD15
SDCS1#SDCS3#SDA0SDA1SDA2
PCOMPP
SCOMPP
PVREF
SVREF
IDE_PDD[0..15]
IDE_SDD[0..15]
PWROK#
WAKE_UP#EXTSMI#SCI#GPI4PME#SUSST1#SUSCLK
SUSA#SUSB#SUSC#GPI7SMBCLK1SMBDATA1
GPO0
GPI0GPIO24GPIO25GPIO30GPIO31
CLKRUN#GPO5GPO6
ISA_SOE#ISA_ROMCS#
SA17SA16
SDA0
SMBCLK1
SMBDATA1
GPI0
ISA_SOE#
PCOMPP
SCOMPP
SVREFPVREF
SDCS3#ISA_ROMCS# SDCS1#
SDA1 SDA2 SA19 SA18
SA16SA17SA18SA19
ACSDIN2ACSDIN3
ACSDIN2
ACSDIN3
PME#
ISA_SD3
ISA_SD1
ISA_SD6ISA_SD5ISA_SD2ISA_SD4
ISA_SD0
ISA_SD7ISA_SD4ISA_SD5ISA_SD6
GPIO30 GPO6
IOW#
GPIO25 GPO5
GPIO31 IOR#
GPIO24
IOR#IOW#
GPI19
GPI19
PWROK#WAKE_UP#EXTSMI#SCI#
GPI4SUSA#SUSCLKGPO0
GPI1
GPI1
GPI7
ISA_SD7
ISA_SD2ISA_SD3
ISA_SD0ISA_SD1
TESTB
TESTB
GND
+3VS +2.5V
+3V +3V
GND GND
GND
+3V
GND
+3V
GND
+3V
+3V
GND
+3V
+3V
+2.5V
+3V
+VCC_RTC
+3V
GND
+3V+3V
GNDGND
GND
+3V+3V
GNDGND
+3VS
GND
+3V+3V
GNDGND
+3V
+3VS
+3VS
+3VS +3V +3V
+5V +3VS
+3VS
+3V
R301 0/NA 04025%1 2
R381
2.7K/NA0603D
12
R332 4.7K 04021 2
R365
2.7K/NA0603D
12
R379
2.7K0603D
12
R3592.7K/NA
0603D
12
R3782.7K/NA0603
12
R3732.7K0603
12
R34610K04025%
12
R3642.7K
0603D
12
R366
2.7K0603
12
R36210K/NA
0603D
12
C3940.1U0402+80-20%
12
R3802.7K/NA
0603D
12
R374
2.7K0603
12
R3171K04025%
12
RP65
4.7K*8 1206
12345 6
78910
R31110K04025%
12
R3602.7K/NA0603D
12
R302 4.7K 04021 2
R3632.7K/NA
0603D
12
R304 22 04021 2
R375
2.7K0603
12
D S
Q35 2N7002
G
D S
R354 4.7K 04021 2
R299 4.7K 04021 2
R3523830603
12
R3722.7K0603
12
R367
2.7K0603
12
C3490.1U0402+80-20%
12
C39310U0805+80-20%
12
R3612.7K/NA0603D
12
R377
2.7K/NA0603
12
R3511K04025%
12
D S
Q372N7002
G
D S
R300 22 04021 2
R312 4.7K 04021 2
R32410K04025%
12
RP56
10K*8 1206
12345 6
78910
R3193830603
12
R371 1K 04025%1 2
R32910K04025%
12U20B
VT8235BGA451_36_1MM
AA24AA25AB24AC26AC24AD25AE26AF25AF26AD24AD26AC25AB23AB26AA26AA22
Y23V25V26
Y22W26Y24Y25Y26V24
W24
T3T2U3U2V1T1U1R3
AE24
AF24
AF15AD16AF16AF17AE17AD18AF18AE18AF19AD19AD20AF20AE20AD21AF21AE21
AE15AD22AF22AC21AD15AC23AD23AE23AC22AF23
AF4AD2AD5Y2AA1W3AC1W4Y3AB1
AA2AF2AF1AB2AB3AC2
AC3AA3
AE3AE5AE6AD6AC6
AF5AC7AF6
AA
4A
B4
AC
4A
C5
AC14AC13AF14AE14AD14AF13AE13AD13
F14
F10
F9 H5
J5 J21
K5
AE12AF10AF12AD12
N13
N15
N16
AF9
AC10AD9
AD10
AF11AE11AD11AC11
AE2
N14
P11
K21
T5 T21
U5
U21
U22
F15
V5
AB
8A
B9
AB
16A
B17
AD17
L12
L13
L14
L15
L16
L23
L25
M11
M12
M13
M14
M15
M16
N5
N11
N12
AC15
W22
W23
F11
F6 AB
25A
B22
PDD0PDD1PDD2PDD3PDD4PDD5PDD6PDD7PDD8PDD9PDD10PDD11PDD12PDD13PDD14PDD15
PDA0PDA1PDA2
PDDREQPDDACK#PDIOR#/PHDMARDY/PHSTROBEPDIOW#/PSTOPPDRDY/PDDMARDY/PDSTROBEPDCS1#PDCS3#
ACBITCLKACSDIN0ACSDIN1
ACSDIN2/GPI20/GPO20ACSDIN3/GPI21/GPO20
ACSYNCACSDO
ACRST#
IRQ14
IRQ15
SA0/SDD0SA1/SDD1SA2/SDD2SA3/SDD3SA4/SDD4SA5/SDD5SA6/SDD6SA7/SDD7SA8/SDD8SA9/SDD9SA10/SDD10SA11/SDD11SA12/SDD12SA13/SDD13SA14/SDD14SA15/SDD15
SDDRQSDDACK#SDIOR#/SHDMARDY/SHSTROBESDIOW#/SSTOPSDRDY/SDDMARDY/SDSTROBESDCS1#SDCS3#SDA0SDA1SDA2
PWRGDPWRBTN#RSMRST#
RING#/GPI3EXTSMI#/GPI2
PME#/GPI6LID#/GPI4
BATLOW#/GPI5SUSST1#/GPO3SUSCLK/GPO4
SUSA#/GPO1SUSB#/GPO2
SUSC#SMBALRT#/GPI7
SMBCK1SMBDT1
GPI1GPO0
GPI0GPIOA/GPI24/GPO24GPIOC/GPI25/GPO25GPIOD/GPI30/GPO30GPIOE/GPI31/GPO31
PCLKRUN#CPUSTP#/GPO5PCISTP#/GPO6
VS
US
33V
SU
S33
VS
US
33V
SU
S33
XD0XD1XD2XD3XD4XD5XD6XD7
VD
DV
DD
VD
D
VD
DV
DD
VD
DV
DD
MEMR#MEMW#
ROMCS#/KBCS#SOE#
GN
D
GN
DG
ND
TEST
IOR#/GPI22/GPO22IOW#/GPI23/GPO23
IORDY#/GPI19
SA16/GPO16SA17/GPO17SA18/GPO18SA19/GPO19
PWROK#
GN
D
GN
D
VD
DV
DD
VD
DV
DD
VD
DV
DD
VD
D
VD
DV
DD
VD
DV
DD
VD
D
SVREF
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
SCOMPP
PVREF
PCOMPP
GN
DG
ND
GN
DG
ND
C3920.1U0402+80-20%
12
R305 22 04021 2
R32610K/NA04025%
12
R1
Q34
DTC144TKA/NA
2
13
R347 4.7K 04021 2
R315 360 04021%1 2
C3340.1U0402+80-20%
12
RP67
10K*8 1206
12345 6
78910
TP81
R322 10K 04021 2
R34410K04025%
12
R3582.7K/NA0603D
12
R37610K
0603D
12
R350 360 04021%1 2
C35010U0805+80-20%
12
IDE_PDIOW#13
IDE_PDDACK#13
IDE_PDCS1#13
IDE_PDIOR#13
IDE_PDA113IDE_PDA013
IDE_PDDREQ13
IDE_IRQ1413
IDE_PIORDY13
IDE_PDA213
IDE_PDCS3#13
IDE_IRQ1513
IDE_SDA013
IDE_SDCS1#13
IDE_SDIOW#13
IDE_SDA113
IDE_SIORDY13
IDE_SDDACK#13
IDE_SDA213
IDE_SDDREQ13
IDE_SDIOR#13
IDE_SDCS3#13
AC97_RST# 15,16,18
AC97_SDIN 18
AC97_SYNC 15,16,18
AC97_BITCLK 15,16,18
MDC_SDIN 15,16
AC97_SDOUT 15,16,18
IDE_PDD[0..15]13
IDE_SDD[0..15]13,17
PWROK_SB 3,7,20SB_PWRBTN# 19RSMRST# 19WAKE_UP# 19EXTSMI# 19SCI# 19
SUSST1# 7
SUSA# 5SUSB# 19,20,22SUSC# 19,21
MINIPCI_PD 15
CLKRUN# 14,15
SMB_DATA0 4,5
SMB_CLK0 4,5
MPCI_PME# 14,15
CARD_PME# 14,15
AGP_PME# 14,15
MII_PWRDWN 16
CRT_IN# 11
ISA_SD0 17ISA_SD1 17ISA_SD2 17ISA_SD3 17
ISA_SD5 17ISA_SD6 17ISA_SD7 17
ISA_SD4 17
ISA_ROMCS# 17
ISA_SA16 17ISA_SA17 17ISA_SA18 17
ISA_MEMR# 17ISA_MEMW# 17
ISA_SOE# 17
LCD_ID1 12
SB_GPO0 18
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SB VIA_VT8235CD (3/3)是否能改為+2.5VS_DDR
Sec soure 291000010209
<Doc> R00
<Title>
C
10 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
VAD0VAD1VAD2VAD3VAD4VAD5VAD6VAD7
VAD[0..7]
SB_VPAR
SB_VLREF
SB_VCOMPP
SB_VCOMPP
SB_VPAR
LAD0LAD1LAD2LAD3
LREQ
LFRAME#
SERIRQ
SPKR
SB_WSC
SB_APICCLKSB_APICD1
SB_WSC
SB_APICD1
SB_APICCLK
SB_APICD0
SB_APICD0
SB_RAMGND
SB_RAMVCC
SB_PLLVCC
SB_RAMVCC
SB_RAMGND
SB_PLLVCC
SB_PLLGND
SB_PLLGND
RTCX2
RTCX1RTCX2
EEDOEEDIEESKEECS
EEDOEEDI
EECS
EESK
SB_GHI#SB_VIDSELSB_VRDSLPSB_AGPBZ#
SB_IGNNE#
SB_A20M#
SB_INIT#SB_INTR
SB_FERR#
SB_NMISB_SLP#SB_SMI#SB_STPCLK#
RTCX1
SB_GHI#
SB_AGPBZ#
SB_VRDSLP
SB_VIDSELGPIO27GPIO26
GPI18
INTRUDER#
INTRUDER#
GPI17
MTXC
MRXC
MTXC
MRXCSB_INIT#
SB_FERR#
SB_INTR
SB_IGNNE#SB_A20M#
SB_NMISB_SMI#SB_STPCLK#
GPIO27GPIO26
GPI17GPI18
SERIRQ
LFRAME#LAD2LAD1
LAD3
LREQLAD0
SB_SLP#
LAN_MTXE
LAN_MTXE
SB_SLP#
SB_VLREF
SPKR
+2.5V
GND
+2.5V
GND
+2.5V +2.5VS +3VS
+3V
GND
+2.5V
GND
+2.5V
GNDGND
+3V
+3V
GND
GNDGND
+3VS
+VCC_RTC
GND
+VCC_RTC
GND +SVDD3
GND
+VCC_RTC
+3V
GND
+3VS
+3V
+2.5V
GNDGND
GND
+3V
GND
R318 1K 04021 2
C3760.1U0402
50V+80-20%
12
C32610U080510V+80-20%
12
R306 10K 04021 2
R316 330 04021 2
R349
10K/NA0402
12
RP72 470*4 08041234
5678
R345 10M 04021 2
R45040204021%
12
U20C
VT8235BGA451_36_1MM
F25F26J26J25E26E24K24K26
T25U26T26R25T23R23U25T24R26
B13C13
B11A11C12B12
A12C11
C9B9
A9
D10
C10B10A10
D9
A13A14B14C14
E7
P22
P23
D25F23G23G22H22G24J22K22
F24
D26
J23
L26
K25J24H24H26G25G26
K23
E8
D12
E11
E12
U24T22V23U23
AD1AE1
Y4Y1
AD3
AE10
AE9AC12
AE4
L24
D11
P12
P13
P14
P15
P16
R4
R11
R12
R13
P25P24
R24
P26
R14
R15
R16
T11
T12
T13
T14
T15
T16
V4
V21
AA
5W
25W
21V
22
AA
23A
B5
AB
12A
B13
AB
18A
B19
AC
16A
C17
AC
20A
E16
AE
19A
E22
AE
25
F22
G21
H21
L21
L22
M21
M22
M23
M24
M25
M26
N21
N22
N23
N24
N25
N26
AD4AF3
AF8AE8AD8AF7
AD7
AE7
E10
A8
D13
E13
VD0VD1VD2VD3VD4VD5VD6VD7
A20M#FERR#
IGNNE#INIT#INTRNMI
SLP#/GPO7SMI#
STPCLK#
MCRSMCOL
MTXD2MTXD1MTXD0
MTXENA
MTXCLKMTXD3
MDCKMDIO
MRXD3
MRXD1
MRXDVMRXCLKMRXERR
MRXD2
EECS#EEDOEEDI
EECK
RAMVCC
PLLVCC
PLLGND
VD8VD9VD10VD11VD12VD13VD14VD15
VBE0#
VPAR
VLREF
VBE1#
UPCMDDNCMDUPSTBUPSTB#DNSTBDNSTB#
VCOMPP
RAMGND
MIIV
CC
MIIV
CC
MIIV
CC
WSC/APICREQ#APICD0/APICCS/GPI28/GPO28APICD1/APICACK/GPI29/GPO29APICCLK
SMBDT2/GPI26/GPO26SMBCK2/GPI27/GPO27
AOLGPI/GPI18/THRM#CPUMISS/GPI17INTRUDER#/GPI16
SERIRQ
SPKROSCVBAT
VCLK
MIIV
CC
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
VIDSELVRDSLP
GHI#/GPIO22
DPSLP#/GPIO23
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
VC
CV
KV
CC
VK
VC
CV
KV
CC
VK
VC
CV
KV
CC
VK
VC
CV
KV
CC
VK
VC
CV
KV
CC
VK
VC
CV
KV
CC
VK
VC
CV
KV
CC
VK
VC
CV
KV
CC
VK
VC
CV
K
RTCX1RTCX2
LAD0LAD1LAD2LAD3
LREQ
LFRAME#
MRXD0
AGPBZ#MIIS
US
25M
IISU
S25
C3541U0402
10V+80-20%
12
L64120Z/100M
20121 2
D17
BAT54C
1
23
R56 10K 04021 2
TP71
U15
NM93C46SO8
1234 5
678CS
SKDIDO GND
NC0NC1VCC
U22B
74HCT08_VTSSOP14
4
56
147
C35618P
25V0603
10%
12
L79120Z/100M
20121 2
RP60
10K*8 1206
12345 6
78910
R309 1K 04021 2
C33110U080510V+80-20%
12
R443 10K 04021 2
C34710U080510V+80-20%
12
RP66
10K*8 1206
12345 6
78910
X5
32.768KHZ
1 4
L66120Z/100M
20121 2
R308 4.7K 04021 2
C33210U080510V+80-20%
12
C17710U080510V+80-20%
12
R444 10K 04021 2
R2724.7K/NA04025%
12
C3581U0402
10V+80-20%
12
R357 4.7K 04021 2RP52 22*4 08041234
5678
R479
2204025%
1 2
R307 1K/NA 04021 2
R59 22 0402 5%12
R290 8.2K 04021 2
R95 0/NA 04021 2
C32310U080510V+80-20%
12
R445 360 04021%1 2
C3790.1U0402
50V+80-20%
12
C3081U0402
6.3V+80-20%
12
C35518P
25V0603
10%
12
R330 4.7K 04021 2
R283 0 04021 2
R93 22 04025%1 2
R310 10K 04021 2C406220P0402
50V10%
12
R276 10K 04021 2
C3240.1U0402
50V+80-20%
12
RP73 470*4 08041234
5678
R436
10K0402
12
J20
1.25MM/ST/MA-2ACES85205-0200
12
R284 0 04021 2
R92 22 04025%1 2
R368 1K 04025%1 2
R4483K04021%
12
L80120Z/100M
20121 2
C3200.1U0402
50V+80-20%
12
VAD[0..7]7
VBE#7
VPAR7
DNCMD7
UPSTB#7DNSTB7DNSTB#7
UPSTB7
UPCMD7
SB_VCLK5
LAD015,19
LAD215,19LAD315,19
LAD115,19
LFRAME#15,19
LDRQ0#15
SERIRQ14,15,19
SB_SPKR1814M_SB_IOSC5
LAN_MTXE 16
LAN_MTXD1 16
LAN_MTXD3 16
LAN_MRXER 16
LAN_MRXD3 16
LAN_MTXD0 16
LAN_DATAIO 16
LAN_CRS 16
LAN_MRXDV 16
LAN_MRXD1 16LAN_MRXD2 16
LAN_MTXD2 16
LAN_COL 16
LAN_MRXD0 16
LAN_DCLK 16
14M_SB_APICCLK5
SB_THRM#19
LAN_MTXC 16
LAN_MRXC 16
AGP_8X#7
LDTSTOP# 2,6
LCD_ID012
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MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S-VIDEO
Exte
rnal
VG
A Co
nnec
tor
W/S=12/12/12/12/12 milsClose to VGA Connector
TV Encoder(VIA_VT1622)
<Doc> R00
<Title>
C
11 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
TV_DSTV_TE
TV_DS
TV_TE
TV_CRMATV_LUMA
TV_COMP
TV_RSET
TV_CONF_XLTTV_ADDR
TV_ADDRTV_CONF_XLT
TV_VSO
TV_BCO
TV_CSO TV_BCO
TV_CSO
TV_VSO
CRT_BLUE
CRT_RED
CRT_GREEN
CRT_DDCK
CRT_DDDAHSYNC_CON
CRT_IN#
TV_RSET
TV_LUMA
TV_CRMA
TV_COMP
TVD12TVD13TVD14TVD15
TVD12
TVD13
TVD14
TVD15
VSYNC_CON
GND
GND
GND_TVIC
+3V_TV
TV_VDD
TV_VDDA1
TV_VDDA2
TV_VDDA2
+3V +3V
GND
+2.5V
+2.5V
TV_VDDA2
+3V
TV_VDDA1
+3V
GND_TV GND_TV
GND_TV
GND_TV
+3V
+3V
GND_CRT15GND_CRT15
+3V
GND_CRT15
+3V
GND_CRT15
GND GND
GND_CRT15
GND
GND
GND
GND_TVIC GND
+2.5V TV_VDD
GNDGND
+5V
GND
GND
+5V
GND_TVIC
GND_TVIC
GND
GND
GND
+3V_TV
L18120Z/100M1608 1 2
L29120Z/100M
20121 2
R57 0 06031 2
U4074HCT1G126SC70_5
2
53
4
1
L16120Z/100M1608 1 2
R7510K/NA04025%
12
L9 2.7uH 16081 2
C46270P0402
50V+/-10%
12
R421 51 06031 2
L17120Z/100M1608 1 2
R422 51 06031 2
X6
14.318MHZ274011431414
1 2
L15120Z/100M1608 1 2
C41222P0402
50V+/-10%
12
DS
Q5
2N7002
G
DS
C52 0.1U0402+80-20%
1 2
R82 10K 04021 2
C5270P0402
50V+/-10%
12
R419 1M/NA 04025%
1 2
C5310U080510V+80-20%
12
R12
1K04021%
1 2
R8010K04025%
12
C3980.1U0402
50V+80-20%
12
C70 10P/NA0402+/-10%
1 2
U3974HCT1G126SC70_5
2
53
4
1
L1
JP_BEAD_DFS
1 2
R682.2K0402
5%
12
R692.2K04025%
12
C48270P0402
50V+/-10%
12
R1310K04025%
12
R38 0 04025%1 2
C6910U080510V+80-20%
12
R79 10K 04021 2
R423 33 04025%
1 2
C39627P04025%
12
R113 10K 04021 2
DS
Q6
2N7002
G
DS
D8
BAV99/NA
123
R119 0 04025%1 2
R8410K/NA04025%
12
RP475*41206
1234
8765
U3
VT1622PQFP64_0.5MM
2322
25
2761
29545860
2120
303134353637384142434445
64159
264057
55
7
2
3
19
46475051
53
13
18324859
63481115
243956
17334962
6
10121416
5228
HSYNCVSYNC
XCLK
P_OUTBCO
DSTECSO/HSOVSO
SBDSBC
PD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11
VDDA1VDDA2VDDA3VDDA4
VCC_0VCC_1VCC_2
CONF_XLT
RSET
XI
XO/FIN
RESETN
PD12PD13PD14PD15
ADDR
VDDA4_1
VDD_0VDD_1VDD_2VDD_3
GNDA1GNDA2GNDA3GNDA4
GNDA4_1
VSS_0VSS_1VSS_2
GND_0GND_1GND_2GND_3
COMP
DACADACBDACCDACD
NC1NC0
C66 10P0402+/-10%
1 2
L27120Z/100M
20121 2
R55 4.64K 04021%1 2
C39710U080510V+80-20%
12
C670.1U0402
50V+80-20%
12
CP122P*41206
1234
8765
C550.1U0402
50V+80-20%
12
C680.01U0402
50V+80-20%
12
R94 10K 04021 2
CP222P*41206
1234
8765
R112 10K 04021 2
C590.01U0402
50V+80-20%
12
C39527P04025%
12
L13 120Z/100M 16081 2
L14 120Z/100M 16081 2
R89 10K 04021 2
C41122P0402
50V+/-10%
12
C64 10P0402+/-10%
1 2
C3990.01U0402
50V+80-20%
12
L501 600Z/100M/NA16081 2
C7270P0402
50V+/-10%
12
C5710U080510V+80-20%
12
R8310K04025%
12
C620.1U0402
50V+80-20%
12
L30120Z/100M
20121 2
L11 2.7uH 16081 2
L10 2.7uH 16081 2
C1100P0402
50V10%
12
C47270P0402
50V+/-10%
12
J1
7P/RASUYIN33007S-07T1-C
123456
GND1GND2
7
123456
GND1GND2
7
C560.01U0402
50V+80-20%
12
J2
VGASUYIN
7535S-15G2T-05CONN_SYN7535S_15GT
331720015071
192
103
114
125
136
147
158
17
16
RP2
75*41206
1234
8765
L8 BEAD_600Z/100M/NA0603D
1 2
L100600Z/100M/NA16081 2
L12 120Z/100M 16081 2
C41022P0402
50V+/-10%
12
D10
BAV99/NA
1 23
D9
BAV99/NA
123
R420 33 04025%
1 2
L99120Z/100M
20121 2
C6270P0402
50V+/-10%
12
TVD37
TVD97TVD87
TVD17
TVHS7
TVD47
TVD67
TVVS7
TVD117
TVD27
TVCLK7
TVD07
TVD77
TVD107
TVD57
TV_PCIRST# 7,8,19
CRT_HSYNC7
CRT_RED7
CRT_DDCK7
CRT_DDDA7
CRT_BLUE7
CRT_GREEN7
CRT_VSYNC7
I2C_DATA7I2C_CLK7
TVCLKI7
TV_DS7
CRT_IN# 9
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
High Remove R8Install R10
For one channel panelDUAL (pin23)
For two channel panelLow Remove R10
Install R8
VREF near pin 78
1
LCD Panel ID
XGA
XGA1
LCDID2
CLOSE TO AO3400
X
XGA
1
1
S/W/W/S=10/8/8/10 mils
Hannstar
XGA
00
1Lg-Phillips
HSD150PX14-A
LP150X08-A3
VENDOR
Hydis
1
AU0
LCDID1
0
四組各自平行走線等長
HT15X34-100
PANELLCDID0
1
as short as possible
01
0
0
B150XG02-1
XGA
Close to LCD Connector
40 mils
1
XGA
Layout Note:
LCD Connector+Inverter
0
QDIQD15XL06-01-20
0
X
40 mils
0
Samsung
LCD 14" 330mA,15"800mA
1
LPN150XB-L03
0
1
1
LVDS Encoder(VIA_VT1634)
<Doc> R00
<Title>
C
12 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
LVDS_D0LVDS_D1LVDS_D2LVDS_D3LVDS_D4
LVDS_D7
LVDS_D5LVDS_D6
LVDS_D8LVDS_D9
LVDS_D10LVDS_D11
LV_A0LV_A1LV_A2
LV_TST1
LV_A2LV_TST1
LV_A0LV_A1
LV_I2SEL
LV_PD#
LV_INTR
LV_INTR
LV_PD#
LV_I2SEL
LV_DUAL
LV_EDGE
LV_DUAL
LV_EDGE
TXCLK-TXCLK+
TXOUT0-TXOUT0+
TXOUT1+TXOUT1-
TXOUT2+TXOUT2-
LVDS_VSYNC
LVDS_DELVDS_CLKIN+LVDS_CLKIN-LVDS_HSYNC
LVDS_D12LVDS_D13LVDS_D14
LVDS_D15LVDS_D16LVDS_D17LVDS_D18LVDS_D19
LVDS_D20LVDS_D21LVDS_D22LVDS_D23
LVDS_D0LVDS_D1LVDS_D2LVDS_D3
LVDS_D5
LVDS_D7LVDS_D6
LVDS_D4
LVDS_D9
LVDS_D11LVDS_D10
LVDS_D8
LVDS_D13
LVDS_D15LVDS_D14
LVDS_D12
LVDS_D17
LVDS_D19LVDS_D18
LVDS_D16
LVDS_D21
LVDS_D23LVDS_D22
LVDS_D20
LVDS_DE
LVDS_CLKIN+LVDS_CLKIN-LVDS_HSYNCLVDS_VSYNC
LVDS_VREF
LVDS_VREF
TXOUT0-TXOUT1+
TXCLK-
ENAVDD
TXOUT0+
TXOUT2+
LCD_ID0
TXOUT1-
LCDVCC
LCD_ID1
TXOUT2-TXCLK+
LV_RES1
LV_RES1
LCD_ID1LCD_ID0
LV_I2SEL
LCD_ID2
LCD_ID2
GND
PLLGND
LVDSGND
PLLGND
LVDSGNDGND
GND
GND
+2.5V
GND
+2.5V LVDSVCC
LVDSVCC
DVDD
I2CVCC
PLLVCC
+2.5V
DVDD+2.5V
I2CVCC+2.5V
PLLVCC+2.5V
GND
+1.5V
PWR_VDDIN
+3V
GNDGNDGND
GND GND GND GND
GND
GND
GND
DVMAIN
+1.5V
LVDSGND
PLLGND
GND
GND
+3V
GND
GND
GND
GND
GND
+3V
R199 22 04025%1 2
R182 22 04025%1 2
J8
MA/15PX2/STACES87216-3002
13579
11131517
246810121416182019
GND1GND2
2123252729
2224262830
C1550.1U0402
50V+80-20%
12
RP12 22*4 0804
1234
5678
C2010U/NA
10V1206
12
C210.1U0402
16V+80-20%
12
C1130.1U0402
50V+80-20%
12
C430.1U040216V1
2
R122 0/NA 06031 2
R193 22 04025%1 2
RP1
10K*41206
1234
8765
RP8 22*4 0804
1234
5678
C3150.1U0402
50V+80-20%
12
R196 4.7K/NA 04021 2
R18810K04025%
12
C4140.1U0402+80-20%
12
R198 22 04025%1 2
C1760.1U0402
50V+80-20%
12
C1540.01U0402
50V+80-20%
12
C1780.1U0402
50V+80-20%
12R41 0 04025%1 2
C10510U080510V+80-20%
12
R140 4.7K 04021 2
R19010K04025%
12
L370 0603
1 2
RP10 22*4 0804
1234
5678
C4150.1U0402+80-20%
12
C221000P0402
50V10%
12
U9
VT1634PQFP100_0.5MM
50
47
45
39
37
34
32
29
49
46
44
38
36
33
31
28
42
27
41
26
8887
9493929190
8986858483
8281876
54321
100999897
6059
23
18
911526971778096
25354351
141517
75
61
68
21
67
22
304048
78
74
58575655
636465
7273
1016
1213192024546266
76
53707995
A0-
A1-
A2-
A3-
RESERVED_9
RESERVED_7
RESERVED_5
RESERVED_3
A0+
A1+
A2+
A3+
RESERVED_8
RESERVED_6
RESERVED_4
RESERVED_2
CLK1-
RESERVED_1
CLK1+
RESERVED_0
CLKIN-CLKIN+
D0D1D2D3D4
D5D6D7D8D9
D10D11D12D13D14
D15D16D17D18D19
D20D21D22D23
DSEL/I2CDATI2CCLK
DUAL
EDGE
GND_0GND_1GND_2GND_3GND_4GND_5GND_6GND_7
GNDLVDS_0GNDLVDS_1GNDLVDS_2GNDLVDS_3
GNDPLL_0GNDPLL_1GNDPLL_2
HSYNC
I2CSEL
I2CVCC
INTR
MODSEL
PD#
VCCLVDS_0VCCLVDS_1VCCLVDS_2
VREF
VSYNC
GPIO1-1GPIO1-2GPIO2-1GPIO2-2
A0A1A2
TST1TST2
VCCPLL_0VCCPLL_1
RESERVED1RESERVED2_0RESERVED2_1RESERVED2_2RESERVED2_3RESERVED2_4RESERVED2_5RESERVED2_6
DE
VCC_0VCC_1VCC_2VCC_3
RP13 0*4 0804
1234
5678
C190.1U0402
16V+80-20%
12
R1Q1
DTC144TKA
2
13
C4130.1U0402+80-20%
12
L6 120Z/100M 1608
1 2
R129 0 04025%1 2
RP11 22*4 0804
1234
5678
DS
Q2AO3400
SOT23_FET
G
DS
C421000P0402
50V10%
12
C18310U080510V+80-20%
12
C1120.01U0402
50V+80-20%
12
L360 0603
1 2
R197 4.7K 04021 2
C18410U080510V+80-20%
12
C4160.1U0402+80-20%
12
RP7 22*4 0804
1234
5678
R43310K0603
12
RP31K*41206
1234
8765
D1
BAW56
2
13
R144 4.7K 04021 2
L35120Z/100M
20121 2
RP9 22*4 0804
1234
5678
R143 4.7K 04021 2
R32
470K 0402
1 2
R415 4.7K 04021 2
L44120Z/100M
20121 2
C1790.01U0402
50V+80-20%
12
R141 4.7K 04021 2
C15810U080510V+80-20%
12R179 22 04025%1 2
L46120Z/100M
20121 2
L42120Z/100M
20121 2
C440.1U0402
16V+80-20%
12
C1750.01U0402
50V+80-20%
12
R102 0 04021 2
R106 0/NA 04021 2
R124BEAD_600Z/100M
0603D1 2
L25 120Z/100M 1608
1 2
R142 4.7K 04021 2
C4240.1U0402
50V+80-20%
12
NB_FPD007NB_FPD017NB_FPD027NB_FPD037
NB_FPD047
NB_FPD077
NB_FPD057NB_FPD067
NB_FPD087
NB_FPD117
NB_FPD097NB_FPD107
NB_FPD127
NB_FPD157
NB_FPD137NB_FPD147
NB_FPD167
NB_FPD197
NB_FPD177NB_FPD187
NB_FPD207
NB_FPD237
NB_FPD217NB_FPD227
NB_FPDE7
NB_FPCLK+7NB_FPCLK-7NB_FPHS7NB_FPVS7
ENPBLT7
ENAVDD 7
BLADJ 19
I2C_DATA_LVDS 7I2C_CLK_LVDS 7
ENAVEE 7
ENBL_SB8
LCD_ID010LCD_ID19LCD_ID28
ENBL_KBC19
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Close to IDE Connector
Seco
ndar
y EI
DE
Con
nect
orW/S=10/10/10/10 mils
SW_LEFT
SW_RIGHT
Close to IDE Connector
Prim
ary
EIDE
Con
nect
or
HDD & CD_ROM Conntor
Sec soure 291000150607
Sec soure 331000050005
Sec soure 331030044023
Sec soure 297040100027
Sec soure 297040100027
<Doc> R00
<Title>
C
13 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
HDD_PDA1
CD_SDD7
CD_SDCS1#
HDD_PIORDY
CD_SDD3
HDD_PDD0
CD_SDIOW#
HDD_PDD15
HDD_PDA2
HDD_PDD12
CD_SDA1
CD_SDDACK#
HDD_PDIOR#
T_DATA
HDD_PDD5
HDD_PDD14
HDD_PDD4
HDD_PDDACK#
CDROM_COMM
CDROM_RIGHT
HDD_PDDREQ
CD_SDD6
IDERST#
CD_SDA0
HDD_PDD13
CD_SDD12
HDD_PDCS1#
CD_SDD13
HDD_PDD3
HDD_IRQ14
CDROM_LEFT
CD_SDD5CD_SDD10
HDD_PDCS3#
CABLE_SEL
CD_SDD14
CD_SDD4
CD_SDIOR#
HDD_LED#
CD_SDA2
HDD_PDIOW#
CD_SDD15
CD_SIORDY
HDD_PDD7
CD_SDD11
HDD_PDD2
CD_SDD9
CD_SDD2
HDD_PDD9
HDD_PDD1
CD_SDD1
HDD_PDD8
HDD_PDA0
CD_SDD8
CD_IRQ15
HDD_PDD6
HDD_PDD11
CDROM_LED#
CD_SDD0
IDERST#
CD_SDDREQ
T_CLK
HDD_PDD10
IDE_PDD0
IDE_PDD5
IDE_PDD3IDE_PDD2IDE_PDD1
IDE_PDD7IDE_PDD6
IDE_PDD4
IDE_PDD13
IDE_PDD8
IDE_PDD10IDE_PDD9
IDE_PDD14
IDE_PDD12
IDE_PDD15
IDE_PDD11
HDD_PDD7
IDE_PDD[0..15]
HDD_PDA2HDD_PDCS3#
HDD_PDDACK#
HDD_PDIOW#HDD_IRQ14
HDD_PIORDY
HDD_PDA0
HDD_PDA1HDD_PDIOR#
HDD_PDCS1#
HDD_PDDREQ
HDD_PDD15
HDD_PDD11
HDD_PDD13
HDD_PDD10
HDD_PDD14
HDD_PDD12
HDD_PDD8HDD_PDD9
HDD_PDD0HDD_PDD1HDD_PDD2HDD_PDD3HDD_PDD4HDD_PDD5HDD_PDD6HDD_PDD7
CD_SDD7
IDE_SDD8
IDE_SDD1
CD_SDD8
CD_SDD10
CD_SDD0
IDE_SDD2 CD_SDD2
IDE_SDD12
CD_SDD1
IDE_SDD6
CD_SDD14
CD_SDD7
CD_SDD12
IDE_SDD3
IDE_SDD14
CD_SDD9
CD_SDD15
CD_SDD4
IDE_SDD10
IDE_SDD7
CD_SDD3IDE_SDD4
CD_SDD13
IDE_SDD[0..15]
IDE_SDD9
IDE_SDD5
IDE_SDD11
IDE_SDD0
IDE_SDD15
CD_SDD11
IDE_SDD13
CD_SDD6CD_SDD5
CD_SDCS3#CD_SDDREQCD_SDDACK#
CD_SDCS3#
CD_SDA2
CD_SIORDY
CD_SDA0
CD_SDCS1#
CD_SDA1CD_SDIOW#
CD_SDIOR#CD_IRQ15
IDERST#
HDD_PIORDY
CD_SIORDY
HDD_PDDREQ
HDD_IRQ14
CD_SDDREQ
CD_IRQ15
HDD_LED#
CDROM_LED#
+5V
+5V
+5V
GND
GND GND
GND
GNDGND
GNDGNDGND
GND
GND
GND
+VDD3+3VS+3V+5V
GND
GND
GND
+5V+3V +3V
+3V
GND
GND
GND
+3V
+5VS
SW503TC010-PSS11CET297040105010
SW_TC010-PS11CETT-MEC(台灣美琪)
13
245
D503CL-190G AK
D15
ESD0805A/NA AK
C3140.1U0402
16V+80-20%
12
D506CL-190G AK
C3130.1U0402
16V+80-20%
12
R323470/NA04025%
12
D502CL-190G AK
R33533004025%
12
R226 10K 04021 2
R3565.6K04025%
12
RP68 0*8
RPX8
12345678 9
10111213141516
RP70 0*8
RPX8
12345678 9
10111213141516
R229
470 0402 5%
1 2D507CL-190G AK
R22833004025%
12
L69 120Z/100M 16081 2
C2540.1U0402
16V+80-20%
12
C2510.1U0402
16V+80-20%
12
R33733004025%
12RP59 0*8
RPX8
12345678 9
10111213141516
R426 0 04025%1 2
D501CL-190G AK
J14
FM/22PX2/2MMALLTOPC17834-144XX
135791113151719212325272931333537394143
2468
101214161820222426283032343638404244
GND0DD8DD9
DD10DD11DD12DD13DD14DD15
KEYGND3GND4GND5CSELGND6
IOCS16#PDIAG#
DA2CS#1GND7AVCC
RSV
RESET#DD7DD6DD5DD4DD3DD2DD1DD0GND1DMARQDIOW#DIOR#IORDYDMACK#INTRQDA1DA0CS#0DASP#DVDDGND2
L67 120Z/100M 16081 2
R22533004025%
12
C3410.1U0402
16V+80-20%
12
VG
SR
D510
19-22SRVGC/TR8
34
12
R33833004025%
12
J21
MA/0.8MM/RASPEED
K211-A503-507
214368
5
107
1214
9
16
11
1820
13
22
15
2426
17
28
19
3032
21
34
23
3638
25
40
27
4244
29
46
31
4850
333537394143454749
GND1GND2
ROUTLOUTNCAGND
DD8DD9
RESET#
DD10DD7
DD11DD12
DD6
DD13
DD5
DD14DD15
DD4
DIVARQ
DD3
DIOR#GND3
DD2
DMACK#
DD1
IOCS16#PDIAG#
DD0
DA2
GND
CS#1VCC2
DIOW#
VCC3
IORDY
VCC4GND4
INTRQ
GND5
DA1
GND6RSV2
DA0CS#0DASP#VCC0VCC1GND1GND2CSEL#RSV
GND7GND8
R42900603
12
R1
Q32
DTC144TKA
2
1 3
D13
BAW56/NA
2
13
R15433004025%
12
D16
ESD0805A/NAAK
D504CL-190G AK
R3285.6K04025%
12
R4300/NA0603
12
R32710K0402
5%
12
RP69 0*4
0804
1234
5678
R22733004025%
12
R384 10K 04021 2
R425 0 04025%1 2
R398 4.7K 04021 2
R385 10K 04021 2
R40233004025%
12
R325 10K 04021 2
SW504TC010-PSS11CET297040105010
SW_TC010-PS11CETT-MEC(台灣美琪)
13
245
RP63 0*8
RPX8
12345678 9
10111213141516
J18
FPC/FFC/0.5MM/6PACES20096-0600
123456
RP58 0*4
0804
1234
5678
R33110K0402
5%
12
R320 4.7K 04021 2
R4270/NA04025%
12
D505CL-190G AK
RP62 0*8
RPX8
12345678 9
10111213141516
RP61 0*8
RPX8
12345678 9
10111213141516
R34033004025%
12
J19
FPC/FFC/0.5MM/12P/NAACES 20096-1200
123456789
101112
CDROM_COMM 18
CDROM_RIGHT 18CDROM_LEFT 18
T_DATA19
T_CLK19
SCROLL#19
NUM#19
CAP#19
AC_POWER#19
BATT_POWER#19
BATT_R#19
BATT_G#19
IDE_PDD[0..15]9
IDE_PDDACK#9IDE_PDDREQ9
IDE_IRQ149
IDE_PDA19
IDE_PDA09
IDE_PDIOW#9
IDE_PIORDY9
IDE_PDCS1#9
IDE_PDIOR#9
IDE_PDCS3#9IDE_PDA29
IDE_SDD[0..15]9,17
IDE_IRQ159
IDE_SDA09
IDE_SDA19
IDE_SIORDY9
IDE_SDIOW#9
IDE_SDCS1#9
IDE_SDDREQ9
IDE_SDA29
IDE_SDIOR#9
IDE_SDDACK#9
IDE_SDCS3#9
IDE_PCIRST#8,14,15
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Close toTPS2211A
AD20
Close to TPS2211
PCMCIA CONTROLLER & CARDBUS SCOKETREQ0#/GNT0#
PCI_INTB#
CARD_VCC
VOLT
PCI1410 HAVE INTEGRATED ALL PULL UP RES ABOVE
CIRDY#
CPERR#
CVS1
CARD_VCC
CARD_VCC
CCD#1
CSTSCHG#
Car
d B
us S
ocke
t
+3V
CARD_VCC
CARD_VCC
CAUDIO
CVS2
PC CARD PULL UP
CCD#2
CSTOP#
CRST#
+3V
CARD_VCC
CARD_VCC
CBLOCK#
+3V
CARD_VCC
CREQ#
CARD_VCC
SIGNAL
CSERR#
CARD_VCC
CINT#
+3V
CARD_VCC
CTRDY#
CARD_VCC
CDEVSEL#
hoder 331000000303
<Doc> r00
<Title>
C
14 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
CAD19
SERIRQ
PCICLK_CARD
VPPEN0
CCLK
VCCEN#0
PCI_AD23
CAD7
CCBE#3
CAD5
CAD28
PCI_AD31
PCI_STOP#
CAD17
VCCEN#1
PCI_AD17
PCI_AD13
PCI_AD3
PCI_C/BE#2
CAD0
PCI_AD9
PCI_AD5
PCI_AD11
CIRDY#
VCCEN#0
PCI_LOCK#
PCI_AD1
CSTSCHG
CAD29
R2_D2
PCI_C/BE#3
VPPEN1
PCI_PAR
CAD31
VPPEN0
PCI_FRAME#
PCI_AD16
PCI_GNT0#
PCI_C/BE#0
PCI_AD22
CVS2
CAD13
CAD3
CAD1
CCLKRUN#PCI_REQ0#
CGNT#
CRST#
CAD26
VPPEN1
PCI_SERR#
CSERR#
CAD8
CSTOP#
CAD16
PCI_AD6
CAD25
PCI_C/BE#1
CAD23
CAD9
CAD2
CAD6
CINT#
PCI_AD10
R2_A18
PCI_AD7
CAD18
CAD11
PCI_AD18
PCI_AD4
PCI_AD8
PCI_AD14
CCD#1
CPAR
CAD4
R2_D14
CCD#2
CAD22
PCI_AD30
CFRAME#
PCI_AD29CAD30
CAUDIO
PCI_AD12
PCI_AD19
CCBE#2
CAD27
PCI_IRDY#
PCI_PERR#
PCI_AD2
CARD_PCIRST#
PCI_AD25
PCI_AD20
CPERR#
CVS1
CAD15
CAD20
VCCEN#1
PCI_DEVSEL#
CLKRUN#
CDEVSEL#
CBLOCK#
PCI_AD[0..31]
CAD12
CAD24
PCI_AD27
CTRDY#
CREQ#
PCI_AD24
CAD21
CAD14
PCI_TRDY#
PCI_AD0
CARD_PCIRST#
CARD_PME#
PCI_AD21
PCI_AD15
PCI_AD26
CCBE#1
PCI_AD28
PCI_AD20
CCBE#0
CAD10
CAD16
CAD6
CDEVSEL#
CVS1
CAD20
CAD12
CVS2CAD19
CAD24
CCD#2
CSERR#
R2_D14
CCBE#2
CGNT#
CAD7
CREQ#
CCD#1
CPERR#
CAD28CSTSCHG
CAD15
CAD2
CCBE#1
CAD9CCBE#0
CAD0
CAUDIOCCBE#3
CAD21
CAD18
CAD30
CAD13
CAD23
CAD11
CTRDY#
CAD22
CAD14
CAD5
CAD31
CBLOCK#
CAD4
CCLKRUN#
CAD26
CCLK
CPAR
R2_D2
CAD25
CAD3CAD1CAD1
CFRAME#
CSTOP#
CAD10
CINT#
CRST#
R2_A18
CAD8
CAD27
CIRDY#CAD17
CAD29
+5V
+VCCA
+3V
+3V
+3V
+VCCA
+VCCA
+VPPA
+VCCA
+VPPA
+VCCA
+VPPA
GND
GND
GNDGND
GND
GNDGND
GND
GND
GND
GND
+3V
+3V
+VCCA
+VCCA
R401 10K 04021 2
C3770.1U0402
16V+80-20%
12
C378270P0402
50V+/-10%
12
C357270P0402
50V+/-10%
12
R39110K04025%
12
C368
0.1U040216V
12
R399 10K 04021 2R400 10K 04021 2
R396 10K04025%
1 2
U26
CBI1410
PQFP144_0.5MM
18 30 44 50 14 66 86 102
122
138
63 73 74 71 72
90126
1441421411401391291281271241211201181161151139896979395929189878582838081777976
1081111101091071051011041331231061321031361191438410013111775137134135
1251129988
345789
1011151617192324252638394041434546474951525354555657
12273748
1321322829313336343512
20
597062
69686765646160
6 22 42 58 78 94 114
130
PC
I_V
CC
0P
CI_
VC
C1
PC
I_V
CC
2P
CI_
VC
C3
CO
RE
_VC
C0
CO
RE
_VC
C1
CO
RE
_VC
C2
CO
RE
_VC
C3
CO
RE
_VC
C4
CO
RE
_VC
C5
AU
X_V
CC
VC
CD
0#/V
CC
5#/S
DA
TV
CC
D1#
/VC
C3#
/SC
LKV
PP
D0/
VP
P_P
GM
/SLA
TV
PP
D1/
VP
P_V
CC
SKT_VCC0SKT_VCC1
CAD31CAD30CAD29CAD28CAD27CAD26CAD25CAD24CAD23CAD22CAD21CAD20CAD19CAD18CAD17CAD16CAD15CAD14CAD13CAD12CAD11CAD10CAD9CAD8CAD7CAD6CAD5CAD4CAD3CAD2CAD1CAD0
CCLKCFRAME#
CIRDY#CTRDY#
CDEVSEL#CSTOP#
CPARCPERR#CSERR#
CREQ#CGNT#CINT#
CBLOCK#CCLKRUN#
CRST#R2_D2
R2_D14R2_A18
CVS1CVS2
CCD1#CCD2#
CAUDIOCSTSCHG
CC/BE3#CC/BE2#CC/BE1#CC/BE0#
AD31AD30AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0
C/BE3#C/BE2#C/BE1#C/BE0#
IDSELPCI_CLKDEVSEL#FRAME#IRDY#TRDY#STOP#PARPERR#SERR#REQ#GNT#RST#
RI_OUT#/PME#SUSPEND#SPKR_OUT#
MF6MF5MF4MF3MF2MF1MF0
GN
D0
GN
D1
GN
D2
GN
D3
GN
D4
GN
D5
GN
D6
GN
D7
R38247K04025%
12
C3610.1U0402
16V+80-20%
12
C372
0.1U040216V
12
R397 10K04025%
1 2C365
0.1U040216V
12
R394 10K 04021 2
C3634.7U/NA
16V1206
12
C3600.1U0402
16V+80-20%
12
C367
0.1U040216V
12
U27
CP2211 SSOP16
12345678
161514131211109
VCCD0VCCD13.3VA3.3VB5VA5VBGNDOC
SHDNVDDP0VDDP1AVCCAAVCCBAVCCC
AVPP12V
C369
0.1U040216V
12
J502
FM/34PX2/1.27MMACECONMF-291000000009
123456789
10111213141516171819202122232425262728293031323334
35363738394041424344454647484950515253545556575859606162636465666768
GND1GND2GND3GND4GND5GND6GND7GND8
12345678910111213141516171819202122232425262728293031323334
35363738394041424344454647484950515253545556575859606162636465666768
GND1GND2GND3GND4GND5GND6GND7GND8
C373
0.1U040216V
12
C371
0.1U040216V
12
C3640.1U040216V
12
C3660.1U0402
16V+80-20%
12
C3740.1U040216V
12
R387 100 0402 1%1 2
C3704.7U/NA
16V1206
12
PCI_C/BE#28,15
PCI_PERR#8,15
PCI_REQ0#8
PCI_C/BE#18,15
SERIRQ10,15,19
PCI_IRDY#8,15
PCI_DEVSEL#8,15
PCI_INTB#8
PCI_STOP#8,15
PCI_SERR#8,15
PCI_C/BE#08,15
PCI_GNT0#8
PCI_PAR8,15
CARD_PCIRST#8,13,15
CARD_PME#9,15
PCI_AD[0..31]8,15
PCI_FRAME#8,15
CARDSPK#18
CLKRUN#9,15
PCI_TRDY#8,15
PCI_CARD_CLK5
PCI_C/BE#38,15
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Mini-PCI & USB 2.0
Close toMiniPCICONN.
Wireless LED
PIN24, 124 ARE AUX_POWER
REQ2#/GNT2#
MIN
I-PC
I TYP
E III
A
MINI-PCIPCI_INTD# \ INTC#AD21
Sec soure 291000001206
<Doc> R00
<Title>
C
15 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
MINI_LPC_AD3
LAD1
MINI_LPC_CLK
MINI_LPC_AD2
LFRAME#
MINI_LPC_AD1
LAD0
LAD3
LDRQ0#
PCI_SERIRQ MINI_PCI_SERIRQ
LAD2
MINI_LPC_FRAME#
MINI_LPC_LDRQ#
LPC_48M
MINI_LPC_AD0
LAD2
PCI_AD14
PCIRST#
PCI_FRAME#
PCI_AD25
PCI_AD9
PCI_AD16
WIRE_LED#
PCI_PERR#PCI_C/BE#1
MDC_SDINAC97_BITCLK
PCI_AD[0..31]
MPCI_PME#
CLKRUN#
PCI_PAR
WIRE_LED#
PCI_AD24
PCI_AD19
PCI_TRDY#
WIRE_LED
PCI_AD28
LAD0
PCI_AD3
PCI_SERR# PCI_STOP#
WIRE_LED
PCI_AD6
PCI_AD1
PCI_C/BE#3
PCI_AD21
MPCIACT#
PCI_AD11
PCI_AD7
PCI_AD12
PCI_AD17
PCI_AD26
MINIPCI_SPKR#
PCI_GNT2#
PCI_AD29
PCI_AD13
AC97_RST#
PCI_AD0
PCI_AD8
PCI_AD10
LAD1
PCI_AD30
PCI_INTC#
PCI_C/BE#2
PCI_AD22
PCI_REQ2#
PCI_AD2
PCI_AD23
PCI_AD27
PCI_DEVSEL#
AC97_SYNC
PCI_AD18
PCI_C/BE#0
PCI_AD31
PCI_AD4
LAD[0..3]
PCI_AD21
AC97_SDOUT
PCI_IRDY#
PCI_AD15
PCI_AD5
CLK_MINIPCI
PCI_AD20
MPCI_PD
MPCI_PD
MINI_LPC_AD2
MINI_LPC_AD0
MINI_PCI_SERIRQ
MINI_LPC_AD1
MINI_LPC_FRAME#
MINI_LPC_AD3
MINI_LPC_CLK
MINI_LPC_LDRQ#
LAD3
+5V
+5V
+3V
+3V
+5V
+5V
+3V
+3V
GND
GND
GND GNDGND
GND
R33933004025%
12
R476 0 0402 5%1 2
R127 22 04021 2R128 22 04021 2
R268 0 0402 5%1 2
D508
CL-190G
AK
R115 0/NA 04021 2
R116 0/NA 0402
1 2
R478 0 0402 5%1 2
R348 0 0402 5%1 2
C920.1U0402
16V+80-20%
12
C940.1U0402
16V+80-20%
12
C930.1U0402
16V+80-20%
12
J22
124P/0.8MM/H9.2TYCO1566678-1
GND1GND2
13579
111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101103105107109111113115117119121123
2468101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124
GND1GND2
TIPRX+RX-PJ7PJ8LED1_GRNPLED1_GRNNCHSGNDINTB#3.3V[0]RESERVED0GROUND0CLKGROUND1REQ#3.3V[1]AD[31]AD[29]GROUND2AD[27]AD[25]RESERVED1C/BE[3]#AD[23]GROUND3AD[21]AD[19]GROUND4AD[17]C/BE[2]#IRDY#3.3V[2]CLKRUN#SERR#GROUND5PERR#C/BE[1]#AD[14]GROUND6AD[12]AD[10]GROUND7AD[8]AD[7]3.3V[3]AD[5]RESERVED2AD[3]5V[0]AD[1]GROUND8AC_SYNCAC_SDATA_INAC_BIT_CLKAC_CODEC_ID1#MOD_AUDIO_MONAUDIO_GND0SYS_AUDIO_OUTSYS_AUDIO_OUT_GNDAUDIO_GND1RESERVED3VCC5VA
RINGTX+TX-PJ4PJ5
LED2_YELPLED2_YELN
RESERVED45V[1]
INTA#RESERVED5
3.3VAUX[0]RST#
3.3V[4]GNT#
GROUND9PME#
RESERVED6AD[30]3.3V[5]AD[28]AD[26]AD[24]IDSEL
GROUND10AD[22]AD[20]
PARAD[18]AD[16]
GROUND11FRAME#
TRDY#STOP#3.3V[6]
DEVSEL#GROUND12
AD[15]AD[13]AD[11]
GROUND13AD[9]
C/BE[0]#3.3V[7]
AD[6]AD[4]AD[2]AD[0]
RESERVED_WIP4[0]RESERVED_WIP4[1]
GROUND14M66EN
AC_SDATA_OUTAC_CODEC_ID0#
AC_RESET#RESERVED7GROUND15
SYS_AUDIO_INSYS_AUDIO_IN_GND
AUDIO_GND2MPCIACT#3.3VAUX[1]
R267 0 0402 5%1 2
R255 0 0402 5%1 2
RP5 0*4/NA 12061234
8765
C890.1U0402
16V+80-20%
12
R1
Q10
DTC144TKA
2
13
R269 0 0402 5%1 2
JS502
SHORT-SMT4
1 2
C790.1U0402
16V+80-20%
12
R472 0 0402 5%1 2
R120 100 04021 2
R11710K04025%
12
LAD010,19
SERIRQ10,14,19
LPC_48M5
LFRAME#10,19
LAD110,19
LAD310,19
LAD210,19
LDRQ0#10
AC97_SDOUT 9,16,18AC97_BITCLK9,16,18
AC97_RST# 9,16,18
PCI_DEVSEL# 8,14
LAD[0..3]10,19
PCI_C/BE#18,14
PCI_C/BE#0 8,14
PCI_FRAME# 8,14
PCI_PERR#8,14
MPCIACT# 8
MINIPCI_SPKR#18
CLKRUN#9,14
PCI_GNT1# 8
MINIPCI_PD9
PCI_TRDY# 8,14
PCI_IRDY#8,14
PCI_C/BE#38,14
PCI_AD[0..31]8,14
PCI_C/BE#28,14
MPCI_PME# 9,14
PCI_SERR#8,14
PCI_REQ1#8
PCI_INTC#8
MDC_SDIN9,16
PCI_PAR 8,14
MINI_PCIRST# 8,13,14
PCI_INTD# 8
PCI_STOP# 8,14
AC97_SYNC9,16,18
MINI_PCI_CLK5
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LAN PHY (VT6103L) & MDC
AUDIO CODEC ON DAUGHTER BOARD
Layout Note:
HIGH
S/W/W/S=10/8/8/10 mils二組中間須絕緣 , EX: GND SHIELDING
LOWMDC HARDWARE S TRAP
CLOSE TO VT6103L
CLOSE TO MDC
二組各自平行走線等長
PHY ADDRESS = 00000
CLOSE TO VT6103L
Mod
em D
ougt
her B
oard
CLOSE TO MDC
CLOSE TO CONN.
AUDIO CODEC ON MOTHER BDPIN 16
as short as possible
Sec soure 291000923002
Sec soure 291000010410
CLOSE TO CONN. Sec soure 291000810819
<Doc> R00
<Title>
C
16 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
RING
AC97_SYNC
PJ4
TXD-
AC97_RST#
PJ7
MONO_OUT
TIP
AC97_BITCLK
PJTX+
TIP
AC97_SDOUT
PJ4
PJ7
RING
PJTX-
MDC_SDIN
PJRX+
PJRX-
PJRX+
PJRX-
PJTX+
PJTX-
LAN_RST
FXEN
FXEN
TEST#
DUPLEX
ANE
SPEED
LAN_PD#
REXT
TXD+
RXIN+
RXIN-
REXT
LAN_DATAIO
LAN_MTXD0
LAN_MTXD3LAN_MTXD2LAN_MTXD1
LAN_MTXE
LAN_MRXC
LAN_MRXDVLAN_MRXER
TXD+TXD-
RXIN-RXIN+
SPEEDDUPLEXANE
TEST#
LAN_XI
LAN_DATAIO
LAN_MTXC
LAN_XI LAN_XO
LAN_CRSLAN_COL
LAN_XOLAN_MRXD3LAN_MRXD2LAN_MRXD1LAN_MRXD0
LAN_PD#
RING_1
TIP_1
TIP_1
RING_1
+3V
+3V
GND_45
GND_MDC
+5V
+3VSGND_MDC
GND_45
GND
GND
GND
+3VS_LAN
+3VS_LAN_PLL+3VS
GND_PLLGND
GND
GNDGNDGND
GND
GND_45 GND
GND
+3VS
GND_PLL
+3VS_LAN+3VS+3VS_LAN
+3VS_LAN_PLL
+3VS_LAN
+3VS
GNDGND
GND
+3VS_LAN
GND
GND
+3VS_LANGND
GND_MDC
GND_PLL
+5VS +5VS
+3V +3V
R36 10K 04021 2
R98
1M/NA0402
1 2
F501
MINISMDC110/NA
1 2
R51 10K 04021 2
U4
LF_H41SSOX16
678
11109
123
161514
45
1213
TD+TDCTD-
TX+CMT
TX-
RD+RDCRD-
RX+RXCRX-
NC0NC1
NC2NC3
C8722P06035%
12
L31 120nH 16081 2
L32120Z/100M
20121 2
R342 4.7K 04021 2
R50 5.1K/NA 04021 2
C6661000P
3KV1808
10%
12
R487504021%
12
R71 22 04021 2
R497504021%
12
R45 0/NA 04021 2R74 22 04021 2
C4230.1U040210% 1
2
R87 1.5K 04021 2
R477504021%
12
R34 0 06031 2
R467504021%
12
J15
FM/0.8MM/H8.4AMP 3-1473293-0
13579
11131517192123252729
24681012141618202224262830
C750.1U0402
50V+80-20%
12
L33120Z/100M
20121 2
R7849.904021%
12
C8522P06035%
12
RP6 22*4 08041234
5678
C21000P
3KV1808
10%
12
R343 0/NA 04021 2
TP505 1
R413 22 04021 2
C741000P
3KV1808
10%
12
L19400UH
21
35
R334 22 04021 2
X1
25MHZ
1 2
R35 5.1K/NA 04021%
1 2
R341 22 04021 2R336 22 04021 2
C730.1U0402
16V10%
12
L105400UH
21
35
C650.1U0402
16V10%
12
C4090.1U0402
16V10%
12
R867
0 04025%
1 2
C540.1U040216V1
2
R6649.904021%
12
JS1
SHORT-SMT4
1 2S1Protector/NA
1808A
12
C4220.1U040210% 1
2
C61
4.7P/NA0603
1 2
R62 22 04021 2
C1671U0402
6.3V+80-20%
12
S501Protector/NA
1808A
12
R5
0 04025%
1 2
R54 22 04021 2
C31000P
3KV1808
10%
12
C710.1U0402
16V10%
12
C4070.1U0402
16V10%
12
R7749.904021%
12
C1101U0402
10V+80-20%
12
L2890Z/100M
21
34
R6149.904021%
12
L2690Z/100M
21
34
C3531U0402
6.3V+80-20%
12
F502
MINISMDC110/NA
1 2
J7
1.25MM/ST/MA-4ACES85205-0400
1234
R88 0/NA 04021 2C630.1U0402
50V+80-20%
12
R73
00603
1 2
R53 22 04021 2
R85 600Z/100M16081 2
R52 10K 04021 2
C880.1U0402
16V10%
12
R70 6.49K 04021%
1 2
R43 0/NA 04021 2
R64 2.1K/NA 06031%
1 2R44 0/NA 04021 2
C4080.1U0402
16V10%
12
R76 600Z/100M16081 2
C1111U0402
10V+80-20%
12
R65 0/NA 04021 2
R63 0/NA 04021 2
C35210P/NA0402
50V5%
12
C510.1U0402
16V10%
12
J5
RJ45-8P/RJ11-4PAMP 1470120-2
GND1GND2
A2A3
87654321
A1
A4
GND1GND2
A2A3
PJ7PJ8RX-PJ4PJ5RX+TX-TX+
A1
A4
C500.1U040250V+80-20% 1
2
JS506
SHORT-SMT4
1 2
R91 3000402
12
R37 10K 04021 2
R67 5.1K 04021 2
C6671000P
3KV1808
10%
12
U2
VT6103LPQFP48_0.5MM
4344
3
19
20212223
39
40
42
31
24
28
45464748
4
5
8
9
10
11121314
1516
3534
2726
2176
3829373330
118741253632
MDIOMDC
RXDV
INT#/PHYAD0
LED0/LINKLED1/SPD100LED2/DUPLEX
LED3/NWAYEN
XO
XI
RST
REXT
PD#
TEST
PHYAD1/RXD3PHYAD2/RXD2PHYAD3/RXD1PHYAD4/RXD0
RXC
RXER
TXER
TXC
TXEN
TXD0TXD1TXD2TXD3
COLCRS
TX+TX-
RX+RX-
GND0GND1GNDCGNDOSCGNDRXGNDTXGNDTXCGNDPLL
VDD0VDD1VDDC
VDDOSCVDDRXVDDTX
VDDPLL
AC97_SYNC 9,15,18
MONO_OUT18
MDC_SDIN 9,15AC97_RST#9,15,18
AC97_SDOUT9,15,18
AC97_BITCLK 9,15,18
LAN_DATAIO10LAN_DCLK10
LAN_MTXC10LAN_MTXD010
LAN_MTXD210LAN_MTXD110
LAN_MTXD310LAN_MTXE10
LAN_COL10LAN_CRS10
LAN_MRXC10LAN_MRXD310LAN_MRXD210LAN_MRXD110LAN_MRXD010
LAN_MRXDV10LAN_MRXER10
MII_PWRDWN 9
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB 2.0
USB 2.0
USB 2.0DOWN
UP
USB2.0 & Flash ROM
SDA0 ==> LDT Trasmit Timing control
Sec soure 297040100027 Sec soure 297040100027
Sec soure 297040100027Sec soure 297030105003
Sec soure 331000008090
Sec soure 331000008090
Sec soure 331000008090
<Doc> R00
<Title>
C
17 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
USB_OC#0
USBP0-
USB_OC#1
USBP1+
USBP1-
USBP0+
USBP3-
USBP3+USBP2+
USB_OC#3
USBP2-
USB_OC#2
USBP5-
USBP4+
USB_OC#5
USBP4-
USB_OC#4
KI3
KO0
ISA_SA14IDE_SDD13
IDE_SDD3
ISA_SOE#
ISA_SA9
ISA_SA15
IDE_SDD2
ISA_SA13ISA_SA12IDE_SDD12
IDE_SDD15
IDE_SDD9
IDE_SDD11
IDE_SDD0ISA_SA1
IDE_SDD7
ISA_SA5
ISA_SA10IDE_SDD10
ISA_SA8IDE_SDD8
ISA_SA4
IDE_SDD1
IDE_SDD5
ISA_SA7ISA_SA6
IDE_SDD[0..15]
IDE_SDD6
ISA_SA11
ISA_SA0
ISA_SA2
IDE_SDD14
IDE_SDD4ISA_SA3
ISA_MEMR#
ISA_MEMW#
ISA_SA16ISA_SA17
ISA_SA6
ISA_SA13
ISA_SA2
ISA_SA4
ISA_SA15
ISA_SA11
ISA_SA3
ISA_SA8
ISA_SA1
ISA_SA12
ISA_SA14
ISA_SA5
ISA_SA7
ISA_SA10ISA_SA9
ISA_SA0
ISA_SA7
ISA_SA2ISA_SA3
ISA_SA4ISA_SA1ISA_SA0
ISA_SA8ISA_SA12
ISA_SA14
ISA_SA11
ISA_SA9ISA_SA15 ISA_SA10
ISA_SA13
ISA_SA6ISA_SA5
ISA_MEMR#
ISA_MEMW#
USBP5+
+5VS
GND_USB
GND_USB
GND_USB
GND_USBGND_USB
+5VS
GND_USB
GNDGND
+5VS
GND_USB
GND
GND
GNDGND
GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
+5V
GND
+5V
+5V
+5V
+5V +5V +5V +5V +5V
GND
L21
90Z/100M
21
34
R392 4.7K 04021 2
F3
MINISMDC110
1 2
C3800.1U0402
16V+80-20%
12
U24
74HCT244D SO20
2468
11131517
119
181614129753
2010
1A11A21A31A42A12A22A32A4
1G2G
1Y11Y21Y31Y42Y12Y22Y32Y4
VCCGND
L97
90Z/100M
21
34
R405 0/NA 06031 2
SW506
5V/1MADT016-PT11AB-B-1
12
34
R9560K04021%
12
R149 0/NA 06031 2
R15 0/NA 06031 2
R395 4.7K 04021 2
U25
32P/PLCC/SMTPLCC32
12111098765272623254282932
2224
1
31
1314151718192021
32
16
30
A0A1A2A3A4A5A6A7A8A9
A10A11A12A13A14A15A16
CE#OE#
VPP
WE#
O0O1O2O3O4O5O6O7
VCC
VSS
A17
R4560K04021%
12
C101000P0402
50V10%
12
R404 0/NA 06031 2
L2090Z/100M
21
34
R21 0/NA 06031 2
R16 0/NA 06031 2
+ C33330U6.3V20%
12
JO50112
C41000P0402
50V10%
12
L101 600Z/100M16081 2
R18 0/NA 06031 2
C341U0402
6.3V+80-20%
12
JO52912
C3861000P0402
50V10%
12
C1010.1U0402
16V+80-20%
12
R2710K04021%
12
R19510K04021%
12
R224560K04021%
12
J3
4PX2/RATYCO1470748
GND1GND2
A1
GND3GND4
B1A2B2A3B3A4B4
GND1GND2
A1
GND3GND4
B1A2B2A3B3A4B4
R29560K04021%
12
C3851000P0402
50V10%
12
JS504
SHORT-SMT4
1 2
J4
4PX2/RATYCO1470748
GND1GND2
A1
GND3GND4
B1A2B2A3B3A4B4
GND1GND2
A1
GND3GND4
B1A2B2A3B3A4B4
C3620.1U0402
10V10%
12
JO53012
C3820.1U0402
10V10%
12
R1010K04021%
12
F4
MINISMDC110
1 2
R353560K04021%
12
R389 0 04021 2
R26560K04021%
12
R1110K04021%
12
U23
74HCT244D SO20
2468
11131517
119
181614129753
2010
1A11A21A31A42A12A22A32A4
1G2G
1Y11Y21Y31Y42Y12Y22Y32Y4
VCCGND
L2290Z/100M
21
34
R20 0/NA 06031 2
R17 0/NA 06031 2
C841U0402
6.3V+80-20%
12
C371000P0402
50V10%
12
SW502
TC010-PSS11CET297040105010SW_TC010-PS11CETT-MEC(台灣美琪)
13
245
C3830.1U0402
16V+80-20%
12
R21210K04021%
12
C3810.1U0402
10V10%
12
R2810K04021%
12
JS505
SHORT-SMT4
1 2
+ C384330U6.3V20%
12
RP71
4.7K*8 1206
12345 6
78910
R22 0/NA 06031 2
J9
4PX2/RATYCO1470748
GND1GND2
A1
GND3GND4
B1A2B2A3B3A4B4
GND1GND2
A1
GND3GND4
B1A2B2A3B3A4B4
JO53112
C391000P0402
50V10%
12
R136 0/NA 06031 2
RP64
4.7K*8 1206
12345 6
78910
R390 0/NA 04021 2
JS501
SHORT-SMT4
1 2
SW505
TC010-PSS11CET297040105010SW_TC010-PS11CETT-MEC(台灣美琪)
13
245
C361U0402
6.3V+80-20%
12
SW501
TC010-PSS11CET297040105010
SW_TC010-PS11CETT-MEC(台灣美琪)
13
245
L23
90Z/100M
21
34
R23 0/NA 06031 2
F2
MINISMDC110
1 2
L98
90Z/100M
21
34
+ C32330U6.3V20%
12
USBP0-8
USB_OC#08 USB_OC#1 8
USBP0+8
USBP1- 8
USBP1+ 8
USBP3- 8USBP2-8
USBP2+8
USB_OC#3 8
USBP3+ 8
USB_OC#28
USBP5- 8USBP4-8
USBP4+8
USB_OC#5 8
USBP5+ 8
USB_OC#48LID#19
POWERBTN#19
KI319
KI419
KO0 19
IDE_SDD[0..15]9,13
ISA_SOE#9
ISA_SD49
ISA_SD19
ISA_SD59
ISA_SD39ISA_SD29
ISA_SD79ISA_SD69
ISA_SD09
ISA_ROMCS# 9
ISA_SA189
ISA_SA17 9ISA_SA16 9
ISA_MEMR# 9
ISA_MEMW# 9
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
MiTac Secret
Confidentia
l Docum
ent
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LOW
平行走線等長
Internal Microphone
SPK_OFF / EAPD
Aud
io C
odec
Microphone Jack
CLOSE TO CODEC
HI
W=10milsas short as possible
Shutdown
HI
" High Shutdown "
Close to L78L05ACU
LOW
Close to Codec
close to MTG8
Audio CODEC(VT1617A)
Sec soure 291000010410
P/N 286101428001
Sec soure 339115000059
<Doc> R00
<Title>
C
18 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
SPKR_LOUT-
SPKR_ROUT+
MIC1
MONO_OUT
AC97_RST#
EAPD
SPKR_LOUT+
SHUTDOWN
SPKR_ROUT+
VREF_OUT
EAPD
AC97_BITCLK
VREF_OUT
AC97_SDIN
SPKR_ROUT-
CDROM_RIGHTCDROM_COMM
ACSDOUT
AOUT_L
CDROM_LEFT
AOUT_R
HP_SENSE
PCBEEP
PCBEEP
AC97_SYNCAC_ID1
AC_ID1
AOUT_L
SHUTDOWNHP_SENSE
AOUT_R
SPKR_LOUT+
SPKR_ROUT+SPKR_ROUT-
SPKR_LOUT+SPKR_LOUT-
MIC2
AC_GPI0
AC_GPI0
AC_GPI3
AC_GPI3
SB_SPKR
CARDSPK#
+AVDDAD
+5V
AGND
AGND
AGND
+AVDDAD
AGND
AGND
AGND
+3V
AGND
+5V_AMP
AGND
AGND
+VDD3
AGND_C
AGND
AGND
AGND_C
+AVDDAD
AGND
AGND
AGND
AGND_C
AGND_C
AGND
+5V
AGND
AGND_C
AGND
AGND
GND
GND
GND
GND
GND
GND GND
GND
AGND
+5V_AMP
AGND
AGND
AGND
AGND AGND
AGND
AGND
AGND
+5V_AMP
GND
AGND
GNDGND_USB
C146 1U 04021 2
C192 1U/NA 04021 2
L62 120Z/100M 16081 2
R220 100K/NA 04021 2
C233 1U04026.3V
1 2
C144 1U 04021 2
L43 600Z/100M16081 2
L38BEAD_600Z/100M
0603D1 2
C1880.1U0402
16V+80-20%
12
C401 1U 04021 2
+
C236
100U16VCPWX6.6
1 2
C1711U0402
12
R1Q13DTC144TKA
2
13
C142 1U 04021 2
R21447K04025%
12
+ C235100U16VCPWX6.6
12
R216100K04025%
12
L49BEAD_600Z/100M
0603D1 2
C2300.1U040216V+80-20%
12
C228 1U04026.3V
1 2
R403
100K 0402
5%
1 2
C1850.1U0402
16V+80-20%
12
L47 120Z/100M 16081 2
R20310K04025%
12
R192 22 04021 2
L51 600Z/100M16081 2
TP534 1
R333 22 04021 2
J13
1.25MM/ST/MA-4
ACES85205-0400
1234
R176100K04025%
12
C400 1U 04021 2
L41 120Z/100M 16081 2
L48 600Z/100M16081 2
L45 120Z/100M 16081 2
C1631U/NA0402
12
R213 1K0402
1 2
C1342200P0603
12
C210 1U04026.3V
1 2
J10
JACK-5P-R/A-W9.1ST-28M-F60331840005013CONN_JACK_ST28MF60
3
54
76
R222
100K0402
5%
12
R173 330 0402 5%1 2
C211 1U04026.3V
1 2
L52 120Z/100M
16081 2
C2130.1U0402
16V+80-20%
12
U13
G1428
23
4
56
78
910
11
14
15
16
17
18
19
20 21
22
23
1121324
2526272829
3031323334
GAIN0GAIN1
LOUT+
LLINEINLHPIN
PVDD0RIN
LOUT-LIN
BYPASS
PC-BEEP
SEBTL
ROUT-
HP/LINE
PVDD1
VDD
RHPIN ROUT+
SHUTDOWN
RLINEIN
GND0GND1GND2GND3
G1G2G3G4G5
G6G7G8G9G10
R17847K0402
5%
12
J12
JACK-5P-R/A-W9.1ST-28M-F60331840005014CONN_JACK_ST28MF60
3
54
76
C224100P0402
50V10%
12
+C227
100U16VCPWX6.6
1 2
C2081U0402
10V+80-20%
12
R191 0 0402 5%1 2
R205 0 04021 2
C1332200P0603
12
C1730.1U0402
16V+80-20%
12
+-
MIC501
D6/H2.2FM-10B1P-07
12
R22347K04025%
12
C147 1U 04021 2
C153 1U 04021 2
R202
10K04025%1
2
R185
47K/NA0402
1 2
R194 1K0402
1 2
L39BEAD_600Z/100M
0603D1 2
C2140.1U0402
16V+80-20%
12
C1820.1U0402
16V+80-20%
12
C1810.1U0402
16V+80-20%
12
R42810K/NA04025%
12
R20610K04025%
12
C187 1U 04021 2
R39310K04025%
12
C2120.1U0402
50V5%
12
C1931U0402
10V+80-20%
12
C174270P0402
50V+/-10%
12
C148
1U04026.3V+80-20%
1 2
C4190.1U040210% 1
2
C161
1U/NA04026.3V+80-20%
1 2
C1890.1U0402
16V+80-20%
12
C145 1U 04021 2
C157 1U 04021 2
C191 1U/NA 04021 2
L50 600Z/100M16081 2
L53 120Z/100M 16081 2
C135 1U 04021 2
L54 120Z/100M 1608
1 2
R172 330 0402 5%1 2
U11
AHC1G86DBVSOT25
42
35
1
C1701U0402
12
R204 0/NA 04021 2
C2311U0402
10V+80-20%
12
C1690.1U0402
16V+80-20%
12
R215 4.7K 04021 2
C2290.1U0402
16V+80-20%
12
C143 1U 04021 2
C19910U080510V+80-20%
12
L57 0 06031 2
C2321U0402
10V+80-20%
12
C223100P0402
50V10%
12
C1860.1U0402
16V+80-20%
12
R221 100K 04021 2
C234 1U040210V
1 2
U10
VT1617APQFP48_0.5MM
1
2 3
4
5
6
7
8
9
10
11
12
13
1415
1617
18
1920
2122
2324
25
26
27
28
3536
37
38
3941
42
4546
47
3133344043
2930
3244
48
DVCC1
XTAL_IN XTAL_OUT
DGND1
SDATA_OUT
BIT_CLK
DGND2
SDATA_IN
DVCC2
SYNC
RESET#
PC_BEEP
PHONE
AUX_LAUX_R
VIDEO_LVIDEO_R
CD_L
CD_GNDCD_R
MIC1MIC2
LINE_IN_LLINE_IN_R
AVCC1
AGND1
VREF
VREF_OUT
LINE_OUT_LLINE_OUT_R
MONO_OUT
AVCC2
LNL/SR_OUT_LLNL/SR_OUT_R
AGND2
ID0ID1
EAPD
NC0NC1NC2NC3
CENTER_OUT
AFLT1AFLT2
CAP2LFE_OUT
SPDIF_OUT
R219 100K 04021 2
C141 1U 04021 2
C201270P040250V
12
C1900.1U0402
16V+80-20%
12
R201 4.7K/NA 04021 2
R200 1K 04025%1 2
R177100K04025%
12
C1801000P0402
50V10%
12
R2181K04021%
12
R2171K04021%
12
R1892.2K/NA04025%
1 2
L40BEAD_600Z/100M
0603D1 2
L55 120Z/100M 16081 2
C172270P0402
50V+/-10%
12
C162270P040250V
12
L56 120Z/100M 1608
1 2
MINIPCI_SPKR# 15
CDROM_COMM13
AC97_RST#9,15,16
MONO_OUT 16
AC97_SYNC9,15,16
CDROM_RIGHT13CDROM_LEFT13
AC97_SDIN9
CARDSPK# 14
SB_SPKR 10
AC97_SDOUT9,15,16
AC97_BITCLK9,15,16
AUDIO_14M5
SB_GPO0 9
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MiTac Secret
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FAN OFF
Signal
FAN ON
HI
Close to AO3403
FAN ON
Signal
FAN
30milFA
N
LOW
KBC (W83L950D)
Close to AO3403
LOW
DOWN
CPU_FAN Control
FAN0
CPU_FAN Control
HI
FAN OFFFAN0
Come From Battery
Sec soure 291000152610
Sec soure 291000010209
Sec soure 291000010209<Doc> R00
<Title>
C
19 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
SERIRQ
KBC_CPUCORE
KBC_RSMRST
XIN
BATTRY_TYPE
KBC_SCIKBC_SUSB
KBC_PWR_ON
KBC_LRST#
KBC_WAKE_UP#
POWERBTN#
T_DATA
T_CLK
FAN0
FAN0
KBC_RESET#
FAN1
LID#
LAD0
KBC_SB_PWRBTN
LAD1
BAT_DATA
LFRAME#
FAN1
XOUT
BAT_CLK
KBC_ADEN#
LAD3
BATT_DEAD#
LAD2
BAT_TEMP BAT_T
BAT_DBAT_C
BAT_VOLT BAT_V
BAT_CLKBAT_DATA
SW_VDD3
KBC_SUSB
BAT_DATA
BAT_CLK
BAT_CLKBAT_DATA
T_CLKT_DATA
KBC_WAKE_UP#KBC_SB_PWRBTN
KBC_EXTSMI#
KI7
KO10
KO1
KI1KI2
KO5
KO0
KI4
KO8
KO6
KO14
KI3
KO13
KI5
KI0
KO9
KO4
KO12
KO7
KO15
KI6
KO11
KO3KO2
KI5
KO0
KI7
KO6
KO8
KO11
KI6
KO5
KO2
KI1
KO9
KI3
KO7
KO12
KO14
KI0
KO10
KO4
KO1
KI2
KO15
KI4
KO3
KO13LID#
KBC_PWR_ON
KBC_RSMRST
KBC_SB_PWRBTN
KBC_SCI
SCI#
KBC_WAKE_UP#
KBC_EXTSMI#
KBC_+3VS
LAD[0..3]
LAD1LAD0
LAD3LAD2
KI4
BATT_DEAD#
KI2KI3 KI6
POWERBTN#
KI1KI0
KBC_ADEN#
KI5
KI7
KBC_EXTSMI#
BAT_CLK
KBC_RSMRST
KBC_+3VS
KBC_CPUCORE
BATT_DEAD#
+SVDD3
+KBC_VDDA
+5V
+KBC_VDDA
+SVDD3
+5V
GND
GND
GND
+SVDD3
+3V
+3V
GND
GND
GND
GND
+5V +SVDD3
+VDD3
GND
GND
GND
GND
GND
GND
+3VS
+VDD3
+3VS
+VDD3
+VDD3
GNDGND GND
+KBC_VREF
+VDD3
+VDD3
+SVDD3
+SVDD3
GND
GND
+3VS
+VCC_CORE
JO516 12
R123470K04025%
12
JO517 12
C2071U0402
6.3V+80-20%
12
C3040.1U040216V+80-20%
12
JO502 12
C3070.1U0402
50V+80-20%
12
D S
Q192N7002G
D S
JO504 12
C3020.1U0402
16V+80-20%
12
DS
Q212N7002G
DS
JO520 12
X4
8MHZ
1 2
C3180.1U0402
50V+80-20%
12
RP45
10K*41206
1234
8765
C32922P0402+/-10%
12
DS G
Q11AO3403SOT23_FET
G
DS
R29510K04025%
12
R1Q25
DTC144TKA
2
13
D S
Q182N7002G
D S
R285 10K 04021 2
C3010.1U0402
16V+80-20%
12
C860.1U0402
16V+80-20%
12
JO524 12
C32110P0402
50V+/-10%
12
R1
Q22
DTC144TKA
2
13
JO518 12
R43200402
12
JO507 12JO508 12
R270 10K/NA 04021 2
R2860/NA0402
12
J501
FPC/FFC/1MM/26PACES85202-26-05
1234567891011121314151617181920212223242526
R1
Q17DTC144TKA
2
1 3
JO505 12
J11
1.25MM/ST/MA-2ACES85205-0200
12
JO525 12
C261U0402
6.3V+80-20%
12
JO503 12
R293 10K 04021 2
JO511 12
JO523 12
R28920K04021%
12
JO512 12
R288 1K 04021 2
R274 22 04021 2
JO510 12
C3030.1U040216V+80-20%
12
R273 10K 04021 2
R2921M
0402 5%1 2
R1
Q27DTC144TKA
2
1 3
DS G
Q9AO3403SOT23_FET
G
DS
R275 22 04021 2
JO519 12
L60 120Z/100M 16081 2
R27710K04025%
12
R1
Q23
DTC144TKA
2
13
RP53
10K*81206
12345 6
78910
JO515 12
R211470K04025%
12
D14
BAV70LT1
1 23
R1Q24
DTC144TKA/NA
2
13
RP47
10K*81206
12345 6
78910
JO506 12
JO513 12
U16
W83L950D
PQFP80_0.5MM
3132333435363738
1
20
7069686766656463
171514232219
21
1618
987654
55
1110
80797877767574
32
2726
1312
54535251504948474645444342414039
62616059585756
24
25
28
29
30
71
72
73
GP27/FD7GP26/FD6GP25/FD5GP24/FD4
GP23/FD3/SCL1/TXD1GP22/FD2/SDA1/RXD1
GP21/FD1GP20/FD0/LPCEN
GP60/AN0/INT5
GP45/TXD
GP80/SD0GP81/SD1GP82/SD2GP83/SD3GP84/SD4GP85/SD5GP86/SD6GP87/SD7
GP50/A0GP52/INT30#/RGP53/INT40#/WGP42/INT0/OBF00GP43/INT1/OBF01GP46/SCLK1/OBF1
GP44/RXD
GP51/INT20#/S0GP47/SRDY1#/S1
GP70/SIN2P71/SOUT2
GP72/SCLK2GP73/SRDY2#/INT21
GP74/INT31GP75/INT41
GP37/OE#
GP56/DA1/PWM01GP57/DA2/PWM11
GP61/AN1/INT6GP62/AN2/INT7GP63/AN3/INT8GP64/AN4/INT9
GP65/AN5/INT10GP66/AN6/INT11GP67/AN7/INT12
GP76/SDAGP77/SCL
GP40/XOUT/PWM2GP41/XCIN/PWM3
GP54/CNTR0GP55/CNTR1
GP0/P3REF/FA0GP1/FA1GP2/FA2GP3/FA3GP4/FA4GP5/FA5GP6/FA6GP7/FA7GP10/FA8GP11/FA9GP12/FA10GP13/FA11GP14/FA12GP15/FA13GP16/FA14GP17/FA15
GP30/PWM0/FCTRL0GP31/PWM10/FCTRL1GP32/FCTRL2GP33/FCTRL3#GP34/BANK0GP35/BANK1GP36/CE#
CNVSS
RESET#
XIN
XOUT
VSS
VCC
VREF
AVSS
R29110K04025%
12
DS
Q20
FDV301NSOT23_FET
G
DS
JO521 12
C32822P0402+/-10%
12
R28010K0402
12
C2000.1U0402
16V+80-20%
12
JO514 12
RP44 33*41206
1234
8765
C3060.1U0402
50V+80-20%
12
JO522 12
JO509 12
R271 10K/NA 04021 2
J6
1.25MM/ST/MA-2ACES85205-0200
12
Q26
DTC144WK
1
2
3
I_CTRL 24
T_DATA 13
BATT_SELL24
CLK_KBC5
SUSC# 9,21
SERIRQ10,14,15LID# 17
I_LIMIT 23
SB_THRM# 10
T_CLK 13
ADEN#20,23
LFRAME#10,15
LEARNING23
BLADJ 12
LPC_RST#7,8,11
BAT_C 23BAT_D 23
SW_+SVDD320
BATT_DEAD_P 24
SUSB# 9,20,22
KBD_CS0 8
THRM_DATA 5
PWR_ON_3VS_5VS 26
CAP# 13NUM# 13SCROLL# 13
KBRC# 8A20G 8
RSMRST# 9
SB_PWRBTN# 9
SCI#9
WAKE_UP# 9
EXTSMI# 9
BATT_G# 13BATT_R# 13
POWERBTN# 17
BAT_T 23BAT_V 23
CHARGING 24
KBC_RESET# 20
KBC_PWRON_+VDD3 20
LAD[0..3]10,15
BATT_POWER# 13
KBC_SUSB20
KI317KI417
KO017
AC_POWER#13
THRM_CLK 5
I_CHG 23
I_DISCHG 23
ENBL_KBC12
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
For Lan
POWER ON PERPHERIAL CIRCUIT
KBC RESET#
<Doc> R00
<Title>
C
20 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
PWRIN1
SUSB#
SW_+SVDD3
SUSB#
H8_RESET#
THERM_ALERM#
SUSB#
PWRIN1
PWR_VDDIN+SVDD3
GND
+5V
GND
GND
+5VS
+3VS
GND
GND
GND
GND
GNDGND
+3VS
GND
+3V
+2.5VS +5VS
GND
GND GND
GND
+VDD3+SVDD3
+3V_P+2.5V_P +3VS
+5V_P+1.25VTT
+1.2V_P+1.2VLDTA
+2.5VS_DDR
+1.25V_DDR_P +5VS
+1.5V_P+1.5V
GND
GND
+2.5VS_DDR
+2.5V
PWR_VDDIN
GND
GND
+3V
+SVDD3
GND
+2.5V
GND
GND
+2.5V
+3V
GND
+3V
+2.5V
GND
GNDGNDGND GND
GNDGND
+KBC_VREF
+KBC_VREF
U22C
74HCT08_VTSSOP14
9
108
147
F5
FUSE_1206
1A-12063216FF-1
1 2
C346
10U6.3V080510%
12
U22D
74HCT08_VTSSOP14
12
1311
147
R41010K04025%
12
U29
AME8800AEEV/NASOT25
123 4
5GND0VINVOUT NC1
NC0
C4214.7U0805+80-20%
12
C3371U0402
10V+80-20%
12
JO5
OPEN-SMT4
1 2
DS
Q282N7002
G
DSC390
0.1U0402
50V+80-20%
12
C2822.2U0603+/-10%
12
C33310U080510V+80-20%
12
R3130
04025%
1 2
R1
Q40
DTC144TKA288202240001
2
13
JO11
OPEN-SMT4
1 2
JO8
OPEN-SMT4
1 2
U17
AME8800DEFTSOT89N1
23
GN
D
VINVOUT
R1Q16
DTC144TKA288202240001
2
13
C3880.1U0402
50V+80-20%
12
C3891U0402
10V+80-20%
12
JO3
OPEN-SMT4
1 2
JO527
OPEN-SMT4
1 2
JO526
OPEN-SMT4
1 2
C3514.7U0805+80-20%
12
R4081K04025%
12
DSG
Q36AO3413
G
DS
C269
4.7U0805+80-20%
12
C3871U0402
10V+80-20%
12
R1
Q30
DTC144TKA288202240001
2
13
R134 0 04021 2
JO1
OPEN-SMT4
1 2
R4310/NA0805
12
R263100K04025%
12
R409100K04025%
12
GD S
U18AO4422SO8
876
4
5 1
32
R406
100K04025%
1 2
C319
4.7U0805+80-20%
12
JO4
OPEN-SMT4
1 2
C4202.2U/NA0805+80-20%
12
C3430.1U0402
50V+80-20%
12
DS
Q412N7002
G
DS
JO10
OPEN-SMT4
1 2
R2660
04025%
1 2
C34010U
6.3V0805
10%
12
C311
1U0603
12
U19
AMS3107SOT223286303107001
1
2
3INPUT
GN
D
OUTPUT
C4251U0603
12
JO9
OPEN-SMT4
1 2
C3450.1U0402
50V+80-20%
12
R294
100K04025%
1 2
U38
IMP811SOT143
1
2
4
3
GND
RESET
VCC
MN
JO528
OPEN-SMT4
1 2
R43500805
12 DS
G
Q15
AO3413
G
DS
C3440.1U
50V0603
12
JO2
OPEN-SMT4
1 2
C310
4.7U0805+80-20%
12
GDS
U21AO4403SO8
876
4
51
32
R298
100K0603
1 2D S
G
Q12
AO3413
G
D S
C33510U6.3V080510%
12
C35910U
10V0805C
12
U28
LP2951-02BM/NASO8
8273
6154
INSENSEF/BSHUTDN
5VTAPOUT
ERR-GND
C3390.1U
25V0603
+80-20%
12
R4071K04025%
12
R321100K04025%
12
SW1
TC010-PSS11CET297040105010SW_TC010-PS11CETT-MEC(台灣美琪)
13
245
JO6
OPEN-SMT4
1 2
JO7
OPEN-SMT4
1 2
U8D
74HCT08_VTSSOP14
12
1311
147
JO12
OPEN-SMT4
1 2
R2961K04025%
12
DS
Q29
2N7002
G
DS
Q31
DTC144WK288202237002
1
2
3
C3362.2U0603
12
GDS
U35AO4403SO8
876
4
51
32
D12
BAS32L
A K
R355 0 04021 2
SW_+SVDD319
KBC_RESET# 19
THERN_ALERM# 5
KBC_SUSB 19
KBC_PWRON_+VDD3 19
CPU_CORE_EN_P 25
PWROK_SB 3,7,9
ADEN# 19,23
+1.2VPG22
SUSB#9,19,22
ALL_PWROK_2.5V 3,7,9
CPU_PWROK_2.5V 2
+2.5VDDA_PG3
CPU_THERMTRIP# 2
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MiTac Secret
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.25V
+2.5V_P
DVT:1. ADD PC77 150U/6.3V2. PL8 take off placement
<Doc> R00
<Title>
C
21 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
SUSC#
+2.5V_P
GND
+1.25V_DDR_P
+2.5V_P
GNDGND
+1.25V_DDR_P
GND
SGND7
GND
GND
SGND7
+2.5V_P
GND
GND
GND
SGND7
GND+5V_P
DVMAIN
GND
+ PC82820U4V
12
PC6810U
16V1206
12
PC880.01U0402
50V+80-20%
12
GD
S
PU10
AO4410SO8288204410010
876
4
52 31
PC70
10U16V1206
12
JS3
SHORT-SMT4
1 2
+ PC9622U25V20%
12
PR580
06031 2
PJL1
JP_NET20
1 2
PC7410U
16V1206
12
PR46100603
1 2
+ PC81820U/NA4V
12
PL11
120Z/100M2012
1 2
PR521K06031%
12
PR518.2K06031%
1 2
PR491M0603
12
PC730.1U/NA
50V0603
12
PR482.20603
12
PC670.1U
50V0603
12
+ PC9522U/NA25V20%
12
PC790.01U
50V0603
10%
12
PU11
SC1470TSSOP14
34
876
2
5
1
91011121314
VOUTVCCA
PGNDAGNDPGOOD
VIN
FB
EN/PSV
DLVDDP
ILIMLXDH
BST
PC710.1U0402
50V+80-20%
12
PC9722U
10V1210
12
PC751000P060310%,X7R
12
PR504.02K06031%
1 2
PL12
120Z/100M2012
1 2
JS2
SHORT-SMT1
1 2
PL7
2.2UHIHLP5050CE-0120%
1 2
PR5300603
1 2
PC890.1U
50V0603
12
PC830.1U
50V0603
12
PU13
G2996SO8_GND_4
1
2
3
4
8
7
6
5
910111213
GND
SD
VSENSE
VREF
VTT
PVIN
AVIN
VDDQ
GND1GND2GND3GND4GND5
PC861000P
25V0603
10%
12
PC800.1U080510%
12
PC720.1U
50V0603
12
PR47
00603
1 2
PC870.01U0402
50V10%
12
GD
S
PU12
AO4422
SO8
876
4
51 32
+ PC77150U72436.3V
12
PJL2
JP_NET20
12
PD10
SSA34/NADC2010
AK
PC7810U
16V1206
12
PD11
SS14DC2010
AK
PR540
0603
1 2
SUSC#9,19
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MiTac Secret
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DVT:1. ADD PC7.PC9 150U/6.3V2. ADD PC5 10U/25V change from 272023106701 to 2720231065023. PR8 change from 10Kto 9.09 for H/W +1.57V
<Doc> R00
<Title>
C
22 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
+1.5V_P
GND
GND
+2.5VS_DDR
GND
+1.2V_P
GND
GND
GND
+5V_P
GND
GND
+VDD3
GND
+3V
PR10
00603
1 2
PC160.1U
50V0603
12
PC120.1U/NA
50V0603
12
PC510U
25V1210
20%
12
PC1010U
16V1206
12
PR1610K06031%
12
+ PC7150U72436.3V
12
PU3
SC338PSOP10_0.5MM
12345 6
78
109DRV1
ADJ1EN1PGD1GND PGD2
EN2ADJ2
INDRV2
PR1514K06031%
12
PR12
00603
1 2
PC1310U
16V1206
12
PC150.1U
50V0603
12
PR700603
1 2
PR1447K/NA0603
12
PC610U
16V1206
12
PR1147K0603
12
PC80.1U/NA
50V0603
12
PL2
120Z/100M2012
1 2
PC140.1U
50V0603
12
PC310U
16V1206
12
PC40.1U
50V0603
12
GDS
PU4
AO4422SO8
876
4
51
32
PR920K06031%
12
PR13
00603
12
PC1110U
25V1210
20%
12
PR89.09K06031%
12
+ PC9150U72436.3V
12
GD S
PU2AO4422
SO8
876
4
5 1
32
SUSB#9,19,20
PG_VCC_CORE_P 25
+1.2VPG 20
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ADPIN & Dischrage
DVT:1. PU20--> VDD3 change to SVDD2. ADD PR108 , PR1093. ADD PR85PVT:1. PJO6.PJO7 take off2. PJO1.PJO2 take off
Sec soure 331000007044
Sec soure 331000007044
<Doc> R00
<Title>
C
23 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
B2 BATT1
LEARNING
A4A1 A2 A3
BATT1
GND
GND
GNDB
GND
+SVDD3
GND
GND
GNDB
GND
GND
GND
GND
GND
PWR_VDDIN
GND
GNDGND
GND
GND
DVMAIN
GND
GND
GND
GND
+SVDD3
GND
GND
PF3
TR/SFT-10AFUSE_2917
1 2
PC1231000P
25V0603
10%
12
PC21000P0603
12
PR7633K0603
12
PR82226K06031%
12
PC1290.1U
50V0603
12
GD
S
PQ15AO4407SO8
876
4
51 32
PC1471U
10V0805
12
PC1501000P0603
12
PJO8
SPARKGAP_6
12
PR75
100K0603
1 2
PR3100K0603
12
PD6
BAV70LT1
1
23
PR21M0603
12
PU20
MAX4377MSOP8
1234 5
678OUT1
RS1-RS1+GND RS2+
RS2-OUT2VCC
PJP1
SPARKGAP_6
12
GDS
PU1AO4407SO8
876
4
51
32
PR87499K06031%
12
PC11000P0603
12
PR108100603
1 2
PJO501
OPEN-SMT4
12
DS
PQ142N7002G
DS
PR86100K06030.1%
12
PC1250.1U
50V0603
12
PR31100603
12
PC1451U
10V0805
12
PL5120Z/100M2012
12
PC1520.01U
50V0603
10%
12
DS
PQ12N7002G
DS
PJ1
JACK-2P
2DC-S107B200
331910002006
2
1
3 4
PR109100603
1 2
PD2BZV55C24VMLL34B
AK
PL17120Z/100M2012
12
PC1511000P0603
12
PC1300.1U
50V0603
12
PC1190.01U
50V0603
10%
12
PD3
SBM1040
1
23
PC1460.1U
50V0603
12
PR1
.0125121%
1 2
PU9
MAX4073FEUT-TSOT26
162
354
GND0OUTGND1
VCCRS-RS+
PD1RLZ24D_NAMLL34B
AK PR6
4.7K0805
12
PR94 0 06031 2
PQ17DTC144WKSOT23AN_1
1
2
3
PC1260.1U
50V0603
12
PJO3SPARKGAP_6
12
PR54.7K0805
12
PD4
SM840B/NADC2012
A K
PC390.1U
50V0603
12
PC1240.01U50V10%0603D
12
PR4470K0603
12
PJ2
MA/2.5MM/7PTBTD-0070018_7
1234567
1234567
PC1480.01U
50V0603
10%
12
PJO4SPARKGAP_6
12
PD5
BAV70LT1
1
23
PC380.1U
50V0603
12
PC410.1U
50V0603
12
PR9120K06031%
12
PL1120Z/100M2012
12
GD
S
PQ18AO4407/NASO8
876
4
51 32
PR884.99K06031%
12
PR92 0 06031 2
PC441U
10V0805
12
PR97 0 06031 2
PF1
6.5A/32VDC
1 2
PC1180.1U
50V0603
12
PL16120Z/100M2012
12
PC1490.1U
50V0603
12
PR85.0125121%
1 2
PC401000P
0603
12
BAT_C 19
BAT_D 19
BAT_T 19
BAT_V 19
ADINP 24
LEARNING19
I_LIMIT 19
ADEN# 19,20
I_DISCHG19
I_CHG19
BATT24
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
=8.56V
BATT_SELL:HI 11.1V;LOW 8.556V
CHARGING
BATT_SELL:HI 16.8V;LOW 12.65V
DVT:1. PC143 change from 1000P to 0.1U/50V2. PR101 change from 1% to 0.1%PVT:1. PR104 change from 24.3K to 23.7K (271071237211) for 8 cellcharging voltage 16.9V
<Doc> R00
<Title>
C
24 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
BATT_SELL
1.25V_REF
L2
REF
2IN+
CHARGINGCHARGING
2IN+
L3 L4
GNDGND
D/VMAIN
GND
GND
+SVDD3
GND
+SVDD3
GND
GND
GND GNDB
GND
GNDGND
PC1200.1U/NA
50V0603
12
PJO9
OPEN-SMT4
12
PR1064.7K0603
12
PR107
.0225121%
1 2
DS
PQ252N7002G
DS
PC1340.01U
50V0603
10%
12
PQ21MMBT2222A
B
EC
PD16
BAS32LMLL34B
AK
PC133
0.1U50V0603
1 2
GDS
PQ23AO4407SO8
876
4
51
32
PR992.49K06031%
12
PD15
BZV55C20/NA
AK
PR100249K06031%
12
PR77590K/NA06031%
12
DS
PQ20
2N7002
G
DS
PC1400.1U
50V0603
12
DS
PQ222N7002G
DS
PR833.3K/NA0603
12
PL19
BEAD_120Z/100M0805D
1 2
PC1321000P060310%
12
PR78100K/NA06031%
12
PL20
33UHSPC-1204P20%
1 2
PC141 0.01U50V0603
10%1 2
PC13110U
25V1210
20%/X5R
12
PC1440.1U
50V0603
12
PR98124K06031%
12
DS
PQ162N7002/NAG
DS
PR1054.7K0603
12
PC1210.1U/NA
50V0603
12
PR10423.7K06031%
12
+
-PU18ALMV393M/NASSOP8
3
21
84
PQ19
SCK431LCSK-.5/NASOT23N3
2
1
PR93100K0603
12
PR8400603
1 2
PL18
3.0UHSPC-0670330%
1 2
PQ24DTA144WKSOT23AN_1
12
3
PC1351U
16V0805
12
PF2
TR/3216FF-3A
1 2
PC13710U
25V1210
20%/X5R
12
PJO5
OPEN-SMT4
12
PR894.70603
1 2
PC1220.1U/NA
50V0603
12
PC1391000P0603
12
PR9010K0603D1%
12
PU19
TL594CSO16
123456789
10111213141516 1IN+
1IN-FEEDBACK
DTCCTRT
GNDC1E1
E2C2VCCOUTPUTCTRLREF2IN-2IN+
PR10113.7K06030.1%
12
PR810/NA0603
1 2
PC14210U
25V1210
20%/X5R
12
PJS501
SHORT-SMT3
12
PJO502
OPEN-SMT4
1 2
PD14
SSA34DC2010
A K
+
-PU18BLMV393M/NASSOP8
5
67
84
PR9510K0603D1%
12
PD17
SSA34DC2010
AK
PC138
0.1U16V060310%
1 2
PC1271000P060310%
12
PR79287K/NA06031%
12
PC1360.01U
50V0603
10%
12
PC128
0.01U50V060310%
1 2
PR10220K06030.1%
12
PD13
BZV55C15V/NA
AK
PC1430.1U0603+80-20%
12
PR966.19K
06031%
1 2
PR103100K0603
12
PR80100K/NA0603
12
BATT_DEAD_P 19
ADINP23
I_CTRL19
BATT_SELL 19
BATT 23
CHARGING19
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_CORE
CLOSE TO CPU
DVT:1. PL3.PL4.PL6 change to 273000990127 2. ADD PR44.PR42 , PR43.PR45 N/A3. PR30.PR33.PR35 change from 2K to 3K , for one low-side mos O.C.P4.PQ3.PQ6 /NA5.ADD input cap PC76.PC69.PC30.PC55.PC49.PC24.PC51.PC43 6.ADD output cap PC64.PC60.PC357.PC24.PC30.PC43.PC49.PC51.PC55 change from 272023106701 to272023106502PVT:1. PC69.PC76.PC60 N/A <Doc> R00
<Title>
C
25 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
ENBALE
IN-
P_VID2
P_VID1
P_VID3
D/VMAIN_P3
IN+
P_VID0
D/VMAIN_P3
P_VID4
P4_3
PG_VCC_CORE_P
IN-
P_VID2
P_VID3
ENBALE
D/VMAIN_P3
P_VID0P_VID1
IN+
P_VID4
P4_2
+3V_P
GND
+5V_P
GND
+VCC_CORE
GND
GND
GND
GND
GND
GND
GND
D/VMAIN_P3
+VCC_CORE
GND
GND
+VCC_CORE
GND
+VCC_CORE
GND
GND
GND
GND
GND
GND
+5V_P
DVMAIN
GND
PR260
06031 2
PR270
06031 2
PC470.1U
16V0603
12
PD9
SSA34/NADC2010
AK
PC5110U
25V1210
12
PC660.1U
16V0603
12
PR28100805
12
PC4910U
25V1210
12
PC181000P060310%
12
PR2500603
1 2
PQ8AOB420/NAG
DS
PR230
06031 2
+PC7615U/NA
25V7243
20%
12
PC5510U
25V1210
12
PR240
06031 2
PR450/NA0603
12
PC310.1U
16V0603
12
+ PC58820U2.5V
12
PR3810/NA0805
12
+ PC29820U2.5V
12
PC211000P0603
12
PQ9AOB416/NAG
DS
+ PC53820U2.5V
12
PC3010U
25V1210
12
PC650.1U
16V0603
12
PQ3AOB416/NAG
DS
PC4310U
25V1210
12
+PC6915U/NA
25V7243
20%
12
PD7
SSA34DC2010
AK
PL10
BEAD_120Z/100M0805D
1 2
+ PC25820U2.5V
12
PC361000P0603
12
PC461000P060310%
12
PR41
00603
12
+ PC2722U25V20%
12
PQ7AOB420G
DS
PC260.1U/NA
50V0603
12
PC171000P060310%
12
PC610.1U/NA
16V0603
12
PC841000P0603
12
PC571000P/NA0603
12
PC220.1U
16V0603
12
PL3
0.68UHIHLP5050CE-0120%
1 2
PR4400603
1 2
PR4200603
1 2
PQ5AOB416G
DS
PR430/NA0603
12
PR21107K06031%
12
PR390/NA
06031 2
+ PC5222U25V20%
12
PC200.1U
16V0603
12
PL4
0.68UHIHLP5050CE-0120%
1 2
PQ4AOB420G
DS
+ PC35220U73432V
12
PL9
BEAD_120Z/100M0805D
1 2
PC42
330P/NA060310%
1 2
PQ2AOB416G
DS
PR2210K0603
12
PC32 56P0603 50V1 2
PR36
0/NA0603
1 2
PQ6AOB416/NAG
DS
PR293.48K0603
12
PC280.1U
16V0603
12
PC231U
16V0805
12
PU6
ISL6559SOL28
76543
14
9
1
13
11
17
18
21
19
22
23
28
26
27
10
25
12
8
20
16
15
2
24
VID0VID1VID2VID3VID4
RGND
COMP
GND_0
VSEN
IOUT
PWM3
ISEN3
PWM2
ISEN2
PWM1
ISEN1
EN
PGOOD
FS/DIS
FB
PWM4
VDIFF
OFS
GND_2
VCC
GND_1
OVP
ISEN4
PU5
ISL6207SO8
1
2
3
4 5
6
7
8
UGATE
BOOT
PWM
GND LGATE
VCC
EN
PHASE
PU7
ISL6207SO8
1
2
3
4 5
6
7
8
UGATE
BOOT
PWM
GND LGATE
VCC
EN
PHASE
PR34
100603
1 2
PU8
ISL6207/NASO8
1
2
3
4 5
6
7
8
UGATE
BOOT
PWM
GND LGATE
VCC
EN
PHASE
PC331U
16V0805
12
+ PC50820U/NA2.5V
12
PR40
10/NA0603
1 2 PL6
0.68UH/NAIHLP5050CE-0120%
1 2
PC631U/NA
16V0805
12
+ PC60220U/NA73432V
12
PR32
4.99K06031%
1 2PC37
4700P0603
1 2
PR190
0603
1 2
PR37
1K06031%
1 2
PR30
3K0603
1 2
PR33
3K0603
1 2
+ PC5422U25V20%
12
PR35
3K/NA0603
1 2
PC62
0.1U/NA080510%
1 2
PR18
100603
1 2
PR200
06031 2
PC560.1U
50V0603
12
PC850.01U0603
12
PC2410U
25V1210
12
PR17100805
12
PC4810U
16V1206
12
PC19
0.1U080510%
1 2
PC590.1U/NA
16V0603
12
PC34
0.1U080510%
1 2
PC45
33P/NA060325V
12
+ PC64220U73432V
12
PD8
SSA34DC2010
AK
COREFB_L 2
COREFB_H 2
PG_VCC_CORE_P22
CPU_CORE_EN_P20
VID43
VID33
VID23
VID13
VID03
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+5V_P/+3.3V_P
DVT:1. PR74 change from 0.008 to 0.0122. PL13.PL15 change to 273000990018 for height3. PC90 change from 1000P to 4700P for H/W sequencePVT:1. +VDD3 change to +SVDD32. PC106 change from 1000P to8200P ( 272075822401 )3. PC90 change from 4700P to 0.01U ( 272075103403 )
<Doc> R00
<Title>
C
26 26星期四, 五月 20, 2004
Title
Size DocumentNumber
Rev
Date: Sheet of
SW1
INTVCC2
INTVCC2
PWR_ON_3VS_5VS
SW1
GND
GND
DVMAIN
SGND3
GND
GND
+3V_P
+SVDD3
+5V_P
GND
SGND3
+SVDD3
+5V_P
SGND3
GND
GND
GND
SGND3
GND
GND
PD12
BAW56SOT23N
2 13
PU14LTC3728LHVQFN32_1
1 2 3 4 5 6 7 8
910111213141516
1718
3231302928272625
24 23 22 21 20 19
3334353637 V
OS
EN
SE
1P
LLFL
TRP
LLIN
FCB
ITH
1S
GN
D3.
3VO
UT
ITH
2
VOSENSE2NC0
SENSE2-SENSE2+RUN/SS2
TG2SW2NC1
BO
OS
T2B
G2
NC3SENSE1-SENSE1+NC2RUN/SS1PGOODTG1SW1
BO
OS
T1 VIN
BG
1E
XTV
CC
INTV
CC
PG
ND
SGND1SGND2SGND3SGND4SGND5
PR74
0.01225121%
1 2
PR6820K06031%
12
GD
S
PU16SI4832DYSO8
876
4
52 31
PC990.1U
50V0603
12
+ PC114680U6.3V20%
12
+ PC11222U25V20%
12
PR55
00603
1 2
JS4
SHORT-SMT1
1 2
PR652.20603
1 2
PC105
1000P060310%,X7R
1 2
PR72100K0603
12
PR6120K06031%
12
PR62
10K06031%
1 2
PC92
1000P060310%,X7R
1 2
PC1091000P060310%,X7R
12
PC10047P060310%
12
PC1070.1U
50V0603
12
PC98180P06035%
12
PC103
10U16V1206
12
PR561M0603
12
PR69
107K06031%
1 2
PR64
00603
1 2
PR710
06031 2
PC1170.01U
50V0603
10%
12
PR602K0603
12
PC1068200P060310%,X7R
12
PC1110.1U080510%
12
PC1130.1U
50V0603
12
PL14
120Z/100M2012
1 2
PR67200K06031%
12
PR59
63.4K06031%
1 2
PC1081000P060320%
12
PR702.20603
1 2
DS
PQ122N7002G
DS
GD
S
PU17AO4422SO8
876
4
51 32
D2
G2
G1S1A
D1
PU15
AO4912SO8
1
8567
34
2
PC9110U
16V1206
12
PC11010U
16V1206
12
PC104180P06035%
12
DS
PQ112N7002G
DS
PC1020.01U
50V0603
10%
12
PC1160.01U
50V0603
10%
12
PR66200K06031%
12
+ PC94820U4V
12
R3031M0603
12
JS5
SHORT-SMT4
1 2
PC900.01U0603
12
PC930.1U080510%
12
DS
PQ102N7002G
DS
PR63
0/NA0603
12
DS
PQ132N7002G
DS
+ PC11522U25V20%
12
PL1310UHSPC-1205P20%
1 2
PL1510UHSPC-1205P20%
1 2
PR57100K0603
12
PC10147P
060310%
12
PR73
.01220101%
1 2
PWR_ON_3VS_5VS19
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REFERENCE MATERIAL
AMD Athlon 64 CLAWHAMMER Processor AMD, INC.
“VIA K8N800 North Bridge” VIA, INC.
“VIA VT8235 South Bridge”
WINBOND, LTD.
VIA, INC.
H8/W83L950D
System Explode View
8399 Hardware Specification Technology Corp / MiTAC
Technology Corp / MiTAC
SERVICE MANUAL FOR 8399SERVICE MANUAL FOR SERVICE MANUAL FOR 8399
Sponsoring Editor : Jesse Jan
Author : Grass Ren
Assistant Editor : Ping Xie
Publisher : MiTAC International Corp.
Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5779250 Fax : 886-3-5781245
First Edition : Aug.2004
E-mail : Willy.Chen @ mic.com.tw
Web : http: //www.mitac.com http: //www.mitacservice.com
Sponsoring Editor : Jesse Jan
Author : Grass Ren
Assistant Editor : Ping Xie
Publisher : MiTAC International Corp.
Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5779250 Fax : 886-3-5781245
First Edition : Aug.2004
E-mail : Willy.Chen @ mic.com.tw
Web : http: //www.mitac.com http: //www.mitacservice.com
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