Setting up an Interrupt...A hardware interrupt is an electronic signal that alerts the...

Embedded Systems Lab 2 - HS 201914.10.2019Andreas Biri, Zhongnan Qu

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 1

Goals

Configuration of hardware interrupts

Learn how to debug program running on a microprocessor

Configuration of hardware timers

Implementation of pulse-width modulation (PWM)

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 2

Hardware Interrupt

Definition

A hardware interrupt is an electronic signal that alerts the micro-processor of an event. An interrupt can be triggered by either aninternal peripheral (e.g. timer) or an external device (e.g. button).

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 3

Polling vs. Interrupts

Polling

check button

event

ACTIVE

IDLEreact

active Polling

Interrupts

ACTIVE

IDLE

event

react

wake up

activesleep

Interrupt

PCM_gotoLPM3()

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 4

Setting up an Interrupt

CPUTIMER_A

GPIO Port 1

…

0

10

0

P1IE

Pin 0

Pin 1

Pin 2

Pin 3... ......

P1IFG

Interrupt Enable (IE)

GPIO_enableInterrupt(port,pin);GPIO_disableInterrupt(port,pin);Interrupt_enableInterrupt(interrupt);

enables individual interruptsGlobal Interrupt Enable (GIE)

Interrupt_enableMaster();enables ALL maskeable interrupts

Interrupt Flag Reg (IFR)

GPIO_getInterruptStatus();GPIO_clearInterruptFlag();

bit set when interrupt occursInterrupt Flag Reg (IFR)

GPIO_getInterruptStatus(port,pin);GPIO_clearInterruptFlag(port,pins);

Interrupt enablefor interrupt source

Global interruptenable

Interrupt enablefor GPIO pins

Interrupt flag

IFG bit IE bit GIE bitIE bit

1. Enable interrupt for GPIO pin

2. Enable interrupt source (GPIOport)

3. Globally enable interrupts

Interrupt service routine (ISR):Special “function” which isexecuted when a specific interruptis triggered

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 5

Hardware Timer

PCM

PowerControl

Manager

PSS

PowerSupplySystem

CS

ClockSystem

RTC_C

Real-TimeClock

WDT_A

WatchdogTimer

I/O Ports

P1 to P1078 I/Os

I/O Ports

PJ6 I/Os

Flash

256KB128KB

RSTCTL

ResetController

SYSCTL

SystemController

AES256

SecurityEncryption,Decryption

CRC32

PrecisionADC

1 Msps,SAR A/D

Comp_E0,Comp_E1

AnalogComparator

REF_A,

VoltageReference

TA0, TA1,TA2,TA3

Timer_A16 Bit5 CCR

Timer32

2 x 32-bitTimers

eUSCI_A0,eUSCI_A1,eUSCI_A2,eUSCI_A3

(UART,IrDA, SPI)

eUSCI_B0,eUSCI_B1,eUSCI_B2,eUSCI_B3

(I C, SPI)2

BusControlLogic

DMA

8 Channels

Capacitive Touch I/O 0,Capacitive Touch I/O 1

Address

Data

LFXIN,HFXIN

LFXOUT,HFXOUT

DCOR

LPM3.5 Domain

P1.x to P10.x PJ .x

BackupMemory

SRAM6KB

CPU

MPU

NVIC, SysTick

FPB, DWT

ARMCortex-M4F

ITM, TPIU

J TAG, SWD

SRAM(includesBackupMemory)

64KB32KB

ROM(Peripheral

DriverLibrary)

32KB

Copyright © 2017 Texas Instruments Incorporated

Timer_A (TA): internalperipheral of the MSP432.

4 instances:TA0, TA1, TA2, TA3

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 6

Hardware Timer

15 0

16-bit Counter(TA0R)

Interrupt (TA0ICG)

Divideby 5-bits

(up to ÷ 64)

Enable(TA0IE)

CCR0

CCR1

CCR2

Time

0xFFFF

0x0

CCR0

Counter Value

TA0Interrupt

CCR0Interrupt

Counter: Main component,incremented on every input edge

Divider: Divides the input clock signal

CCR: Registers to control the timer’sbehavior.

Counting modes:ContinuousUp (used in this lab)Up/Down

Output: interrupt, modify pin, signal toperipheral

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 7

Capture and CompareInput Capture

Capture/CompareRegister (CCRn)

CounterRegister

15 0TAR

CounterOverflow Action� Interrupt (TAICG)

Capture Input� CCInA� CCInB� Software

Capture Actions� Interrupt (CCICGn)� Signal peripheral� Modify pin (TAx.n)

Clock Input� Clock� GPIO Pin (TACLK)

Copying of counter value

If an event occurs, the current countervalue is stored in the CCR register (andoptionally another event is triggered).

Output Compare

Compare Actions� Interrupt (CCICGn)� Signal peripheral� Modify pin (TAx.n)

Capture/CompareRegister (CCRn)

CounterRegister

15 0

Clock Input� Clock� GPIO Pin (TACLK)

CounterOverflow Action� Interrupt (TAICG)

Comparing the

two registers

TAR

Triggers an action if the counter valueequals the CCR register value.

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 8

Lab 2

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Andreas Biri, Zhongnan Qu 14.10.2019 Page 1 of 2

Pulse-width Modulation (PWM)

Switch a load on and off at ahigh frequency

Average transferred powercan be configured with theduty-cycle in software Power

Time

Time

Pavg

Pmax

0

0xFFFF

0x0

CCR1

CCR0

Counter Value

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 9

Tasks of Lab 2

Task 1:InterruptsDebugging

Task 2:TimersPWM

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 10

Questions?

Andreas BiriETZ G75+41 44 632 08 73abiri@ethz.ch

Zhongnan QuETZ G76+41 44 632 70 21zhongnanqu@ethz.ch

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Andreas Biri, Zhongnan Qu 14.10.2019 11

Lab 2

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Andreas Biri, Zhongnan Qu 14.10.2019 Page 2 of 2