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EE141
CMOS Logic
EE141- Spring 2003Lecture 14
EE141
Static Complementary CMOS
VDD
F(In1,In2,…InN)
In1In2
InN
In1In2
InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networks
……
2
EE141
Standard Cells
Cell boundary
N WellCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch =repetitive distance between objects
Cell height is “12 pitch”
2λ
Rails ~10λ
InOut
VDD
GND
EE141
Standard Cells
A
Out
VDD
GND
B
2-input NAND gate
B
VDD
A
3
EE141
Multi-Fingered Transistors
One finger Two fingers (folded)
Less capacitance, Less resistance
EE141
Stick Diagrams
Contains no dimensionsRepresents relative positions of transistors
In
Out
VDD
GND
Inverter
A
Out
VDD
GNDB
NAND2
4
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Stick Diagrams
C
A B
X = C • (A + B)
B
AC
i
j
j
VDDX
X
i
GND
AB
C
PUN
PDNABC
Logic Graph
EE141
Two Versions of C • (A + B)
X
CA B A B C
X
VDD
GND
VDD
GND
5
EE141
Consistent Euler Path
j
VDDX
X
i
GND
AB
C
A B C
EE141
OAI22 Logic Graph
C
A B
X = (A+B)•(C+D)
B
A
D
VDDX
X
GND
AB
C
PUN
PDN
C
D
D
ABCD
6
EE141
Example: x = ab+cd
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}
b
EE141
CMOS Properties� Full rail-to-rail swing; high noise margins� Logic levels not dependent upon the relative
device sizes; ratioless� Always a path to Vdd or Gnd in steady state;
low output impedance� Extremely high input resistance; nearly zero
steady-state input current� No direct path steady state between power
and ground; no static power dissipation� Propagation delay function of load
capacitance and resistance of transistors
7
EE141
VTC of Complementary CMOS Gates
0.0 1.0
Vin, V
V
o ut
, V
2.0 3.00.0
1.0
2.0
3.0
A � 1, B �
A � B � 0→1
B � 1, A �
int
B
VDD
A
M3 M4A
B
F
M2
M1
0→1
0→1
EE141
Body Effect
8
EE141
Switch Delay Model
A
Req
A
Rp
A
Rp
A
Rn CL
A
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
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Input Pattern Effects on Delay
� Delay is dependent onthe pattern of inputs
� Low to high transition» both inputs go low
– delay is 0.69 Rp/2 CL
» one input goes low– delay is 0.69 Rp CL
� High to low transition» both inputs go high
– delay is 0.69 2Rn CL
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
9
EE141
Delay Dependence on Input Patterns
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=1→0
A=1→0, B=1
A=1, B=1→0
time [ps]
Vol
tage
[V]
57A= 1→0, B=1
76A=1, B=1→0
35A=B=1→0
50A= 0→1, B=1
62A=1, B=0→1
69A=B=0→1
Delay(psec)
Input DataPattern
NMOS = 0.5µm/0.25 µmPMOS = 0.75µm/0.25 µmCL = 100 fF
int
B
VDD
A
M3 M4A
B
F
M2
M1
EE141
Transistor Sizing
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
10
EE141
Transistor Sizing a ComplexCMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
1
2
2 2
4
4
8
8
6
6
12
12
EE141
Fan-In Considerations
DCBA
D
C
B
A CL
C3
C2
C1
Distributed RC model(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deterioratesrapidly as a function of fan-in –quadratically in the worst case.
11
EE141
tp as a Function of Fan-In
tpLH
t p(p
sec)
fan-in
Gates with afan-ingreater than4 should beavoided.
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
tpHL
quadratic
linear
tp
EE141
tp as a Function of Fan-Out
2 4 6 8 10 12 14 16
tpNOR2
t p(p
sec)
eff. fan-out
All gateshave thesame drivecurrent.
tpNAND2
tpINV
Slope is afunction of“drivingstrength”
12
EE141
tp as a Function of Fan-In andFan-Out
� Fan-in: quadratic due to increasingresistance and capacitance
� Fan-out: each additional fan-out gateadds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
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Fast Complex Gates:Design Technique 1
� Transistor sizing» as long as fan-out capacitance dominates
� Progressive sizing
InN CL
C3
C2
C1In1
In2
In3
M1
M2
M3
MNDistributed RC line
M1 > M2 > M3 > … > MN(the fet closest to theoutput is the smallest)
Can reduce delay by more than20%; decreasing gains astechnology shrinks
13
EE141
Fast Complex Gates:Design Technique 2
� Transistor ordering
C2
C1In1
In2
In3
M1
M2
M3 CL
C2
C1In3
In2
In1
M1
M2
M3 CL
critical path critical path
charged1
0→1charged
charged1
delay determined by time todischarge CL, C1 and C2
delay determined by time todischarge CL
1
1
0→1 charged
discharged
discharged
EE141
Fast Complex Gates:Design Technique 3
� Alternative logic structuresF = ABCDEFGH
14
EE141
Fast Complex Gates:Design Technique 4
� Isolating fan-in from fan-out using bufferinsertion
CLCL
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Fast Complex Gates:Design Technique 5
� Reducing the voltage swing
» linear reduction in delay» also reduces power consumption
� But the following gate is much slower!� Or requires use of “sense amplifiers” on the
receiving end to restore the signal level(memory design)
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )
15
EE141
Sizing Logic Paths for Speed
� Frequently, input capacitance of a logic pathis constrained
� Logic has to drive some capacitance� Example: ALU load in an Intel’s
microprocessor is 0.5pF� How do we size the ALU datapath to achieve
maximum speed?� We have already solved this for the inverter
chain – can we generalize it for any type oflogic?
EE141
Logical Effort for Inverter Chain
CL
In Out
1 2 N
D = D1 + D2 + …+ DN
+ +
i
ii C
CD
γτ 1
0 1~
∑∑=
+
=
+=
N
i i
iN
ii C
CTDelay
1
10
1
1~γ
τ
How do we extend thisto any logic network?
16
EE141
Logical Effort
+⋅=
γτ gf
pkDelay 0
p – parasitic delay - gate parameter ≠ f(W)g – logical effort – gate parameter ≠ f(W)f – electrical effort (effective fanout)
Normalize everything to an inverter:ginv =1, pinv = 1Everything is measured in unit delays τ0
EE141
Delay in a Logic Gate
Gate delay:
d = h + p
effort delay intrinsic delay
Effort delay:
h = g f
logical effort effective fanout = Cout/Cin
Logical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate size
17
EE141
Buffer Example
∑=
⋅+=N
i
iii
fgpDelay
1 γ
pi, gi are constant (and equal to 1)Variables are fiMinimum delay is when fi’s are equal(each stage bears the same effort)
CL
In Out
1 2 N
(in units of τ0)
EE141
Logical Effort
� Inverter has the smallest logical effort andintrinsic delay of all static CMOS gates
� Logical effort of a gate presents the ratio of itsinput capacitance to the inverter capacitancewhen sized to deliver the same current
� Logical effort increases with the gatecomplexity
18
EE141
Calculating Logical EffortLogical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output current
g = 1 g = 4/3 g = 5/3
EE141
Logical Effort of Gates
Fan-out (f)
Nor
mal
ized
dela
y(d
)
t
1 2 3 4 5 6 7
pINVt pNAND
F(Fan-in)
g=1p=1d=f+1
g=4/3p=2d=(4/3)f+2
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EE141
Logical Effort
EE141
Add Branching Effort
Branching effort:
pathon
pathoffpathon
C
CCb
−
−− +=
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EE141
Multistage Networks
Stage effort: hi = gifi
Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB
Path delay D = Σdi = Σpi + Σfigi/γ
∑=
⋅+=N
i
iii
fgpDelay
1 γ
EE141
Optimum Effort per Stage
HhN =ˆWhen each stage bears the same effort:
N Hh =ˆ
PNH
pfg
DN
iii +=
+=∑ γγ
/1ˆ
Minimum path delay
Effective fanout of each stage:ii ghf ˆ=
21
EE141
Example: Optimize Path
F = 2G = 20/9H = 40/9h =1.45x =10f1 = 10h/g1=14.5y = 14.5(1.45*3/5)=12.6z = 12.6(1.45*3/4)=13.7
From David Harris
f
Assume that size factors relate togate with some input cap as inverter
EE141
Multi-level logic: What is best?
g = 10/3 g =1G = 10/3
g = 2 g =5/3G = 10/3
g =10/3 g=5/3 g=4/3 g=1G = 80/27
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EE141
Handling Wires & Fixed Loads
CL
Cw
∑=
+⋅+=N
i
iiii
wfgpDelay
1
)(
γ
EE141
Summary
D = DH + Pd = h + pDelay
pParasitic Delay
N1Number of Stages
hEffort Delay
H = FGBh = fgEffort
n/aBranching Effort
f = Cout/CinElectrical Effort
gLogical Effort
PathStage
∏= igGinout CCF /=
∏= ibB
∑= iH hD
∑= ipP
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EE141
Method of Logical Effort
� Compute the path effort: H = GBF
� Find the best number of stages N ~ log4H
� Compute the stage effort h = H1/N
� Sketch the path with this number of stages
� Work either from either end, find sizes:Cin = Cout*g/h
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
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