Transistors for THz Systems - UCSB...RF Data: 25 nm thick base, 75 nm Thick Collector 0 5 10 15 20...

Transistors for THz Systems

Mark Rodwell, UCSB

IMS Workshop: Technologies for THZ Integrated Systems (WMD)

Monday, June 3, 2013, Seattle, Washington (8AM-5PM)

rodwell@ece.ucsb.edu

Co-Authors and Collaborators:

UCSB HBT Team: J. Rode, H.W. Chiang, A. C. Gossard , B. J. Thibeault, W. Mitchell Recent Graduates: V. Jain, E. Lobisser, A. Baraskar,

Teledyne HBT Team: M. Urteaga, R. Pierson, P. Rowell, B. Brar, Teledyne Scientific Company

Teledyne IC Design Team: M. Seo, J. Hacker, Z. Griffith, A. Young, M. J. Choe, Teledyne Scientific Company

UCSB IC Design Team: S. Danesgar, T. Reed, H-C Park, Eli Bloch

WMD: Technologies for THZ Integrated Systems RFIC2013, Seattle, June 2-4, 2013 1

DC to Daylight. Far-Infrared Electronics

Video-resolution radar → fly & drive through fog & rain

How high in frequency can we push electronics ?

...and what we would be do with it ?

100+ Gb/s wireless networks near-Terabit optical fiber links

1982: ~20 GHz 2012: 820 GHz ~2030: 3THz

109

1010

1011

1012

1013

1014

1015

Frequency (Hz)

microwave

SHF*

3-30 GHz

10-1 cm

mm-wave

EHF*

30-300 GHz

10-1 mm

optic

al

385-7

90 T

Hz

sub-mm-wave

THF*

0.3-3THz

1-0.1 mm

far-IR: 0.3-6 THz

near-IR

100

-385

TH

z

3-0

.78

mmid-IR

6-100 THz

50-3 m

*ITU band designations

** IR bands as per ISO 20473

2

THz Transistors: Not Just For THz Circuits

precision analog design at microwave frequencies → high-performance receivers

500 GHz digital logic → fiber optics

Higher-Resolution Microwave ADCs, DACs, DDSs

THz amplifiers→ THz radios → imaging, communications

3

THz Communications Needs High Power, Low Noise

Real systems with real-world weather & design margins, 500-1000m range:

3-7 dB Noise figure, 50mW- 1W output/element, 64-256 element arrays

Will require:

→ InP or GaN PAs and LNAs, Silicon beamformer ICs 4

THz Communications Needs High Power, Low Noise

Real systems→ LNAs with low Fmin, PAs with high Psat & high PAE

InP HEMTs give the best noise. InP HBT & GaN HEMT compete for the PA. Comparing technologies

CMOS is great for signal processing, but noise, power, PAE are poor. Harmonic generation is low power, inefficient. Harmonic mixing is noisy. 5

III-V PAs and LNAs in today's wireless systems...

http://www.chipworks.com/blog/recentteardowns/2012/10/02/apple-iphone-5-the-rf/

THz Device Scaling

7

nm Transistors, Far-Infrared Integrated Circuits

IR today→ lasers & bolometers → generate & detect

It's all about the interfaces: contact and gate dielectrics...

Far-infrared ICs: classic device physics, classic circuit design

...wire resistance,...

...heat,...

...& charge density.

band structure and density of states !

8

Transistor scaling laws: ( V,I,R,C,t ) vs. geometry

AR contact /

Bulk and Contact Resistances

Depletion Layers

T

AC

v

T

2

2

max)(4

T

Vv

A

I applsat

Thermal Resistance

Fringing Capacitances

~/ LC finging~/ LC finging

dominate rmscontact te

escapacitanc fringing FET )1

escapacitancct interconne IC )2

W

L

LK

PT

th

ln~transistor

LK

PT

th

ICIC

Available quantum states to carry current

→ capacitance, transconductance contact resistance 9

L

THz & nm Transistors: State Density Limits

2-D: FET 3-D: BJT

current

conductivity

capacitance

2/1

2/1

3

2 2n

qc

3/2

3/22

8

3n

qc

32

23

4

*

VmqJ

22

2/32/12/52/3

3

*2

VmqJ sheet

2

*2

2

mqCDOS

# of available quantum states / energy determines FET channel capacitance FET and bipolar transistor current access resistance of Ohmic contact

10

Bipolar Transistor Design eW

bcWcTbT

nbb DT 22

satcc vT 2

ELlength emitter

eex AR /contact

2

through-punchce,operatingce,max cesatc TVVAvI /)(,

contacts

contactsheet

612 AL

W

L

WR

e

bc

e

ebb

e

e

E W

L

L

PT ln1

cccb /TAC

11

Bipolar Transistor Design: Scaling eW

bcWcTbT

nbb DT 22

satcc vT 2

ELlength emitter cccb /TAC

eex AR /contact

2

through-punchce,operatingce,max cesatc TVVAvI /)(,

contacts

contactsheet

612 AL

W

L

WR

e

bc

e

ebb

e

e

E W

L

L

PT ln1

12

Breakdown: Never Less than the Bandgap

band-band tunneling: base bandgap impact ionization: collector bandgap

13

FET Design

g

DSWL

RRS/D

contact

gW width gate

gfgsgd WCC ,

)/( gchgm LvCg

)/( vWLR ggDS

)density state /well(2// 2

wellwell qTT

WLC

oxox

gg

chg

masstransport

1

capacitors threeabove the

between ratiodivision voltage2/1

v

14

FET Design: Scaling

g

DSWL

RRS/D

contact

gW width gate

gfgsgd WCC ,

)/( gchgm LvCg

)/( vWLR ggDS

)density state /well(2// 2

wellwell qTT

WLC

oxox

gg

chg

masstransport

1

capacitors threeabove the

between ratiodivision voltage2/1

v

15

FET Design: Scaling

g

DSWL

RRS/D

contact

gW width gate

gfgsgd WCC ,

)/( gchgm LvCg

)/( vWLR ggDS

)density state /well(2// 2

wellwell qTT

WLC

oxox

gg

chg

masstransport

1

capacitors threeabove the

between ratiodivision voltage2/1

v

16

2:1 2:1

constant 2:1 2:1

2:1 2:1

2:1 2:1 2:1

2:1

constant

constant

2:1 2:1

constant

2:1 2:1

4:1

constant

constant

FET parameter change

gate length decrease 2:1

current density (mA/m), gm (mS/m) increase 2:1

transport effective mass constant

channel 2DEG electron density increase 2:1

gate-channel capacitance density increase 2:1

dielectric equivalent thickness decrease 2:1

channel thickness decrease 2:1

channel density of states increase 2:1

source & drain contact resistivities decrease 4:1

Changes required to double transistor bandwidth

GW widthgate

GL

HBT parameter change

emitter & collector junction widths decrease 4:1

current density (mA/m2) increase 4:1

current density (mA/m) constant

collector depletion thickness decrease 2:1

base thickness decrease 1.4:1

emitter & base contact resistivities decrease 4:1

eW

ELlength emitter

constant voltage, constant velocity scaling nearly constant junction temperature → linewidths vary as (1 / bandwidth)2

fringing capacitance does not scale → linewidths scale as (1 / bandwidth )

17

THz & nm Transistors: what needs to be done

Metal-semiconductor interfaces (Ohmic contacts): very low resistivity Dielectric-semiconductor interfaces (Gate dielectrics---FETs only): thin !

Ultra-low-resistivity (~0.25 W-m2 ), ultra shallow (1 nm), ultra-robust (0.2 A/m2 ) contacts

Mo

InGaAs

Ru

InGaAs

Heat

W

L

LK

PT

th

ln~transistor

LK

PT

th

ICIC

Available quantum states to carry current L

→ capacitance, transconductance contact resistance 18

THz InP HBTs

19

Scaling Laws, Scaling Roadmap

HBT parameter change

emitter & collector junction widths decrease 4:1

current density (mA/m2) increase 4:1

current density (mA/m) constant

collector depletion thickness decrease 2:1

base thickness decrease 1.4:1

emitter & base contact resistivities decrease 4:1

scaling laws: to double bandwidth

eW

bcWcTbT

ELlength emitter

150 nm device 150 nm device

20

HBT Fabrication Process Must Change... Greatly

32 nm width base & emitter contacts...self-aligned

32 nm width emitter semiconductor junctions

Contacts: 1 W-m2 resistivities 70 mA/m2 current density ~1 nm penetration depths → refractory contacts

nm III-V FET, Si FET processes have similar requirements 21

Needed: Greatly Improved Ohmic Contacts Needed: Greatly Improved Ohmic Contacts

~5 nm Pt contact penetration (into 25 nm base)

Pt/Ti/Pd/Au

22

Ultra Low-Resistivity Refractory Contacts

10-9

10-8

10-7

10-6

1018

1019

1020

1021

N-InAs

Co

nta

ct

Re

sis

tiv

ity (

W

cm

2)

concentration (cm-3

)

1017

1018

1019

1020

N-InGaAs

concentration (cm-3

)

1018

1019

1020

1021

P-InGaAs

Ir

W

Mo

concentration (cm-3

)

Mo Mo

Barasakar et al IEEE IPRM 2012

32 nm node requirements

Contact performance sufficient for 32 nm /2.8 THz node.

Low penetration depth, ~ 1 nm

In-situ: avoids surface contaminants

Refractory: robust under high-current operation

23

Ultra Low-Resistivity Refractory Contacts

10-9

10-8

10-7

10-6

1018

1019

1020

1021

N-InAs

Co

nta

ct

Re

sis

tiv

ity (

W

cm

2)

concentration (cm-3

)

1017

1018

1019

1020

N-InGaAs

concentration (cm-3

)

1018

1019

1020

1021

P-InGaAs

Ir

W

Mo

concentration (cm-3

)

Mo Mo

Barasakar et al IEEE IPRM 2012

32 nm node requirements

Schottky Barrier is about one lattice constant

what is setting contact resistivity ?

what resistivity should we expect ?

24

Ultra Low-Resistivity Refractory Contacts

10-9

10-8

10-7

10-6

1018

1019

1020

1021

N-InAs

Co

nta

ct

Re

sis

tiv

ity (

W

cm

2)

concentration (cm-3

)

1017

1018

1019

1020

N-InGaAs

concentration (cm-3

)

1018

1019

1020

1021

P-InGaAs

Ir

W

Mo

concentration (cm-3

)

Mo Mo

Barasakar et al IEEE IPRM 2012

32 nm node requirements

limit)ty reflectivi-quantum

anddensity (state

:yresistivitcontact barrier -Zero

.cm/107 at m 1.0

tcoefficienon transmissi

ionconcentratcarrier

11

3

8

3192

3/22

3/2

2

W

n

T

n

nTq

c

c

25

Needed: Greatly Improved Ohmic Contacts Refractory Emitter Contacts

negligible penetration

26

HBT Fabrication Process Must Change... Greatly

Undercutting of emitter ends

control undercut → thinner emitter

thinner emitter → thinner base metal

thinner base metal → excess base metal resistance

{101}A planes: fast

{111}A planes: slow

tall, narrow contacts: liftoff fails !

27

HBT: V. Jain. Process: Jain & Lobisser

TiW

W 100 nm

Mo

SiNx

Refractory contact, refractory post→ high-J operation

Sputter+dry etch→ 50-200nm contacts

Sub-200-nm Emitter Contact & Post

Liftoff aided by TiW/W interface undercut

Dielectric sidewalls

28

RF Data: 25 nm thick base, 75 nm Thick Collector

0

5

10

15

20

25

1010

1011

1012

Ga

ins (

dB

)Frequency (Hz)

H21

U

f = 530 GHz

fmax

= 750 GHz

Required dimensions obtained but poor base contacts on this run

E. Lobisser, ISCS 2012, August, Santa Barbara

29

DC, RF Data: 100 nm Thick Collector

0

4

8

12

16

20

24

28

32

109

1010

1011

1012

Ga

in (

dB

)

Frequency (Hz)

U

H21

f = 480 GHz

fmax

= 1.0 THz

Aje = 0.22 x 2.7 m

2

Ic = 12.1 mA

Je = 20.4 mA/m

2

P = 33.5 mW/m2

Vcb

= 0.7 V

0

5

10

15

20

25

30

0 1 2 3 4 5

Je (

mA

/m

2)

Vce

(V)

P = 30 mW/m2

Ib,step

= 200 A

BV

P = 20 mW/m2

Aje

= 0.22 x 2.7 m2

10-9

10-7

10-5

10-3

10-1

0

5

10

15

20

0 0.2 0.4 0.6 0.8 1I c

, I b

(A

)

Vbe

(V)

Solid line: Vcb

= 0.7V

Dashed: Vcb

= 0V

nc = 1.19

nb = 1.87

Ic

Ib

Jain et al IEEE DRC 2011

30

Chart 31

THz InP HBTs From Teledyne

Urteaga et al, DRC 2011, June 31

Towards & Beyond the 32 nm /2.8 THz Node

Base contact process: Present contacts too resistive (4Wm2) Present contacts sink too deep (5 nm) for target 15 nm base

→ refractory base contacts

Emitter Degeneracy: Target current density is almost 0.1 Amp/m2 (!) Injected electron density becomes degenerate. transconductance is reduced.

→ Increased electron mass in emitter

32

Base Ohmic Contact Penetration

~5 nm Pt contact penetration (into 25 nm base)

Base Ohmic Contact Penetration

33

Refractory Base Process (1)

low contact resistivity low penetration depth

low bulk access resistivity

base surface not exposed to photoresist chemistry: no contamination low contact resistivity, shallow contacts low penetration depth allows thin base, pulsed-doped base contacts

Blanket liftoff; refractory base metal Patterned liftoff; Thick Ti/Au

34

Refractory Base Process (2)

0 100

5 1019

1 1020

1.5 1020

2 1020

2.5 1020

0 5 10 15 20 25

do

pin

g, 1

/cm

3

depth, nm

2 nm doping pulse

1018

1019

1020

1021

P-InGaAs

10-10

10-9

10-8

10-7

10-6

10-5

Hole Concentration, cm-3

B=0.8 eV

0.6 eV0.4 eV0.2 eV

step-barrierLandauer

Co

nta

ct

Res

isti

vit

y,

W

cm

2

32 nm node requirement

Increased surface doping: reduced contact resistivity, but increased Auger recombination. → Surface doping spike at most 2-5 thick. Refractory contacts do not penetrate; compatible with pulse doping. 35

Refractory Base Ohmic Contacts Refractory Base Ohmic Contacts

<2 nm Ru contact penetration (surface removal during cleaning)

Ru / Ti / Au

36

Degenerate Injection→ Reduced Transconductance

10-3

10-2

10-1

100

101

102

-0.3 -0.2 -0.1 0 0.1 0.2

J(m

A/

m2)

Vbe

-

Boltzmann

(-Vbe

)>>kT/q

)./exp( kTqVJJ bes

Transconductance is high

)./exp( kTqVJJ bes

JAg Em /

Current varies exponentially with Vbe

37

)./exp( kTqVJJ bes

Degenerate Injection→ Reduced Transconductance

10-3

10-2

10-1

100

101

102

-0.3 -0.2 -0.1 0 0.1 0.2

J(m

A/

m2)

Vbe

-

Fermi-Dirac

Boltzmann

(-Vbe

)>>kT/q

Transconductance is reduced

Current varies exponentially with Vbe

38

Degenerate Injection→ Reduced Transconductance

10-3

10-2

10-1

100

101

102

-0.3 -0.2 -0.1 0 0.1 0.2

J(m

A/

m2)

Vbe

-

Fermi-Dirac

Highly degenerate

(Vbe

->>kT/q

Boltzmann

(-Vbe

)>>kT/q

Highly degenerate limit:

)(8

* 2

32

3

beVmq

J

2* )( beE VmJ

current varies as the square of bias

39

Degenerate Injection→ Reduced Transconductance

10-3

10-2

10-1

100

101

102

-0.3 -0.2 -0.1 0 0.1 0.2

J(m

A/

m2)

Vbe

-

Fermi-Dirac

Highly degenerate

(Vbe

->>kT/q

Boltzmann

(-Vbe

)<<kT/q

Highly degenerate limit:

)(8

* 2

32

3

beVmq

J

2* )( beE VmJ

Transconductance varies as J1/2

current varies as the square of bias

JmAg EEm

*/

At & beyond 32 nm, we must increase the emitter effective mass.

...and as (m*)1/2

40

Degenerate Injection→Solutions

At & beyond 32 nm, we must increase the emitter (transverse) effective mass.

Other emitter semiconductors: no obvious good choices (band offsets, etc.).

Emitter-base superlattice: increases transverse mass in junction evidence that InAlAs/InGaAs grades are beneficial

Extreme solution (10 years from now): partition the emitter into small sub-junctions, ~ 5 nm x 5 nm. parasitic resistivity is reduced progressively as sub-junction areas are reduced.

41

3-4 THz Bipolar Transistors are Feasible.

4 THz HBTs realized by:

Extremely low resistivity contacts

Extreme current densities

Processes scaled to 16 nm junctions

Impact: efficient power amplifiers and complex signal processing from 100-1000 GHz.

42

InP HBT: Key Features

512 nm node: high-yield "pilot-line" process, ~4000 HBTs/IC

256 nm node: Power Amplifiers: >0.5 W/mm @ 220 GHz highly competitive mm-wave / THz power technology

128 nm node: >500 GHz f , >1.1 THz fmax , ~3.5 V breakdown breakdown* f = 1.75 THz*Volts highly competitive mm-wave / THz power technology

64 nm (2 THz) & 32 nm (2.8 THz) nodes: Development needs major effort, but no serious scaling barriers

1.5 THz monolithic ICs are feasible. 43

Can we make a 1 THz SiGe Bipolar Transistor ?

InP SiGe

emitter 64 18 nm width

2 0.6 Wm2 access

base 64 18 nm contact width,

2.5 0.7 Wm2 contact

collector 53 15 nm thick

36 125 mA/m2

2.75 1.3? V, breakdown

f 1000 1000 GHz

fmax 2000 2000 GHz

PAs 1000 1000 GHz

digital 480 480 GHz

(2:1 static divider metric)

Assumes collector junction 3:1 wider than emitter.

Assumes SiGe contacts no wider than junctions

Simple physics clearly drives scaling

transit times, Ccb/Ic

→ thinner layers, higher current density

high power density → narrow junctions

small junctions→ low resistance contacts

Key challenge: Breakdown

15 nm collector → very low breakdown

Also required:

low resistivity Ohmic contacts to Si

very high current densities: heat

44

THz InP Bipolar Transistor Technology Goal: extend the operation of electronics to the highest feasible frequencies

1 THz device Scaling roadmap through 3 THz 220 GHz power amplifiers

ultra-efficient 85 GHz power amplifiers

THz InP Heterojunction Bipolar Transistors 60-600 GHz IC examples; demonstrated & in fab

50 GHz sample/hold 40 GHz op-amp

100 GHz ICs for *electronic* demultiplexing of WDM optical communications

40 Gb/s phase-locked coherent optical receivers

Enabling Technologies : ~30 nm fabrication processes, extremely low resistivity (epitaxial, refractory) contacts, extreme current densities, doping at solubility limits, few-nm-thick junctions

Teledyne Scientific: moving THz IC Technology towards aerospace applications 1.1 THz pilot IC process 204 GHz digital logic (M/S latch) 670 GHz amplifier 300 GHz fundamental phase-lock-loop

Vout

VEE VBB

Vtune

Vout

VEE VBB

Vtune614 GHz fundamental oscillator (VCO)

182 mW 188 mW, 33% PAE

THz InP HEMTs and

III-V MOSFETs

46

FET parameter change

gate length decrease 2:1

current density (mA/m), gm (mS/m) increase 2:1

transport effective mass constant

channel 2DEG electron density increase 2:1

gate-channel capacitance density increase 2:1

dielectric equivalent thickness decrease 2:1

channel thickness decrease 2:1

channel density of states increase 2:1

source & drain contact resistivities decrease 4:1

Changes required to double transistor bandwidth

GW widthgate

GL

HBT parameter change

emitter & collector junction widths decrease 4:1

current density (mA/m2) increase 4:1

current density (mA/m) constant

collector depletion thickness decrease 2:1

base thickness decrease 1.4:1

emitter & base contact resistivities decrease 4:1

eW

ELlength emitter

constant voltage, constant velocity scaling nearly constant junction temperature → linewidths vary as (1 / bandwidth)2

fringing capacitance does not scale → linewidths scale as (1 / bandwidth )

47

FET scaling challenges...and solutions

Gate barrier under S/D contacts → high S/D access resistance addressed by S/D regrowth

High gate leakage from thin barrier, high channel charge density (almost) eliminated by ALD high-K gate dielectric

Other scaling considerations: low InAs electron mass→ low state density capacitance → gm fails to scale increased m* , hence reduced velocity in thin channels minimum feasible thickness of gate dielectric (tunneling) and channel

48

-0.2 0.0 0.2 0.4 0.60.0

0.4

0.8

1.2

1.6

2.0

2.4

Gm

(mS

/m

)

Cu

rre

nt

De

ns

ity

(m

A/

m)

Gate Bias (V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4 VDS

=0.05 V

VDS

=0.5 V

III-V MOS

Peak transconductance; VLSI-style FET: 2.5 mS/micron ~85% of best THz InAs HEMTs

0.1 10.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8 90 [011]

0 [01-1]

at Vds

=0.5V

Gate length (m)

Pe

ak

Tra

ns

co

nd

uc

tan

ce

(m

S/

m)

Lg = 40 nm (SEM)

III-V MOS will soon surpass HEMTs in RF performance

Sanghoon Lee

40 nm devices are nearly ballistic

49

In ballistic limit, current and transconductance are set by: channel & dielectric thickness, transport mass, state density

2/3*

,

2/1*

1

2/3

1

)/()/(1 where,

V 1m

mA84

oequivodos

othgs

mmgcc

mmgK

VVKJ

FET Drain Current in the Ballistic Limit

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

no

rma

lized

drive

cu

rre

nt

K1

m*/mo

g=2

EET=1.0 nm

0.6 nm

0.4 nm

g=1

InGaAs <--> InP Si

0.3 nm

EET=Equivalent Electrostatic Thickness

=Tox

SiO2

/ox

+Tinversion

SiO2

/semiconductor

/EETε

)/c/c(c oxequiv

2SiO

1

depth

11

2

0

2

, 2/ mqc odos

minima band # g

50

Low m* gives lowest transit time, lowest Cgs at any EOT.

Transit delay versus mass, # valleys, and EOT

51

2/1*

,

2/1

0

*

2

2/1

72 1 whereVolt 1

cm/s 1052.2

oeq

odos

thgs

g

D

chch

m

mg

c

c

m

mK

VV

LK

I

Q

0

0.5

1

1.5

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

No

rma

lize

d t

ran

sit d

ela

y K

2

m*/mo

EOT=1.0 nm

EOT includes wavefunction depth term

(mean wavefunction depth*SiO2

/semiconductor

)

0.6 nm

0.4 nm

g=1, isotropic bands

g=2, isotropic bands

1 nm

0.4 nm

0.6 nm

/EOTε

)/c/c(c oxequiv

2SiO

1

semi

11

InGaAs

Si, GaN

FET Scaling: fixed vs. increasing state density

52

0

500

1000

1500

2000

2500

3000 canonical scaling

stepped # of bands

transport only

f , G

Hz

0

500

1000

1500

2000

2500

3000

3500

4000

f ma

x, G

Hz

0

0.5

1

1.5

2

2.5

0 10 20 30 40 50 60

dra

in c

urr

ent

density, m

A/

m

gate length, nm

200 mV gate overdrive

0

200

400

600

800

1000

0 10 20 30 40 50 60

SC

FL

sta

tic d

ivid

er

clo

ck r

ate

, G

Hz

gate length, nm

f fmax

mA/m→ VLSI metric SCFL divider speed

Need higher state density for ~10 nm node

2-3 THz Field-Effect Transistors are Feasible.

3 THz FETs realized by:

Ultra low resistivity source/drain

High operating current densities

Very thin barriers & dielectrics

Gates scaled to 9 nm junctions high-barrier HEMT MOSFET

Impact: Sensitive, low-noise receivers from 100-1000 GHz.

3 dB less noise → need 3 dB less transmit power.

or

53

4-nm / 5-THz FETs: Challenges

4 nm

Channel thickness 0.8 nm: UTB 1.6 nm: fin atomically flat

Gate dielectric 0.1 nm EOT: UTB 0.2 nm EOT: fin

Estimated (WKB) tunneling current is just acceptable at 0.2 nm EOT.

How can we make a 1.6 nm thick fin, or a 0.8 nm thick body ? 54

Thin wells have high scattering rate

Need single-atomic-layer control of thickness Need high quantization mass mq.

Sakaki APL 51, 1934 (1987).

./1y probabilit Scattering 62

wellqTm

55

III-V vs. CMOS: A false comparison ?

UTB Si MOS UTB III-V MOS III-V THz MOS/HEMT

III-V THz HEMT

III-V MOS has a reasonable chance of future use in VLSI

The real THz / VLSI distinction: Device geometry optimized for high-frequency gain vs. optimized for small footprint and high DC on/off ratio.

56

Conclusion

57

THz and Far-Infrared Electronics

IR today→ lasers & bolometers → generate & detect

It's all about classic scaling: contact and gate dielectrics...

Far-infrared ICs: classic device physics, classic circuit design

...wire resistance,...

...heat,...

...& charge density. band structure and density of quantum states (new!).

Even 1-3 THz ICs will be feasible

58

(backup slides follow)

59

Electron Plasma Resonance: Not a Dominant Limit

*2kinetic

1

nmqA

TL

T

AC

ntdisplaceme

m

scatterL

Rf

2

1

2

1

frequency scattering

kinetic

bulk

mnmqA

TR

*2bulk

1

2

1

2/1

frequency relaxation dielectric

bulkntdisplaceme

RC

fdielecic

ntdisplacemekinetic

2/1

frequencyplasma

CLf plasma

THz 800 THz 7 THz 74319 cm/105.3

InGaAs-

n

319 cm/107

InGaAs-

pTHz 80 THz 12 THz 13

60