Verilog Tutorial 2_Kien 082009

VERILOG TUTORIAL 2

Da Nang University of Technology

Prepaired by: Kien T.Nguyen, Lab AssistantNghia Nguyen, Lab Assistant

Materials Tools:

Specification: Word, AbiWord, Open Office RTL coding: HDL TurboWriter, Notepad++, Vim,

Emacs, conTEXT Simulation: iVerilog, ModelSim, Quartus

Simulator, ISE Simulator Synthesis: Quartus, Xilinx ISE

Website: www.asic-world.com www.dut.udn.vn/ece

Reference documents link

DE1_UserManual_v1018.pdf QUARTUS II INTRODUCTION USING

VERILOG DESIGN.ppt

Lectures Outline

1. Altera DE1 Kit.2. Quartus Tutorial3. Lab 3: Implement Mux circuit in DE1 Kit4. Lab 4: Full design Led 7 segment decode

circuit

1. Altera DE1 Kit

DE1 Overview. FPGA is the brain of DE1 Kit. So what is

FPGA? DE1’s pin which are connecting our

resources

Link to read more: DE1_UserManual_v1018.pdf

DE1 Kit Overview

We only need knew them

FPGA. What is it ? FPGA Cylone II is the brain of DE1 Kit

We will find the pin number of them to usewhen implement circuit

FPGA structure.

Now, just keep in mind •LUT use to generate logic circuit. •D Flip-Flop seem an interesting logic.

FPGA pin that are connecting our resources are:

Push buttons are active in low level

Up position is in high levelDow position is in low level

Leds are active on high level. Theywill turn on if have high level input

And 4 leds 7 segments:

7 segments Leds are active in low level. It mean the segment will light onwhen we give it logic 0.

2. Quartus Tutorial A typical FPGA CAD flow Quartus tutorial (Read link below)

Link Read more: QUARTUS II INTRODUCTION USING VERILOG DESIGN.ppt

Quartus tutorial

Link

Quartus software download link: Quartus 9 Webpack

Skim it before Lab: QUARTUS II INTRODUCTION USING VERILOG DESIGN.ppt

3. Lab 1: Implement Mux circuit in FPGA.

1. Generate project Mux2_1 2. Add module mux2_1 (change name from

mux) to the project. 3. Assign pin: Signal sel to switch 0, b to

switch 1, c to switch 2; f to red led 0. Use pin assign tables in slide.

4. Implement: Program to DE 1 Kit. Congratulation! You have real design now.

5. Test in the real circuit and hardware. 6. Make the hard report submit to LA or your

teacher.

4. Lab 2. Full design 7 seg decoder circuit

1. Finish the verilog coding with 7segdecoder module follow the specification (1 structural code and 1 behavior code)

2. Finish your stimulus in module testbench 3. Write test bench to check circuit function

using Icarus. 4. Synthesis your design, assign pins and

program to DE1 kit. 5. Make the hard report submit to LA or your

teacher.

BCD to 7 segments decoder

Why can write function of output 0 to 6 from truth table ? You will learn later. Now just for being family with DE1.

1. We already knew about convertDecimal system to Binary system.

2. Each segment will light on when the input pin is in low level. Ex: if (switch = 4’b0000) then

led_out = 7’b1000000;

Function expression of out put

Find the relation between these functions and the truth table in slide 16.But it is not important now. See this slide later when you meet this problem

again in lecture.

Structural model

Function expression of out put

case SW4'b0000: Led_Out = 7'b0000001; // 04'b0001: Led_Out = 7'b1001111; // 14'b0010: Led_Out = 7'b0010010; // 24'b0011: Led_Out = 7'b0000110; // 34'b0100: Led_Out = 7'b1001100; // 44'b0101: Led_Out = 7'b0100100; // 5………………………………………………. // can you continue

endcase

Find the more comfortable of behavior models than structural models.But what are the incomfortable ?

Behavior model

Pin’s information of DE1 Kit

Value 0, Led is onValue 1, Led is off

Finish the sample codes

Download these Links: Structural file Behavior file

Which one do you prefer: structural file or behavior file ? Why ?

If you are good in digital circuit, practice more in structural file.

Laboratory Final Report There is one hard report per team. The report contain all the lab your team have

done, code, test result in Icarus, test result in DE1 , answer questions.

Structure of report: Member: Names and class Introduction about this Lab Lab report Analysis Errors Summary