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Why do Measurement-based Channel Modeling ?
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AgendaAgenda
• Why do measurement based channel modeling?• Tyco™ HM-ZD legacy backplane study
• Backplane measurements using Vector Network Analyzer (VNA) and PLTS• Importance of VNA Calibration
• Short, Open, Line, & Thru (SOLT)• De-embedding• Thru Reflect Line (TRL)
• Physical Layer Test System (PLTS) measurements• Mixed mode S-parameters• TDR and Eye Diagram measurements
• Advanced Design System simulations• TDR simulation using S-parameters• Building backplane model in ADS• Time domain optimization of backplane model• Model verification using measured data
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Digital Data Rates are IncreasingDigital Data Rates are Increasing
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Digital Data Rates are IncreasingDigital Data Rates are Increasing
Risetimes get faster
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Digital Data Rates are IncreasingDigital Data Rates are Increasing
Via stub reflections get
larger
Risetimes get faster
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Digital Data Rates are IncreasingDigital Data Rates are Increasing
Via stub reflections get
larger
Risetimes get faster
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Typical 10 Gbps Telecom SystemTypical 10 Gbps Telecom System
Components
Line Cards
Network Elements & Systems
Modules
Trunk Fiber
Copper
Router
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Backplanes are a Critical LinkBackplanes are a Critical Link
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ConnectorsBackplanes
IC Packages
Cables
PC Boards
Signal Integrity Problems are EverywhereSignal Integrity Problems are Everywhere
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Example: Tyco HM-Zd Legacy XAUI BackplaneExample: Tyco HM-Zd Legacy XAUI Backplane
The Channel
The Channel consists of one differential transmission line•One 16” backplane
•Two 2” daughter cards
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24
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AgendaAgenda
• Why do measurement based channel modeling?• Tyco™ HM-ZD legacy backplane study
• Backplane measurements using Vector Network Analyzer (VNA) and PLTS• Importance of VNA Calibration
• Short, Open, Line, & Thru (SOLT)• De-embedding• Thru Reflect Line (TRL)
• Physical Layer Test System (PLTS) measurements• Mixed mode S-parameters• TDR and Eye Diagram measurements
• Advanced Design System simulations• TDR simulation using S-parameters• Building backplane model in ADS• Time domain optimization of backplane model• Model verification using measured data
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= Pre-measurement error correction= Post-measurement error correction
MostAccurate
Easiest
S-Parameter De-embedding
Port ExtensionTime Domain Gating
NormalizationReference Plane Calibration
Thru-Reflect-Line (TRL)Line-Reflect-Match (LRM)
Short-Open-Load-Thru (SOLT)
Error Correction Techniques (aka Calibration)Error Correction Techniques (aka Calibration)
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Short-Open-Load-Thru (SOLT) Calibration Short-Open-Load-Thru (SOLT) Calibration
•Electronic Calibration Module (ECal)
•Mechanical Calibration Kit
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De-embedding Example with PLTSDe-embedding Example with PLTS
Step 1
Step 2
Step 3
Assumption: Touchstone (s-parameter) file is available. For extraction of Touchstone file of your fixture, visit www.gigatest.com
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Methods for Obtaining De-embed FilesMethods for Obtaining De-embed Files
• Two tier adaptor removal using PLTS• www.agilent.com/find/plts
• Model from geometry layout• www.agilent.com/find/eesof-eda
• Professional services for fee• www.gigatest.com
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Thru-Reflect-Line (TRL) CalibrationThru-Reflect-Line (TRL) Calibration
TRL Calculator courtesy of Molex
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Thru-Reflect-Line (TRL) CalibrationThru-Reflect-Line (TRL) Calibration
TRL PCB courtesy of Molex
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Typical Reference Plane LocationTypical Reference Plane Location
• SOLT (Easiest)
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••
••
••
••
SOLT
SOLT
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Typical Reference Plane LocationTypical Reference Plane Location
• SOLT (Easiest)• De-embedding (Most Accurate)
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••
••
••
••
SOLT
SOLT
De-embedding
De-embedding
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Typical Reference Plane LocationTypical Reference Plane Location
• SOLT (Easiest)• De-embedding (Most Accurate)• TRL (Most Flexible)
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••
••
••
••
SOLT
SOLT
De-embedding
De-embeddingTRLTRL
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Typical Reference Plane LocationTypical Reference Plane Location
• SOLT (Easiest)• De-embedding (Most Accurate)• TRL (Most Flexible)
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••
••
••
••
SOLT
SOLT
De-embedding
De-embeddingTRLTRL
GoodBetter
Best
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AgendaAgenda
• Why do measurement based channel modeling?• Tyco™ HM-ZD legacy backplane study
• Backplane measurements using Vector Network Analyzer (VNA) and PLTS• Importance of VNA Calibration
• Short, Open, Line, & Thru (SOLT)• De-embedding• Thru Reflect Line (TRL)
• Physical Layer Test System (PLTS) measurements• Mixed mode S-parameters• TDR and Eye Diagram measurements
• Advanced Design System simulations• TDR simulation using S-parameters• Building backplane model in ADS• Time domain optimization of backplane model• Model verification using measured data
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Measurement Set UpMeasurement Set Up4-port Vector Network Analyzer
Physical Layer Test System Software (PLTS)
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Differential S-parametersDifferential S-parameters
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Physical Layer Test System (PLTS) MeasurementsPhysical Layer Test System (PLTS) Measurements
SDD21
TDD11TDC11
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Typical Frequency Domain AnalysisTypical Frequency Domain Analysis
Differential Insertion
Loss(SDD21)
Differential Return Loss
(SDD11)
Differential Crosstalk(SDD13)
Measurement data courtesy of University of New Hampshire
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Typical Time Domain AnalysisTypical Time Domain Analysis
SMA Launch
Daughter card traces
Daughter card via
Backplane via
connector Backplane traces
SMA Launch
Daughter card traces
Daughter card via
Backplane viaconnector
Impe
danc
e, in
Ohm
s
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Synthesizing Eye Diagrams from TDD21Synthesizing Eye Diagrams from TDD21
PRBS, 5 Gbps, 211 – 1 bits
Convolution integral
=Overlay each bit, synchronous with the clock
+Displayed with Agilent’s PLTS
Impulse Response
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Differential Eye Diagram AnalysisDifferential Eye Diagram Analysis
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Transparent Translation Between PLTS and ADSTransparent Translation Between PLTS and ADS
TDR
TermTerm3
Z=50 OhmNum=3
TermTerm1
Z=50 OhmNum=1
TeTe
Z=Nu
TeTe
Z=NuML2CTL_V
CLin1
W [1]=W _1 milLength=Len inSubst="Subst1"
ADS
VNA
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Transparent Translation Between PLTS and ADSTransparent Translation Between PLTS and ADS
Single ended S-parameters Differential S-parameters
Differential T-parametersSingle ended T-parameters
TDR
TermTerm3
Z=50 OhmNum=3
TermTerm1
Z=50 OhmNum=1
TeTe
Z=Nu
TeTe
Z=NuML2CTL_V
CLin1
W [1]=W _1 milLength=Len inSubst="Subst1"
ADS
VNA
Frequency Domain
Time Domain
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TDR or VNA with PLTS System?TDR or VNA with PLTS System?
In order to get the measurement-based model of a differential interconnect, the full 4x4 s-parameter matrix must be obtained. This dictates the use of a VNA for this application to be accomplished.
Ideal SystemCustomer ConcernsTDR-based VNA-based Both
Greatest Ease of Use, Quick Set Up XGood First-Order Characterization XCalculates Excess Reactance XBest Dynamic Range (SNR) for measuring low levels of crosstalk X
Best Models XCharacterize Small Coupling Effects XHighest Accuracy XError Correction Capability XS-Parameters X
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AgendaAgenda
• Why do measurement based channel modeling?• Tyco™ HM-ZD legacy backplane study
• Backplane measurements using Vector Network Analyzer (VNA) and PLTS• Importance of VNA Calibration
• Short, Open, Line, & Thru (SOLT)• De-embedding• Thru Reflect Line (TRL)
• Physical Layer Test System (PLTS) measurements• Mixed mode S-parameters• TDR and Eye Diagram measurements
• Advanced Design System simulations• TDR simulation using S-parameters• Building backplane model in ADS• Time domain optimization of backplane model• Model verification using measured data
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Measured S-parameter using PLTS
TDR simulation is used to:• Detect discontinuities • Locate discontinuities• Quantify discontinuities• Build equivalent circuits from measured data
TDR Simulation in Advanced Design SystemTDR Simulation in Advanced Design System
The Goal is to create the backplane model using TDR response
Comparison of ADS and PLTS TDR response
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•Enables “what if” analysis
• Swap components one by one
• Improve performance of an existing design
•Greater understanding of the internal dynamics of the channel
• Without a model you are limited to the information at the terminals
•Avoid the need to build complex test fixtures for de-embedding
Why Create a Model?Why Create a Model?
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Circuit Model TopologyCircuit Model Topology
Reference : “Hacking the Backplane: Optimizing Backplane Performance with Measurement Based Models Using Agilent ADS” by Eric Bogatin
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Circuit Model TopologyCircuit Model Topology
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Circuit Model TopologyCircuit Model Topology
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Circuit Model TopologyCircuit Model Topology
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Circuit Model TopologyCircuit Model Topology
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Model OptimizationModel OptimizationModel will be acceptable ideally when:TDR response, TDT response, NEXT and FEXT waveformsare the same as measured data.
Parameters that will be optimized:Transmission line impedance, length, spacing, and via capacitance.
Strategy:•Start at the beginning of the model
•Optimize six components (1 through 6 ) using parameter sweep
•Try for TDR best fit
1
2
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5 6
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Modeling Daughter CardModeling Daughter Card
13 4
5 6
2Optimizing Daughter Card Parameters• Dielectric thickness Affects line impedance
Daughter Card dielectric thickness is varied from 8 to 12 mils.
Optimized value ~ 9.2 mils
High impedance
(Dielectric thickness 12 mils)
Low impedance
(Dielectric thickness 8 mils)
measuredsimulated
TDR Response
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Modeling Daughter CardModeling Daughter Card
13 4
5 6
2Optimizing Daughter Card Parameters• Line spacing Impact crosstalk
NEXT Response
Daughter Card line spacing is varied from 10 to 20 mils.
Optimized value ~ 14 mils
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Modeling Daughter Card ViaModeling Daughter Card Via
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45 6
2Optimizing Daughter Card Via Parameters• Via transmission line impedance – Impact TDR/TDT response• Via parasitic capacitance Impact NEXT & FEXT
Spill over effects to neighboring components
Optimized value:
Z21 30 Ohm
Z11 65 Ohm
C 0.4 pF
Ze = Z11 + Z12Zo = Z11 – Z12
Effect of sweeping Daughter card via parameters
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Modeling BackplaneModeling Backplane
13 5 6
2
Sweeping backplane differential line width
Optimizing Backplane Line Parameters• Line width Affect line impedance
Narrower the line width, the higher the impedance
Optimized value:
Line width 11.2 mils
Line spacing 16.2 mils
4
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Backplane Model – Fully Synthesized Backplane Model – Fully Synthesized
Comparing time-domain performance of model and measured data
TDR TDT
NEXT FEXT
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Comparing Eye DiagramsComparing Eye Diagrams
Difference between model and measurement
Eye height : ~ 11 mV
Rise time : ~23 psec
Fall time : ~17 psec
Jitter : ~40 psec
Model
MeasurementIs the model acceptable?
Can we improve this model any further?
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The Optimization ProblemThe Optimization ProblemOptimization Automatically modify model parameters to meet design goals
GoalsModel to provide the same TDR, TDT, NEXT and FEXT waveform as measured data
Measured data
Difficult to define optimization goal in time domain
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Time Domain OptimizationTime Domain Optimization
Model
Measurement
Step 1 : Measure node voltage at A and BStep 2: Calculate difference of A and BStep 3: Optimize difference to zero A
B
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The Optimized ResponseThe Optimized Response
NEXT FEXT
TDR
Comparing backplane time-domain simulation performance
1st pass model
Optimized modelMeasured data
1st pass model
Optimized modelMeasured data
1st pass model
Optimized modelMeasured data
TDT
1st pass model
Optimized modelMeasured data
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Comparison with DCA – MeasurementsComparison with DCA – Measurements
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Comparison of Simulation PerformanceComparison of Simulation Performance
Measurement
1st Pass Model
Optimized Model
Performance DifferenceEye height: ~ 11 mV
Rise time : ~ 23 psec
Fall time : ~ 17 psec
Jitter : ~ 48 psec
Performance DifferenceEye height: ~ 4 mV
Rise time : ~ 7 psec
Fall time : ~ 6 psec
Jitter : ~ 28 psec
Time-domain optimization helped to improve design performance
Earlier
Now
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BER PerformanceBER PerformanceStateye Sink in ADS is used here to calculate Worst-Case BER performance
Transient co-simulation of Tyco™ channel with ADS Ptolemy
Measurement
Model
Comparison of BER performance
S-parameter model vs. measurements
1.0 Gb
3.5 Gb
6.0 Gb8.5 Gb
10 Gb
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Comparison with Measured DataComparison with Measured Data
-0 .4 0 9 -0 .3 1 8 -0 .2 2 7 -0 .1 3 6 -0 .0 4 5 0 .0 4 5 0 .1 3 6 0 .2 2 7 0 .3 1 8 0 .4 0 9-0 .5 0 0 0 .5 0 0
1 E -1 6
1 E -1 4
1 E -1 2
1 E -1 0
1 E -8
1 E -6
1 E -4
1 E -2
1 E -1 8
6 E -1
S t a t E y e 1 . S 1 . T im e _ U I
BER
Comparison of Tyco backplane measured BER performance against ADS model simulated using Stateye
JBERT
DCA-J 86100C
Data Rate – 2.5 Gbps
Random Jitter – 10.7mUI (rms)
Periodic Jitter – 220mUI (sinusoidal)
Simulated BER performance of Backplane design using Stateye
functionality within ADS
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Why Create a Model?Why Create a Model?Now we are able to see eye budget information without any requirements for special de-embedding.
Key Learning: The most dramatic degradation of the eye diagram performance is due to the via field and the backplane interconnect.
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ConclusionConclusion
• Models can be created from measured S-parameters• S-parameters are required to provide accurate
• Channel design topology• TDR, TDT, Eye Diagram, and BER performance
• This technique obtains good correlation between measurement and models and provides greater understanding of the design
• Resources utilized • Vector Network Analyzer (VNA)• Physical Layer Test System (PLTS)• Advanced Design System (ADS)• Digital Communication Analyzer (DCA-J).
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Resources Resources
Websites•www.agilent.com/find/plts•www.agilent.com/find/eesof-eda
Software•Physical Layer Test System (PLTS)•Advanced Design Software (ADS)
Hardware •N1957B VNA-based PLTS•86100C TDR-based PLTS•86100C- DCA J
PLTS Studio - Analysis Only Software • N1930B-1NP networked license• N1930B-1FP fixed license• N1930B-1TP USB key license
1. PNA
2. Test Set3. Software
1. TDR Scope
2. Software
3. TDR Modules
Physical Layer Test System (PLTS) Configurations
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