Verilog hdl

What is HDL?

hardware description language describes the hardware of digital systems in textual form.

One can design any hardware at any levelSimulation of designs before fabricationWith the advent of VLSI, it is not possible to

verify a complex design with millions of gates on a breadboard, HDLs came into existence to verify the functionality of these circuits.

Most Commonly used HDLsVerilog

Verilog HDL is commonly used in the US industry. Major digital design companies in Pakistan use Verilog HDL as their primary choice.

most commonly used in the design, verification, and implementation of digital logic chipsdigital logic chips

VHDL (VHSIC (Very High Speed Integrated Circuits) (Very High Speed Integrated Circuits) hardware description language)VHDL is more popular in Europe. commonly used as a design-entry language for

field-programmable gate arraysfield-programmable gate arrays. . Field-Programmable Gate Array is a type of logic chip that can be programmed.

Verilog Simulator

There are many logic simulators used for Verilog HDL. Most common are:XilinxVeriwellModel Sim

For Beginners Veriwell is good choice and is very user friendly.Xilinx and ModelSim are widely used.

Levels of AbstractionThere are four different levels of abstraction in verilog:

Behavioral /AlgorithmicData flowGate levelSwitch level.

We will cover Gate level, Data flow and Behavioral Level modeling

Getting started…

A verilog program for a particular application consists of two blocks

Design Block (Module)Testing Block (Stimulus)

Design Block

Design Methodologies:

Two types of design methodologies Top Down Design Bottom Up Design

Design Block

inputs outputs

In Top Down design methodology, we define the top level block and identify the sub-blocks necessary to build the top level block. We further divide the sub-block until we come to the leaf cells, which are the cells which cannot be divided.

In a Bottom Up design methodology, we first identify the building blocks , we build bigger blocks using these building blocks. These cells are then used for high level block until we build the top level block in the design

EXAMPLE

FOUR BIT ADDER (Ripple carry adder)

Module RepresentationVerilog provides the concept of module

A module is a Basic Building block in Verilog Basic Building block in Verilog It can be a single element or collection of lower design

blocks

A verilog code starts with module

Syntax:Syntax:

module <module-name>(inputs, outputs);

//Define inputs and outputs …………

………… …………

endmodule

Every verilog program starts with the keyword module and ends with the keyword endmodule

Input Output DefinitionOnce the module is defined at the start the inputs

and outputs are to be defined explicitly. e.g.

input a , b //means there are 2 inputs of one bit each

If input or output is more than 1 bit i.e. two or more bits, then the definition will be:

input [3:0] A, B; //4 bit inputs A3-A0 and B3-B0

output [3:0] C;

Levels of Abstraction

Gate Level ModelingIn gate level modeling a circuit can be defined by use of logic gates.

These gates predefined in verilog library.

The basic gates and their syntax is as follows:and gate_name(output, inputs);or gate_name(output, inputs);

not gate_name (output, inputs);xor gate_name(output, inputs);nor gate_name(output, inputs);

nand gate_name(output, inputs);xnor gate_name(output, inputs);

Data Flow ModelingContinuous assignment statement is used. Keyword assign is used followed by =Most common operator types are

Operator Types

Operator Symbol

Operation performed

Number of Operands

Arithmetic * / + -

Multiply Divide Add Subract

Two Two Two two

Bitwise Logical ~ & | ^ ^~ or ~^

Bitwise negation Bitwise and Bitwise or Bitwise xor Bitwise xnor

One Two Two Two two

Shift >> <<

Shift right Shift left

Two Two

Concatenation { }

Concatenation Any number

Conditional ?: Conditional three

Examples1. assign x = a + b;2. assign y = ~ x ; // y=x’3. assign y = a & b; // y= ab4. assign w = a ^ b; //y= a b5. assign y = x >> 1; //shift right x by 16. assign y = {b, c}; //concatenate b with

c e.g. b = 3’b101, c =3’b 111 y = 101111assign {cout , sum} = a + b + cin; //concatenate sum

and cout7. assign y = s ? b : a // 2×1 multiplexer when s = 1 , y = b when s = 0 , y = a assign y = s1 ? ( s0 ? d : c ) : ( s0 ? b : a ); // 4×1

MUX

Module Instantiation

Module instantiation is a process of connecting one module to another.

For example in a test bench or stimulus the top level design has to be instantiated

Testing Block (Stimulus)

In order to test your circuit a test bench code is to be written which is commonly called Stimulus.

The design block has to be instantiated/called

It displays the output of the design based on the inputs.

Example

2- Input AND Gate

The Design and Stimulus blocks will be as follows:

Design Block

1)Gate Level Modeling

module practice (y, a, b); //module definitioninput a, b; // inputs(by default it takes 1 bit inputoutput y; // one bit outputand gate_1(y, a, b) ;endmodule

2) Data Flow Modeling

module practice (y, a, b); //module definitioninput a, b; // by default it takes 1

bit inputoutput y; // one bit outputassign y = a & b;endmodule

Stimulus Blockmodule stimulus;reg a, b;wire y;//Instantiate the practice module

practice p0(y, a, b);

initialbegin a=0; b=0;#5 a=1; b=1; #5 a=0; b=1;#5 a=1; b=0;#5 a=1; b=1;

#5 $stop; // stop the simulation

#5 $finish; // terminate the simulation

endinitialbegin$display("|%b| and |%b| = ", a,

b);$monitor ($time, "|%b |" , y);end//initial//$vw_dumpvars; // display the

simulation in the form of timing diagram

endmodule

Example #2:4 bit ripple carry adder4 bit ripple carry adder

Full Adder

Bottom Level module//Define a full adder

module fulladder (sum, c_out, a, b, c_in);

//I/O Port declaration

output sum, c_out;input a, b, c_in;

//Internal nets

wire s1, c1, c2;

//full adder logic configuration

xor ( s1,a,b);and (c1,a,b);

xor (sum,s1,c_in);and (c2,s1,c_in);

or (c_out,c2,c1);

endmodule

TOP LEVEL MODULE//Define a 4 bit 4 adder

module toplevel_fa(sum,c_out,a,b,c_in);//I/O port declaration

output [3:0] sum;output c_out;input [3:0] a, b;input c_in;

//internal netswire c1,c2,c3;

//Instantiate four 1-bit full adderfulladder fa0(sum[0],c1,a[0],b[0],c_in);fulladder fa1(sum[1],c2,a[1],b[1],c1);fulladder fa2(sum[2],c3,a[2],b[2],c2);fulladder fa3(sum[3],c_out,a[3],b[3],c3);endmodule

Test Bench (stimulus)

//define stimulus toplevel modulemodule stimulus;

reg [3:0]a,b; //set up variablesreg c_in;wire [3:0] sum;wire c_out;

//Instantiate the toplevelmodule(ripple carry adder) call it tl

toplevel_fa tl(sum,c_out,a,b,c_in);

//stimulate inputs initialbegin a = 4'b0000; b = 4'b0010; c_in = 1'b0;a = 4'b0000; b = 4'b0010; c_in = 1'b0;

#1 $display (“ a = %b, b = %b, c_in = %b, sum = %b", a, b, #1 $display (“ a = %b, b = %b, c_in = %b, sum = %b", a, b, c_in, sum);c_in, sum);

a = 4'd1; b = 4'd2; c_in = 1'b1;a = 4'd1; b = 4'd2; c_in = 1'b1;

#2$display (“ a = %b, b = %b, c_in = %b, sum = %b", a, b, #2$display (“ a = %b, b = %b, c_in = %b, sum = %b", a, b, c_in, sum);c_in, sum);

a = 4'hf; b = 4'ha; c_in = 1'b0;a = 4'hf; b = 4'ha; c_in = 1'b0;

#2$display (“ a = %b, b = %b, c_in = %b, sum = %b", a, b, #2$display (“ a = %b, b = %b, c_in = %b, sum = %b", a, b, c_in, sum);c_in, sum);endendmodule

Verilog KeywordsVerilog uses about 100 predefined keywords. All

the keywords are represented in colored font (either green, blue or red). if it is not shown in a colored font it means there must be some typing error.

All the verilog statements are terminated with a semicolon(;) except for the statements (keywords) like initial, begin, always, if, for, while etc…

Verilog is case sensitive i.e. the keywords are written in lower case.

Continued……Most common keywords are

module, endmoduleinput, outputwire, reg$display, $print, $monitoralways, for, while, ifinitial, beginand, or, not, xor, xnor, nard, norposedge , negedge, clock, reset, case$vw_dumpvars, $stop, $finish

Single line comment is given by // ( two consecutive slash)

and multi-line comment is given by /*……… */ for e.g // This is the first session of verilog /* this is the first

session of verilog*/