Design and Implementation of FPGA Based Low Power Pipelined 64 Bit Risc Processor for Data Logging...

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

159 NITTTR, Chandigarh EDIT-2015

Design and Implementation of FPGA BasedLow Power Pipelined 64 Bit Risc Processor for

Data Logging SystemUdit Singh Thakur[1], D. S Ajnar[2], P. K. Jain[3]

MicroElectronics & VLSI Design, Electronics & Instrumentation DepartmentS.G.S.I.T.S. Indore (M.P.), India

uditsingh17@gmail.com[1], ajnards@gmail.com[2], prjain@sgsits.ac.in[3]

Abstract: This paper presents an efficient design andimplementation of a 64 bit RISC Processor for Data LoggingSystem. RISC is a design mechanism to reduce the amount ofspace, time, cost, power and heat etc. reduces the complexityof instruction. The processor is designed for both fixed andfloating point number arithmetic calculation. A Data Loggeris an electronic instrument that records environmentalparameters such as temperature, Humidity, Wind Speed lightintensity, water level and water quality. Data Loggers find itskey application where automation and control is required.The necessary code written in the hardware descriptionlanguage Verilog HDL.

Keywords: 64-bit RISC Processor, Data Logger

I. INTRODUCTIONIn conventional approach the system consumes too muchof power. The power reduction in conventional RISCprocessor is done at fabrication step itself, but which is toocomplex process. Here the utilization of chip area is moreand the system consumes more power which leads toincreased performance. To overcome this disadvantage,low power RISC Architecture is designed with less numberof Gates. Low power design means reducing the powerconsumption. Low power consumption helps to reduce theheat dissipation, increased battery life and more devicereliability. This technology strongly affects battery size,design, electronic packaging of ICs, heat dissipation andcircuit reliability. Low power embedded processors areused in a wide variety of applications including cars,mobile phones, digital cameras, printers and other devices.Low power has emerged as a principle theme in today’selectronics industry. The need for low power has caused amajor paradigm shift where power dissipation has becomean important consideration as performance and area. RISCis termed as Reduced Instruction Set Computer [1].

In this paper a low power 64 bit RISC processor for datalogger has been proposed. This RISC Processor tracks thecontrolled process at regular interval of time and takes thesample data such as conveyor belt speed and direction,temperature, Pressure, water level. Upon the comparison ofthe sampled data with standard data, Data Logger issuescorresponding signal to the mail computer to takenecessary steps such as, if the temperature is higher thanthe allowed value than then it issues signal to main CPUsuch as to take necessary steps to reduce the temperature.Data logger remains ideal if all the parameters or thesampled data is in specified range of operation. Its mainworking contains 4 steps namely Fetch, Decode, Execute,Store.

II. ARCHITECTURE OF THE DESIGNThe 64bit RISC Processor designed has the architecture inwhich the separate access ports are provided for Data andInstruction. This RISC processor has a central control unitthat controls all the operation execution in different unitssuch as comparator, ALU, clock generator. It has apipelined structure that continuously waits for nextinstruction as soon as the previous instruction executed thenext instruction in fetched from register and the processingfor next instruction starts accordingly.

All basic operation such as arithmetic addition, subtraction,division, multiplication and logical operations like AND,OR, NOT, are being performed by ALU. Shifter is used toshift numbers bitwise to the left and right. Comparator isused to compare two 64 bit numbers. Resistors are beingused to store values as well as the next instruction.

A separate execution unit for comparison shifting is usedto reduce the overhead of ALU which eventually leads tothe reduction of complexity and the execution time. WhileALU is performing its operation meanwhile comparatorand shifter is also performing their operation whichreduces the execution time and increases the overall speedand performance. Block diagram of 64 bit RISC processoris been shown in figure 1.

With this RISC processor while one instruction is executednext instruction is fetched and decoded and is maintainedinto a queue for next instruction. This type of branchprediction reduces the wastage of time [1].

In this paper, a 64 bit RISC processor with classifiedfunctionality of each block is designed with as architecturethat is useful for data logging facility. This RISC processoris been designed keeping in mind about its specificoperations where automation and control is required [2].

III. DESCRIPTION OF LOGIC BLOCKS.The proposed RISC processor contains login block such ascontrol unit, register, ALU, comparator, shifter,temperature comparator, conveyor belt speed comparator,etc as shown in figure 2.

Control unit serves as the top level module that controlseverything that is been executed. It also works asinstruction decoder that initiates each logical block uponopcode occurrence. Registers are useful for storingincoming input, output as well as the opcode. The programcounter is been implemented in the instruction resistor.

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

NITTTR, Chandigarh EDIT -2015 160

Figure 1 Block diagram of RISC Processor[3]

ALU is used for the logical and arithmetic operations,shifter and comparator are used for shifting andcomparison respectively.

Figure 2 logical blocks of RISC Processor

Figure 3 Flow chart for conveyor belt speedComparator & temperature comparator

IV. SIMULATION RESULTFigure shows the simulation result obtained.

Figure 4 Simulation Result for Control Unit

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

161 NITTTR, Chandigarh EDIT-2015

Figure 5 Simulation Result for DataLogger

V. CONCLUSIONA 64 bit RISC processor with 14 instruction set is beendesigned. Design is verified using exhaustive simulation.This RISC processor has reserved opcode set for otherapplication implementation in future as well. This RISCprocessor is also useful in ATM, Printers, gaming Kits,etc.

REFERENCES[1] Jinde Vijay Kumar, Boya Nagaraju, Chinthakunta Swapna and

Thogata Ramanjappa, “Design and Development of FPGA BasedLow Power Pipelined 64-Bit RISC Processor with Double

Precision Floating Point Unit”. International Conference onCommunication and Signal Processing, pp 1054-1058, April 3-5,2014, India

[2] Seung Pyo Jung, Jingzhe Xu, Donghoon Lee, Ju Sung , Kang-jooKim, Koon-shik Cho ,“Design & Verification of 16 Bit RISCProcessor”, 2008 International SoC Design Conference, pp III.13-III.14.

[3] Rohit Sharma, Vivek Kumar Sehgal, Nitin Nitin1, Pranav Bhasker,Ishita Verma, “Design and Implementation of a 64-bit RISCProcessor using VHDL”, UKSim 2009: 11th InternationalConference on Computer Modelling and Simulation, pp 568-573.