Day1 02.Introduction

Introduction

IntroductionIntroduction

Brief history of modern electronic design

IBMPC

IBMPCAT

AppleII

History: x86 History: x86 and ..... and .....

Altera'83

Xilinx'84

TTL'60

MOSCMOS

tsmc

PALMMI'78

10B

1B

100M

10M

IC

'65Moore's Law

Moore's LawMoore's Law

1965:a doubling every 12 months

1975:the future rate of increase in a complexity to doubling every two years

Evolution of PC motherEvolution of PC mother--boardboard

286(MCU+TTL or PAL)

today(MCU+N+S)

A Motorola 68000-based comA Motorola 68000-based com--puter with various TTL chipsputer with various TTL chips

A real-time clock built of A real-time clock built of TTL chips designed about TTL chips designed about 1979.1979.

Logic FamilyLogic Family

Logic IC Technology Life Cycle: Logic IC Technology Life Cycle: ti/2007ti/2007

PAL(Programmable Array LoPAL(Programmable Array Lo--gic)gic)MMI, 1978

AMD, 1983

GAL, Lattice, 1985

ComplexLogic

CPLD

SOPCSystem Logic

Simple Control Logic

SPLD

History of PLD: AlteraHistory of PLD: Altera

84 85 87 88 9386 89 90 91 92 94 95 96 97 98 99 00 01 02 0383

First PLD

TTL LIBEP1200

EPB1400

FLEX 10KIP Library

FLEX 10KAFLEX10KEMAX 7000A

StratixTransceivers

Cyclone

ALTRIPO

MercuryARMNios

MAX+PLUS IIMAX 7000

AHDL

0.5

1.0

1.5

2.0

2.5

3.0

CMOS PLD$B

7032VMAX 9000

FLEX 8000ACCESS EDA

APEX

Application :Application :World of Digital and AnaWorld of Digital and Ana--loglog Computation,

control, communication

● Analog: continuous timetemperature, pres-sureWhy Digital?

● Digital: discrete timeex, word:8/16/32/64-bits

Motor Motor Control: Control: titi

Motion Control: AlteraMotion Control: Altera

Motion Control: AlteraMotion Control: Altera

IntroductionIntroduction

What kind of Problems to be solved by logic design

What kinds of problemWhat kinds of problem

● Digital Only: two Value, Binary, 1/0 ●

● Control● Communication● Computation●

Example: Detector and Example: Detector and controlcontrol

Event:True (T) ONFalse(F) OFF

Voltage:High (H) 1Low(L) 0

Sensor Input:T, PressureIf (A OR B OR C) then

ALARMelse

If (T > 80) thenALARM

else

Example: SequenceExample: Sequence

Off

Running

StartOff

Start

Starting up your CarMotor controlWashing MachineMenu of Cellar Phone

Off

Solution to Logic Design: Why Solution to Logic Design: Why PLDPLD

● HW● Full Custom● ASIC(std Cell)● Discrete: TTL, .....● CPLD● FPGA

● SW/FW●

● Mixed HW/SW● uC

●

● Consideration● Performance● Cost● Schedule●

0.35 µ0.25 µ0.18 µ0.15 µ0.13 µ0.09 µ

Technology

0.35 µ0.25 µ0.18 µ0.15 µ0.13 µ0.09 µ

Technology

RTL Gates Qtr./Person

Verification Qtr./Person

Synthesis + P&RQtr./Person

EngineeringMan Years

30K36K50K75K

110K150K

15K18K25K38K55K

75K

125K300K500K750K

1.0M 1.25M

14303841

46 52

Engineering Costs ($Ms) Masks & Wafers ($)

25

6.47.38.8

10.4

80K160K400K600K900K

1.3M

Rising Cost of Development

General Development General Development CycleCycle

How we designHow we design

PhysicalBlock CellWire

Structuralmodule, symbolSchematic: lines, name

FunctionalmodulenameLanguage: HDL

Level of Abstraction

Behavior, system

IntroductionIntroduction

Review of Binary Number & Boolean Algebra

Binary Number SystemBinary Number System

LSB: least significant bitMSB: Most significant bit

How many bits are suffiHow many bits are suffi--centcent

● Given N, the minimum integer k, ● N=10, k=4● E-ASCII Code, k=8● { high, medium, low}, k=2● 3 digital: 0 ~ 100 , k=7℃ ℃

2kN

● K=8, N= 0 ~ 255● K=10, N=0 ~ 1023 1K● K=16, N=0 ~ 65,535 64K● K=32, N=0 ~ 4,294,967,295 4KKK = 4G

● Telephone: 8bits● CD : 16bits

Binary and Decimal ConBinary and Decimal Con--versionversion

Binary to Decimal

Decimal to Binary

Binary Addition and SubBinary Addition and Sub--tractiontraction

● 0 + 0 → 0● 0 + 1 → 1● 1 + 0 → 1● 1 + 1 → 0,

carry 1 (1+1 → 10)

1 1 1 1 1 (carried digits) 0 1 1 0 1 0Dh 13+ 1 0 1 1 1 17h 23---------------------------------------=1 0 0 1 0 0 24h 36

● 0 0 → 0−● 0 1 → 1, −

borrow 1● 1 0 → 1−● 1 1 → 0 −

(starred columns are borrowed from) * * * * 1 1 0 1 1 1 0 6Eh 110− 1 0 1 1 1 17h 23------------------------------------------=1 0 1 0 1 1 1 57h 87

2's Complement(1)2's Complement(1)

● 10's complement of 95 = 10^2 – 95 =5● 9's complement of 95 = 99 – 95 =

4● CM(10's) = CM(9's) + 1 ● 2's complement 0001 = 2^4 – 0001 =

1111● 1's complement 0001 = 2^4 – 1 – 0001

= 1110 An N-bit two's-complement numeral system can represent every integer in the range −2^(N-1) to +2^(N-1)-1.4bit: -2^(3)= -8 to +2^3-1 = +78bit: -128 to +127

In this way, we only need ADDERBut how it works??

2's Complement(2)2's Complement(2)

● A - B = A + (not B + 1) // ( ) :2's comple-ment

2's complement(3)2's complement(3)

● Overflow

What is Logic: Boolean alWhat is Logic: Boolean al--gebra gebra

● a logical calculus of truth values, developed by George Boole(1815~1864, English).

● Algebra of two values. These are usu-ally taken to be 0 and 1, false and true, low and high

NOT: ¬A, ~A, !A If A = 0 then !A = 1 and if A = 1 then !A= 0

AND: A︿ B, A*B, AB A product term is 1 only when all terms are a 1

OR: A﹀ B, A+B A product term is 1 only when any terms is a 1

Law of Bolean AlgebraLaw of Bolean Algebra

● commutativity 交換律A+B = B+A, A*B = B*A

● Associativity 結合律A+(B+C) = (A+B)+C, A*(B*C) = (A*B)*C

● Distributive 分配律A*(B+C) = A*B+A*C

Bolean Algebra: basic rulesBolean Algebra: basic rules

1. A + 0 = A2. A + 1 = 13. A*0 = 04. A*1 = A5. A + A = A6. A + !A = 17. A*A = A8. A*(!A)= 09. !(!A)= A

10. A + A*B = A = A*(1 + B) where (1+B) according to Rule 2 is equal to 1 = A11. A*(A+B) = A =A*A + A*B Distributive Law =A+A*B Rule 7 =A Rule 1012. A + !A*B = A + B = A*(B+1) + !A*B according to Rule 2 (B+1) = 1 = A*B +A + !A*B = B*(A + !A ) + A according to Rule 6 A + ~A = 1 = B + A13. (A+B)*(A+C) = A+B*C = A*A+A*C+A*B+B*C applying the Distributive Law = A*(1+C+B) +B*C according to Rule 2 (1+B+C) = 1 = A+B*C

Bolean Algebra: De Morgan's Bolean Algebra: De Morgan's lawslaws

● De Morgan's laws, !(A*B) = !A + !B , !(A+B) = !A * !B

● Example![(A+ B*C)*(A*C+ B)]= ![(A+B*C)] + ![(A*C+B)]= [!A]*[!(B*C)] + ![A*C] * [!B]= !A *[!B + !C] + [!A + !C] * [!B]= !A* !B + !A*!C + !A*!B + !C*!B= !A* !B + !A*!C + !B*!C

Bolean Algebra: SwitchBolean Algebra: Switch

LED = X*Y

LED = X + Y

Boolean Algebra: Boolean Algebra: Gate Symbol, Truth Table(1)Gate Symbol, Truth Table(1)

AND OR NOT

Boolean Algebra: Boolean Algebra: Gate Symbol, Truth Gate Symbol, Truth Table(2)Table(2)

NAND NORXOR XNOR

NAND implemented by NAND implemented by NORNOR

NOR implemented by NOR implemented by NANDNAND

NAND: an fan failure deNAND: an fan failure de--tectortector

ALARM

0: Fail1: Ok

Positive LogicNegative Logic

NOR: an detecor in WashNOR: an detecor in Wash--ing Machineing Machine

1: Lid open

1: < min water level

1: > max weight

Normal

OFF

SOP(sum of product)SOP(sum of product)POS(product of sum)POS(product of sum)

SOPTo derive the Sum of Products form from a truth table, OR together all of the minterms which give a value of 1.

POSTo derive the Product of Sums form from a truth table, AND together all of the maxterms which give a value of 0.

Any boolean expression may be expressed in terms of either minterms or maxterms.

Will we start design now ?Will we start design now ?

● With knowledge up to now, we can start to design 『 combinational』 logic circuit such as Decoder, Adder,,,, etc, whenever we have a 『 spec』 or 『 truth table』 derived from the problem re-quirement.

● Traditionally, Karnaugh Map & Boolean Expres-sion Simplification technics will be introduced for design optimization.

● But.....we will skip this portion since we are using HDL and FPGA/CPLD other than TTL or ASIC.

● Let's see “why” later.

IntroductionIntroduction

Evolution of Programmable Logic device

From TTL to CPLD, FPGA

TTL DesignTTL Design

PROM: PROM: combinational logic implemenacombinational logic implemena--tiontion

PLAPLA((Programmable Logic ArProgrammable Logic Ar--ray)ray)

PALPAL((Programmable Array LoProgrammable Array Lo--gic)gic)

fixed-OR, programmable-ANDSOP

SecurityFlexibilityTools: HDL – ABEL,CUPL, PALASM

"one-time programmable" (OTP)

SOP

GAL(Generic Array Logic)GAL(Generic Array Logic)22V1022V10

EEPROM

GALGALOLMCOLMC((OUTPUT LOGIC MACROCELL)OUTPUT LOGIC MACROCELL)

Output SelectInput/Feedback Select

CPLDCPLD

Global Routing, more control on IO

Altera, MAX 3000AAltera, MAX 3000A

MAX 3000 MacroCellMAX 3000 MacroCell

FPGAFPGA

FPGAFPGALELE

MAX II and Cyclone FamilyMAX II and Cyclone Family

MAX CPLD FamilyMAX CPLD Family

MAX IIMAX IILELE

MAX IIMAX IILABLAB

MAX IIMAX IIDevice Floor PlanDevice Floor Plan

CFM: Configuration Flash MemoryUFM: User Flash Memory

MAX IIMAX IIGlobal Signal: Clock, or conGlobal Signal: Clock, or con--troltrolIO PINS

Generated Internally

Design Style

MAX IIMAX II

FPGA CPLD Comparison FPGA CPLD Comparison

Fine-Grain, Gate-array Like

LE, LUTGrid ArrayLAB Local and row/col

SRAM-basedrequire programming

Very Large designdependentlarge memoryHigh powerDSP, TRCVR

Coarse-Grain, PAL likeLAB

LAB around Global ConnectLAB Local and Global

(E)EPROM-basedinstant-on

Medium to smallFast, predictableNo memoryLess powerNA

FGPA CPLD

Arch

LayoutInterconn

Conf

ScaletimingmemoryPowermisc

ApplicationApplication

IntroductionIntroduction

FPGA/CPLD Design Environment & Flow

Generic introduction and RTL simu-lation

Typical Design FlowTypical Design Flow

Typical Design FlowTypical Design Flow

Design Flow Design Flow ModelSimModelSim

Programming

Quartus: Design EntryQuartus: Design Entry

IntroductionIntroduction

What is Verilog HDL, take a tour of 1 st tutorial example logic simulation

What is HDLWhat is HDL

A Hardware Description Language (HDL) is a high-level programming language that offers special constructs with which you can model microelectronic circuits.

These special language constructs permit you to: Describe the operation of a circuit at various levels of abstraction, behavior, function, structure, timing of a circuit.

Language for the concurrency of hardware, not a software language

timingSynthesis: mapping to physical

Why HDLWhy HDL

● Top-down design methodology using synthes-is

● Implementation/technology highly independ-ent

● Quickly/easily explore design alternatives● Architectural problems● Re-use● Design productivity● Take advantage of mature software design

practices

Verilog HistoryVerilog History

● 1980’s Gateway Design Automation developed Veri-log

● 1990 Cadence acquired Gateway● 1991 Cadence released Verilog to the public do-

main.● 1995 IEEE ratified the Verilog LRM

(IEEE Std. 1364-1995)● 2001 IEEE updated the Verilog LRM● System Verilog

We will use

Verilog UsageVerilog Usage

● System architects: system level Simulations

● ASIC and FPGA designers: RTL code for synthesis

● Verification engineers:tests for all level of simulation

● Model developers:component behavior, ex DRAM

SystemVerilog

IntroductionIntroduction

Lab1: your 1st Verilog 『 Program』

What we did in Lab1What we did in Lab1

Modelcounter,v

Test Benchtcounter.v

SimulatorModelSim

Waveform Text Output

tcounter.vtcounter.v

module test_counter;reg clk, reset;wire [7:0] count;

counter dut (count, clk, reset);

initial // Clock generator begin clk = 0; forever #10 clk = !clk; end

initial // Test stimulus begin reset = 0; #5 reset = 1; $display("hello"); #4 reset = 0; end initial $monitor($stime,, reset,, clk,,, count);

endmodule

counter.vcounter.v

module counter (count, clk, reset);output [7:0] count;input clk, reset;

reg [7:0] count;

always @ (posedge clk or posedge reset)

if (reset) count = 8'h00; else count <= count + 8'h01;

endmodule

module and module portdeclaration: output, input, inout

reg data type register

Verilog ModuleVerilog Module

dut

test_counter

counter

Stimulus and control

clkreset

count[7:0]Response

monitorverification

TOP DOWN Design HierTOP DOWN Design Hier--archyarchy

ModuleModule

Module portModule port

Module InstanceModule Instance

Test BenchTest Bench

Procedure BlocksProcedure Blocks

Applying stimulusApplying stimulus

initial // Clock generator begin clk = 0; forever #10 clk = !clk; end

initial // Test stimulus begin reset = 0; #5 reset = 1; #4 reset = 0; end

Time clk reset0 0 05 0 19 0 010 1 020 0 030 1 0...........................

What is time unit ?

Checking the ResponseChecking the Response

Example:$monitor($time, o, in1, in2);$monitor($time,, out,, a,, b,, sel);$monitor($time,, ”%b %h %d %o”, sig1, sig2, sig3,

sig4);

Syntax: C-Like$monitor ([”format_specifiers”,] arguments);

Behavior ModelingBehavior Modeling

Describes a system by the flow of data between its functional blocks, or algorithm

Defines signal values when they change

a=b*c

wait a;

RTL ModelingRTL Modeling

Describes a system by the flow of data and control signals between and within its functional blocks

Defines signal values with respect to a clock

Structure ModelingStructure Modeling

Describes a system by connecting predefined componentsUses technology-specific, low-level components when mapping from an RTL description to a gate-level netlist, such as during synthesis

RTL SynthesisRTL Synthesis

Why we skip Logic OptimWhy we skip Logic Optim--izationization

● HDL● FPGA/CPLD vs TTL, ASIC Cell●

●

● Let Machine do what it excels● You give direction.

You have to know what you really want.Speed, Area, Power

●

● Design Scale Dependent.

SummarySummary

● Brief History● Review of Number system and Boolean Al-

gebra ● Basic concept of CPLD/FPGA ● HDL Tour: ● modules; ports, instances● Test Bench● Stimulus● Response