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eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
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eInfochips Spec to Silicon Services
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Product Engineering Services Company
Bangalore ChennaiPune
AhmedabadNoida
Toronto LondonBostonChicago
DallasAustin
Cedar Rapids
CincinnatiRaleigh
Sunnyvale
10 Design Centers
12 Sales Offices
1200Professionals
19 YearsSolid Track Record
Stable & SecureCash Positive, Debt-free and Profitable
Semiconductor Journey
• 10+ Dedicated Design Center• 5 Design IPs• Intel Strategic Partnership
2002-05 2008 2011 2013
• 8 Dedicated Design Center• 3 Design IPs, 3 VIPs• Synopsys Partnership
• A stepping stone in VIP area• Cadence Partnership
Launched 7 eVCs
OfferingsASIC/FPGA Verification
OfferingsASIC/SoC/FPGA DesignASIC/FPGA Verification
OfferingsPhysical DesignASIC/SoC/FPGA DesignASIC/FPGA Verification
OfferingsDesign for TestabilityPhysical DesignASIC/SoC/FPGA DesignASIC/FPGA Verification
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• Talent ecosystem
250150
50
400
Turnkey Silicon Offerings
Concept - Specification
Design - RTL Design- Simulation- IP Integration
Architecture – Design
Verification - Functional
Verification- Verification IP
Development
Synthesis - Netlist
Physical Design- RTL to GDSII- DFT Services- Layout
Migration
GDSII
Silicon Validation- ASIC Prototyping- Chip Bring Up - Silicon Turn-on
Spec
To
Silicon
Services
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Tools Expertise
ASIC Design
•QuestaSim•Modelsim•VCS•Design & DFT Compiler•PT
FPGA Design
•Synplify-Pro•Xilinx-ISE •Altera-QuartusII•Actel-Libero•ChipScope•SignalTapII•Leonardo Spectrum•PCie Analyzer•Logic Analyzer•O-Scope•CHIPit-PlatinumV4•HAPS Board•Palladium, EVE
Verification
• IUS•NC-Sim•Conformal•Questasim•Modelsim•Formality•FinSim, VeriLint•exploreRTL, LEDA•Verix, SureCov•CoverMeter•HDLScore•NextGen MVRC• IUS LP, CLP LEC
Implementation
•Magma Talus•Blast & Quartz•Synopsys DC• ICC, Astro•PrimeTime, PTSI•TetraMAX•StarRC XT•MG Calibre•SoC Encounter•Celtic, Nanoroute•Virtuoso, Conformal LEC
VertexSpartan
Kintex
CycloneFlexNios
A3P Series
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eInfochips Turnkey LabDesign • 20M Gate Count• 37 Clock Domain; up to 500MHzVerification • 180M Gate Count SoC • 14 VIPsPhysical Design
• 85+ Tape-outs: 130nm– 16nm • 230M Gate Count Silicon Validation• 15+ Pre-silicon FPGA Prototypes• 11 Evaluation Modules
Design • DC Ultra, Design Vision, HDLPhysical Design • StarRC, IC Validator & Compiler• PrimeRail, PrimeTime SI Design For Testability
• DFTMAX, DFT Compiler• TetraMAXVerification • Formality, VCS-MX
• Mature processes evolved over two decades of delivery excellence Comprehensive internal checklists for guaranteed first-pass silicon success
• Dedicated Project Management Office for Silicon Design Engineering team
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Physical Design Services. Services• RTL Synthesis• DFT, ATPG & Fault grading services • Hierarchical Floor planning and Partitioning • Multi-power island designs, power analysis (low power
design)• Place & Route• Customized Clock Tree Synthesis• Signal Integrity Analysis• Physical Verification & DFM• Post-Layout ATPG Simulation• Chip / ASIC Layout Migration• ECO Implementation for functional & timing fixes
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Domain Expertise• Networking & Communication• Wired, Wireless
• Multimedia / Consumer Electronics• High End Processors (GPU, APU, Multi CPU ASICs)• Automotive
eInfochips’ Physical Design Differentiators
Outcome :1. 85+% Area Utilization, 95+% High VT Cells on wireless SoC 2. Timing closure on 150 Mn gate count ASIC on rectilinear Floorplan3. High performance design timing closure with < 1% of LVT cells ensuring power requirements on Networking SoC 4. Low power designs with multiple voltage domains on Tablet SoC
Complete Turnkey Ownership : 85+Silicon Tape-outs across 180 to 16nmComprehensive checklist to ensure first time right silicon: Netlist to GDSII in < 3 iterationsTechnical Expertise :
• Expertise in physical design flow & methodologies using EDA tools from all four major vendors (Synopsys, Magma, Cadence, Mentor Graphics) helps in achieving good results irrespective of tools.
• Experience in tape-outs to foundries like TSMC, UMC, GF, Toshiba, TI and CHARTERED • Dedicated Subject Matter Experts (SME) for each stage of Physical design, Different Methodology (Flow), Tools• Advanced Interface expertise: SerDes, MIPI, PCIe3, DDR, High Speed CPUs• Combination of Die Size Reduction and Clock Speed Improvement cost of derivative SoCs
Domain Expertise : Projects across Networking, CE, Telecom, Mobile for Area, Power & Time optimization for domain specific require.
Unique training program includes basic and advanced Physical design practices and how each Physical Design activity impacts Quality, Product schedule, Time to Market and Business.
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DFT Expertise and Service OfferingsInitial Phases
• DFT Evaluation and Assessment
• DFT Architecture and Methodology Development
• DFT Automation• Design vs Test Time & DFT
Trade-offs• ATPG Library Generation
Expertise
• 20+ tapeouts and Silicon turn-on
• Signoff with various EDA tools• 28nm,40nm, 45nm, 90nm,
130nm technologies• Multiple Clock Domains• On-chip IP DFT Analog blocks• Makefile and Tcl based flow
development
Implementation
• Scan Insertion• Adaptive/Compressed scan logic• Add/Optimize Test Control Logic• ATPG - Vector Generation and GLS• Memory BIST• JTAG Insertion compliant to both
IEEE1149.1 and IEEE1149.6 standards
• Fault Simulation and Grading• Silicon turn-on• Manufacturing Test Program Debug
assistance• Failure Analysis assistance
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eInfochips’ DFT Differentiators • Flexible DFT engagement model starts from DFT Architecture to Silicon Turn-on• 20+ successful Silicon tape-outs and Silicon Turn-on• Subject Matter Experts for Scan, MemBIST, JTAG, ATPG, Equivalence check,
Silicon Turn-on and failure diagnoses• Comprehensive and well documented checklist to ensure first time right silicon
with maximum test coverage• Unique training program includes how DFT activity impacts Profitability, Cost
for the Test and Time to Market• Expertise in DFT flow & methodologies using EDA tools from all three major
vendors (Synopsys, Cadence and Mentor Graphics)• Experience in tape-outs to foundries like TSMC, UMC, TI & TOSHIBA
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Thank you
For more information, write us at marketing@einfochips.com
or visit www.einfochips.com
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