Lecture16

S. Reda EN160 SP’08

Design and Implementation of VLSI Systems(EN1600)

Lecture 16: Interconnects & Wire Engineering


Interconnects introduce cross talk

• A capacitor does not like to change its voltage instantaneously.

• A wire has high capacitance to its neighbor.– When the neighbor switches from 1→ 0 or 0 → 1, the wire

tends to switch too.– Called capacitive coupling or crosstalk.

• Crosstalk has two harmful effects:1. Increased delay on switching wires

2. Noise on nonswitching wires


1. Crosstalk impacts delay

• Assume layers above and below on average are quiet– Second terminal of capacitor can be ignored– Model as Cgnd = Ctop + Cbot

• Effective Cadj depends on behavior of neighbors– Miller effect

A BCadjCgnd Cgnd


2.Crosstalk also creates noise

• Crosstalk causes noise on nonswitching wires• If victim is floating:

– model as capacitive voltage divider

Cadj

Cgnd-v

Aggressor

Victim

Vaggressor

Vvictim

adjvictim aggressor

gnd v adj

CV V

C C


Crosstalk noise effects

• Usually victim is driven by a gate that fights noise– Noise depends on relative resistances– Victim driver is in linear region, agg. in saturation– If sizes are same, aggressor = 2-4 x Rvictim

1

1adj

victim aggressorgnd v adj

CV V

C C k

aggressor gnd a adjaggressor

victim victim gnd v adj

R C Ck

R C C

Cadj

Cgnd-v

Aggressor

Victim

Vaggressor

Vvictim

Raggressor

Rvictim

Cgnd-a

(time constant depends on the ratio of time constant of aggressor and victim)


Simulating noise induced by couplingAggressor

Victim (undriven): 50%

Victim (half size driver): 16%

Victim (equal size driver): 8%

Victim (double size driver): 4%

t (ps)

0 200 400 600 800 1000 1200 1400 1800 2000

0

0.3

0.6

0.9

1.2

1.5

1.8

• Noise is less than the noise margin → nothing happens• Static CMOS logic will eventually settle to correct output even if

disturbed by large noise spikes• But glitches cause extra delay and power

• Large driver oppose the coupling sooner → smaller noise• Memories are more sensitive


Wire Engineering

• Goal: achieve delay, area, power goals with acceptable noise

• Possible solutions:1. Width, Spacing, Layer

2. Shielding

3. Repeater insertion

4. Wire staggering and differential signaling

vdd a0a1gnd a2vdd b0 a1 a2 b2vdd a0 a1 gnd a2 a3 vdd gnd a0 b1


1/2. Width, Spacing, Layer, Shielding

vdd a0a1gnd a2vdd b0 a1 a2 b2vdd a0 a1 gnd a2 a3 vdd gnd a0 b1

• Widening a wire reduces resistance but increases capacitance (but less proportionally) → RC delay product improves

• Spacing reduces capacitance → improves RC delay• Layers

• Coupling can be avoided if adjacent lines do not switch → shield critical nets with power or ground wires on one or both sides to eliminate coupling


3. Repeater insertion

• R and C are proportional to l• RC delay is proportional to l2

– Unacceptably great for long wires

• Break long wires into N shorter segments– Drive each one with a repeater or buffer

source sink

buffer/repeater

Two questions:

A. What is the position that minimizes the delay?B. How many repeaters to insert to minimize the delay?


What is the delay from source to sink without any repeaters?

source sinkL


A. If you have one repeater, where is the optimal position to insert it?

source sink

x

L

buffer

Minimum delay is attained when

Makes sense to add a buffer only if D0-D1 > 0


A. If there are multiple buffers, where are the optimal locations to insert them?

source sink

L/2

L

If Rbuf = Rsnk and Csnk = Cbuf

then the optimal location for the buffer is at distance L/2

If there are N buffers then minimum delay will occur when they are equally spaced, i.e., separation distance is L/(N+1)

L/2


B. What is the optimal number N of repeaters?

source buffer


4. Staggering and differential signaling

staggering

differential signaling

Business

Lecture16