MIS Diode (MOS capacitor) – Ideal

EC

EF

EV

Ei

Ideal MIS Diode n-type, Vappl=0

Assume Flat-band at equilibrium

qS

ECE 663

Ideal MIS Diode p-type, Vappl=0

ECE 663

Band bending due to work function difference

msFBV

ECE 663

Accumulation

Pulling in majority carriers at surface

ECE 663

Depletion

ECE 663

Need CB to dip below EF. Once below by B, minority carrier density trumps the intrinsic density. Once below by 2B, it trumps the major carrier density (doping) !

Inversion

B

Some important equations in the inversion regime (Depth direction)

VT = ms + 2B + ox

Wdm = [2S(2B)/qNA]

Qinv = Cox(VG - VT)

ox = Qs/Cox

Qs = qNAWdm

VT = ms + 2B + ([4SBqNA] - Qf + Qm + Qot)/Cox

Substrate

Channel Drain

InsulatorGate

Source

x

ECE 663

P-type semiconductor Vappl0

Convention for p-type: positive if bands bend down

ECE 663

Substrate

Drain

InsulatorGate

Source Channel

Substrate

InsulatorGate

Channel

MOScap MOSFET

Operation of a transistorVSG > 0 n type operation

Positive gate bias attracts electrons into channelChannel now becomes more conductive

Substrate

Channel Drain

InsulatorGate

Source

VSD

VSG

Substrate

Channel Drain

InsulatorGate

Operation of a transistor

Transistor turns on at high gate voltageTransistor current saturates at high drain bias

Source

VSD

VSG

Saturation Regionoccurs at large VDS

pn+n+

metal

sourceS

gateG

drainD

bodyB

oxide

+-

+++

++++++

VDS large

As the drain voltage increases, the difference in voltage between the drain and the gate becomes smaller. At some point, the difference is too small to maintain the channel near the drain pinch-off

Simplified MOSFET I-V EquationsCut-off: VGS< VT

ID = IS = 0

Active: VGS>VT and VDS < VGS-VT

ID = kn’(W/L)[(VGS-VT)VDS - 1/2VDS

2]

Saturation: VGS>VT and VDS > VGS-VT

ID = 1/2kn’(W/L)(VGS-VT)2