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These slides use concepts (e.g., scaling) from my (Jeff Funk) course entitled analyzing hi-tech opportunities to look at how reductions in the feature sizes for integrated circuits (ICs) are enabling increases in the functionality of IC chips and thus the placements of larger systems on them. In turn, these increases in functionality of ICs are enabling increases in the functionality of mobile phones while at the same time creating new challenges for IC and mobile phone suppliers.
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System On Chip
(for mobile devices)
Jason Koh Sheng Fa (A0082016R)
Adrian Kong Yeng Hong
(A0082260N)
Heng Sin Wei (A0082006U)
Goh Chee Peng (A0077117E)
Chris Liu Chaofeng (A0082015U)
Scope
A way of life, in mobile devices
Requirements of a Smart phone and Tablet for the savvy user
Games, music, video • intense graphics and sound • Powerful processing
Internet surfing/email • Good aspect ratio for a mobile device.
• (gyro, capacitive touch for zooming)
• Wifi, 3g, 4g capability.
GPS • Requires GPS chip and Compass.
Cameras and Video cam • Good image processing module
Mobile health monitoring • Requires bio electronics IC
General • Antenna • Power control
Early mobile phones - Ericsson
DSP, Microprocessor and Memory are all integrated into a single SoC!
Smartphone - Galaxy
S 2
SoC
Future!!
!
But how do we integrate all requirements?
Moore’s Law
More than just transistors?
Scope
What is System on Chip (SoC)? • A complex IC that integrates
the major functional elements into a single chip or chipset.
• programmable processor • on-chip memory • accelerating function
hardware • both hardware and
software • analog components • opto/microelectronic
mechanical system
• Benefits of SoC • Reduce overall system cost • Increase performance • Lower power consumption • Reduce size
Technology Paradigm
Technology Basic Paradigm Basic Method of
Improvements within Technology Paradigm
Chips on Board (COB)
Mounting of IC chips directly on PCBs
Substituting different materials to reducing interconnect delays
System in Package (SIP)
Stacked chips or packages for
reduced form factor
Improving performance and power efficiency by short direct connection
channels
System on Chip (SOC)
Complete system on a chip
Reducing form factor, power consumption, heat dissipation, analog mixed
signal integration
Comparison of COB, SIP & SOC
COB SIP SOC
Performance
(Speed, Power,
Frequency) W M B
Form Factor W M B
Signal process
packing density W M B
Cost in volume W M B
Thermal
dissipation B W M
Functionality W M B
Why SoC?
• Based on the comparison above, SOC poses more potential
• However in certain cases, the IC industry may leverage on both technology to advance.
• Our team felt that although currently both tech are complementing each other but SOC will be the ultimate goal!
•Current Mobile SOCs
Texas
Instrument
OMAP series
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e
OMAP 1
OMAP 2
OMAP 3
OMAP 4
OMAP 5
Exynos 3110
Exynos 4210
Exynos 4412
Exynos 5250
Exynos 5450
Samsung
Exynos
S1
S2
S3
S4
S5
Qualcom
m
Snapdrago
n
NVIDIA
Tegra
Tegra APX
Tegra 2
Tegra 3
Scope
SoC Challenges
Transistor
Size
Transistor
Density
Process
Size
Performance
requirement
Power
issue Cost
Mixed
Signal
Complexity
• Endless Performance Requirement
• Multimedia: Many codecs for
image/audio/video
• Networking: Diverse and
complicated standards
• Wireless: Many new and
existing wireless standard
• Current processing performance is not able to meet current needs.
Current Limits of SoC -Performance
Required Processing Performance
Current Processing Performance
• With the processor speed remaining constant
• Smaller chip = Poorer power
eff.
• As the processor speed increases, power consumption increases at a higher rate
Current Limits of SoC -Power
Limited Battery Improvement
• Power Increase vs. Battery Improvement
Year 2001 2004 2007 2010 2013 2016
Feature Size(nm) 130 90 65 45 32 22
Dynamic Power Reduction(X) 0 1.5 2.5 4.0 7.0 20
Stand-by Power Reduction(X) 2 6 15 30 150 800
[ITRS 2001]
200
400
600
Vo
lum
etr
ic E
ne
rgy
De
ns
ity(W
hr/
L)
Gravimetric Energy Density(Whr/Kg)
100 200 300
Li-Ion / Polymer NI-MH
800
400 500 600 700 800 900
Fuel Cell
• Cellular Phone
Talk Time : 2Hrs ~ 4Hrs
Standby : about 1 week
• Cellular Phone
Talk Time : about 12Hrs
Standby : about 1 month Smaller
Lighter
Only 4~5 X improvement
In Battery lifetime!
- Cost
Higher NRE as Size decreases
Current Limits of SoC
- Cost
Software cost exceeds Hardware cost when size decreases
Current Limits of SoC
• Design considerations of analog devices differs from digital devices
• Process geometry size shrinks, analog gets bigger
• Need to be compensated for by increasing sizes of transistors,
capacitors and resistors used.
• Lower levels of predictability
• Parasitics capacitance and resistance less predictable
• Parasitics
• Noise issue
• Some Mixed Signals Challenges
Current Limits of SoC
At 28nm process technology, wafer costs are significantly higher than 65 nm. (~40% higher)
Unlike digital circuits, analog circuits do not scale in accordance to Moore’s law.
Eg: Scaling limitations of analog audio codec
1) Active amplifiers and resistive ladders
1) Reducing area of device negatively impacts the device
matching characteristics
2) Data converters
1) Noise level in switched capacitor circuits is inversely
proportional to the capacitance.
2) Supply voltage drop as process becomes smaller.
• In order to maintain dynamic range, area and capacitance need to increase
3) Output drivers
1) Size of output devices will not scale with process
technology
• Large output current must be delivered with low distortion.
• Mixed Signals
• Integrating audio codecs in SoC for smartphones and tablets
Current Limits of SoC
40%
20%
Scope
•Multi-Cores for improvements to
CPU performance
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Frequency
Single
Core
High Power Consumption
Heat Loss
High Leakage Current
Multi-Core
Less Power Consumption
Lesser Heat Loss
Lesser Leakage current
Hyper-Threading
•Hyper threading to process tasks in parallel •Easier to turn off entire CPU for power-savings •Switch between CPU for temperature management
Pushing the envelope of CPU Performance
CPU GPU
General processing Iterative processing of huge data
Few cores Hundreds of cores
Process a few threads Thousands of threads simultaneouly
Less Power efficient More power efficient
Lesser floating point cores More floating point cores
Lesser FLOPS MoreFLOPs
Difference between CPU/GPU
0
2
4
6
8
10
12
Omap 3 Omap 4 Omap 5
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)
TI Omap PowerVR GPU
TI Omap Power VR GPU
Improvements
0
0.5
1
1.5
2
2.5
3
3.5
Tegra 2 Tegra 3
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e(X
)
Nvidia UL Geforce GPU
Improvements
•Brand masters Improving GPU to achieve Graphic performance that might rival that of console games or PC
Graphics Processing Unit (GPU)
Smaller size More yield per wafer
Cheaper
Production
Costs
Flexibility of form factor
The size advantage
Most dominant Processor in Smartphone SoC (over 95% market share) – ARM
A need for efficient Power Management in SoC!!!
Power
System/Algorithm/Architecture
have a large potential!
De
sign
Time
SoC need faster Time to
Market
Power Saving vs Abstraction Layers
Main
CPU
(CPU A)
Secondary
CPU (CPU B)
Secondary CPU to handle all the “low-power” tasks like running the operating system in sleep mode,
checking emails and notification, and keeping the system alive when you are reading a book, playing media
files.
SoC
Using Secondary CPU
Asynchronous Symmetrical Multi-Processor system (aSMP)
Independent clock and voltage:
aSMP allows each CPU to run at the
appropriate frequency & voltage
depending on the workload executed
Power Saving via Architecture Design
Semiconductor Manufacturing Technology
Mobile SoC Brand Utilizing Smartphone Utilizing Tablets
Qualcomm Snapdragon S3
HTC
HTC Vivid
HTC Amaze 4G HTC Sensation
HTC EVO 3D HTC Rezound
HTC Rhyme
HTC Jetstream
LG
LG Nitro HD
LG Optimus LTE LU6200 LG Spectrum
Samsung
Samsung Galaxy S II
Samsung Galaxy S II LTE Samsung Galaxy S II Skyrocket
Samsung Galaxy Note Samsung Galaxy S Blaze 4G
Samsung Galaxy Tab 8.9
Asus Asus Eee Pad Memo
Sony Sony Xperia Ion
Sony Xperia S
Others
T-Mobile myTouch 4G Slide
Xiaomi MI-One ZTE Optik
Huawei Mediapad
Le Pan II Pantech Element
T-mobile Springboard Tablet
Toshiba Toshiba AT270
Economies of Scale
• Supply voltage restrictions on output driver performance
• At 28 nm process technology, most SoC will migrate to 1.8 V
I/O transistors.
• Will cause output voltage swing to drop to 0.54 Vrms which will limit
the performance of the headphone. (From 40mW to 12mW)
• Solution:
• Tap into 3.3V supply used for the USB interface.
• Generate 3.3V supply with a charge pump that takes the existing
1.8V supply and creates a negative 1.8V supply
Potential in Mixed Signals
• Moving analog functionality into digital domain
• To increase the percentage of circuitry that follows
Moore’s law and reduce the percentage of
circuitry that has limited scaling.
• Moving signal controls like volume, mixing and switching to
the digital domain.
• Digital-centric architectures where signal processing
is executed in digital blocks.
Potential in Mixed Signals
Scope
Market segment due to SoC
• Semiconductor Industry
• Software industry
• Consumer products
Future of SoC
Future of SoC
