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In the name of him
Microsemi IGLOO®2 FPGAs Best in Class for Cost Optimized FPGA Applications
Author: Samira Riki
Instructor: Dr.Hosseini Nezhad
Khajeh Nasir Toosi University Of Technology
Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Low Static and Dynamic Power
• Power as low as 13 mW/Gbps per lane for SERDES devices
• Up to 25% lower total power than competing devices
High Capacity
• 15K to 1 Million System Gates
• Up to 144 Kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Best-In-Class Integration
• Highest number of 5G transceivers
• Highest number of GPIO
• Only FPGA with hardened memory subsystem
• Only non-volatile and instant-on mainstream FPGA
Reliable FPGAs
• Extended temperature support (up to 125ºC Tj)
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ARM Processor Support in IGLOO FPGAs
High-Performance FPGA
High Speed Memory Interfaces
High Speed Serial Interfaces
High-Performance Memory Subsystem
High-Performance Routing Hierarchy
Advanced I/O
Embedded Memory
Reprogrammable Flash Technology
In-System Programming (ISP) and Security
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IGLOO2 FPGA Architecture
• 4-input look-up table (LUT) based fabric
• 5G transceivers
• based on a 130-nm flash process
• High-speed general purpose I/O (GPIO)
• Block RAM
• Digital signal processing (DSP) blocks in a differentiated, cost- and
power-optimized architecture
• Up to 5X more logic density and 3X more fabric performance than its
Predecessors
• Combines a non-volatile flash-based fabric with the highest number of
GPIO
• 5G serialization/deserialization
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FPGA Memory Blocks
uRAM 1Kbit
18-bit Three Port Memory(2Reads and
1Writes)
Synchronous Writes always
Asynchronous or Synchronous Read
Operation
400MHz
Implemented as a register file
Ideal for small memory,small FIFO,register
file and small DSP Lookup tables
Ideal for creating larger Memories
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Device Programming
The SmartFusion2/IGLOO2 device can be programmed through the
following dedicated interfaces:
• JTAG
• SPI
Following are the supported modes:
• Auto programming mode
• In-system programming:
– JTAG programming mode
– SPI Slave programming mode
• In-application update:
– Cortex-M3 update mode (only for SmartFusion2 device)
– Auto update mode
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Low Power Design Techniques
Flash*Freeze Technology
The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low power Flash*Freeze mode.
IGLOO devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers.
Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field.
The ability of IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power.
When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is
retained.
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LowPowerDesignTechniques(con’t)
Multi VDD Supply
Floating VDDIs and Some of Pins
Defining “UNUSED Condition” for
reduction of power consumption
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