Exploiting Satisfiability Modulo Theories for Analog Layout Automation

Exploiting Satisfiability Modulo Theories for Analog

Layout Automation

Sherif M. Saif,

Mohamed Dessouky

Mentor Graphics Egypt,

78, El Nozha St, Heliopolis,

Cairo 11361, Egypt [email protected]

Salwa Nassar Computer and Systems

Dept, ERI

El Tahrir Street, Dokki,

Giza, Egypt, Egypt [email protected]

Hazem Abbas Computer Science &

Engineering, GUC

New Cairo, Egypt

[email protected]

M. Watheq El-Kharashi

Computer & Systems Eng.

Dept., Faculty of

Engineering, Ain Shams

University, Cairo 11517,

Egypt

[email protected]

Mohammad Abdulaziz

Research School of

Computer Science

ANU College of

Engineering & Computer

Science, Australia

Abstract—This paper explores the use of Satisfiability Modulo

Theories to handle mirror symmetry and common-centroid

analog layout placement constraints. The proposed system reads

the constraints and generates the corresponding equations or

inequalities needed for Microsoft Z3 solver. These inequalities

are resolved using quantifier free nonlinear real arithmetic

theory. This theory has doubly exponential complexity in the

worst case and it guarantees generating a solution if one exists.

The proposed system produces multiple layouts that satisfy the

constraints and allows the designer to choose the appropriate one

according to designer’s experience.

Keywords—Analog, Placement, Layout, Automation, SMT, Z3

I. INTRODUCTION

Due to the increasing functional complexity of system-on-chips, the difficulties in analog design and the lack of design automation support for analog circuits continually increase the bottleneck of analog components in chip design. Automation of analog layout and analog placement has been a research interest since late 1980s [1] [2].

Usually, the layout of analog IC’s has been manually designed by experts [3]. Analog placers use a variety of mostly manually entered physical constraints for placement and certain analog-specific layout conventions to automatically generate small sections of the layout. The placement and routing of analog circuits has a severe impact on the overall performance. Thus, layout constraints are defined to make sure that the circuit fulfills the desired performance specifications. As an example, unbalanced parasitics, being a result of asymmetrical layout, may be detrimental to the power supply rejection ratio or the offset voltage of an analog amplifier. The number and diversity of constraints imposed on an analog circuit prevent approaches used in the digital domain from being used for analog design. With advanced nodes, a layout that meets every physical constraint can still fail to meet the electrical requirements of the design. Designers are quick to recognize the appropriate physical constraints; leading to correct electrical behavior using their experience. They have the ability to rapidly evaluate multiple solutions and quickly discard those options whose physical implementations do not meet the electrical constraints assigned to them.

Hence, the latest generation of analog placement tools has been designed to create a variety of alternative layouts from which designers can choose. This puts the designer back into

the picture by presenting choices rather than assuming that the software has chosen the best layout. The designer can make the choice since layout decisions involve compromise. Prototyping the layout gives the designer control over the automated process and provides a reasonable trial placement from which the final layout can be quickly completed [4].

In this work, the Satisfiability Modulo Theories (SMT) are exploited to find valid placement solutions for analog blocks given pre-defined constraints. In the last few years, satisfiability became the core engine underlying a wide range of powerful technologies. SMT is an active and exciting area of research with many practical applications [5]. The proposed system uses Microsoft Z3 SMT solver [6] to find feasible solutions for a set of equations that are produced by the system to describe the given constraints. The user has the option to choose one of the feasible solutions.

In the following sections the constraints, the corresponding equations and the placement generated by the proposed system are shown. This paper is organized as follows. The next section contains a concise description of SMT solvers and Z3 solver. Section III lists the analog constraints of concern and their equations. Section IV discusses the suggested implementation approach. Section V shows the results in addition to a discussion and section VI concludes the paper.

II. SMT SOLVERS

A. Introduction

Satisfiability Modulo Theories (SMT) is an area of automated deduction that studies methods for checking the satisfiability of first-order formulae with respect to some logical theory T of interest. The problem draws on a combination of some of the most fundamental areas in computer science; Boolean satisfiability with other domains, such as, those studied in convex optimization and term manipulating symbolic systems. It also draws on the most prolific problems in the past century of symbolic logic: the decision problem, completeness and incompleteness of logical theories, and finally the complexity theory. Modern analysis and model-based tools are increasingly complex and multi-faceted software systems, but, at their core is invariably a component using symbolic logic for describing states and transformations between them. A well-tuned SMT solver that takes into account the state-of-the-art breakthroughs usually scales orders of magnitude beyond custom ad-hoc solvers [7].

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2014 9th International Design and Test Symposium

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It differs from general automated deduction in that the background theory T needs not be finitely or even first-order axiomatizable, and specialized inference methods are used for each theory. By being theory-specific and restricting their language to certain classes of formulae, such as quantifier-free formulae, and specifically quantifier free nonlinear real arithmetic (QFNRA) theory used in this work, these specialized methods can be implemented in solvers that are more efficient in practice than general-purpose theorem provers [8].

B. Z3

Z3 is a state-of-the art theorem prover. It was provided by Microsoft Research. Z3 can be used to check the satisfiability of logical formulae over one or more theories. Z3 is a low level tool and it is best used as a component in the context of other tools that require solving logical formulae. It exposes a number of application programming interface (API) facilities to make it convenient for tools to map into Z3. The language syntax used in the front ends favor simplicity in contrast to linguistic convenience. Z3 source version can be downloaded from [6]. This section provides a brief explanation for the Z3 input syntax and usage.

Z3 input format is an extension of the SMT-LIB 2.0 standard [8]. A Z3 script is a sequence of commands where the user uses these commands to provide assertions. These assertions enclose the equations or constraints that the user provides in order to model the system. These equations are written in prefix notation [9]. A formula is “satisfiable” if there is some assignment of appropriate values to its uninterpreted function and constant symbols under which the formula evaluates to true. Hence satisfiability is about finding a solution to a set of constraints. In order to use the solver to check the satisfiability of a formula the “assert” command is used. The “assert” command adds a formula into the Z3 internal stack. A set of formulae in the Z3 stack is satisfiable if there is an interpretation that makes all asserted formulae true. Another command is “check-sat” which determines whether the formulae on the Z3 stack are statisfiable or not. Z3 returns “sat” if the formulae are satisfiable and returns “unsat” if the formulae are unsatisfiable. A command called “get-model” can be used to retrieve an interpretation that makes all formulae on the Z3 internal stack true. A formula is “valid” if it always evaluates to true for any assignment of appropriate values to its uninterpreted function and constant symbols. If the problem is satisfiable, we can get at least one “valid” solution for the problem. If the command “check-sat” returns “sat”; we can use “get-model” to obtain a “valid” solution for the defined problem. Z3 hence provides an interpretation, which is a solution, using “definitions”. The “definitions” is a syntax used by Z3 to express the interpretation in the form of functions. For example,

(define-fun variable1 () Int [value1])

states that the value of variable1 in the model is [value1].

Section IV will discuss how to represent the equations that models the analog layout constraints in the input syntax of the Z3 solver, and how to parse afterwards the output of the Z3 solver, in order to obtain a valid solution.

III. ANALOG CONSTRAINTS

In common layout approaches, the placement is generated before routing the circuit. The placement is subject to various constraints. These constraints are formulated to improve the matching of devices which are intended to be identical by design. Matching can be considered to be an umbrella term of different means to reduce the influence of variations of the process and operating conditions, as well as parasitics. Hence, the placement of devices can be affected by many constraints [10] such as symmetry constraints, and Common Centroid Constraints. In [11] Strasser et. al. use these constraints among others to achieve placement using “Plantage” algorithm. In this section we list these constraints and their equations. The handling of these constraints by our proposed system will be explained in the following sections.

A. Minimum Separation Constraints

A minimum distance constraint is formulated to make sure that all modules m within the set of modules A keep a distance d(m, n) ≥ dmin(m, n) from all other modules (n ∉ A):

∀m∈A,n∉Ad(m, n) ≥ dmin(m, n), dmin(m, n) ≥ 0

B. Symmetry Constraints

The vertical symmetry constraints are formulated as follows. If module i' denotes a module that is to be placed symmetrically to some module i, symmetry constraints will be represented by the following equations [11]

∀i (1

2(xi +

wi

2+ xi′ +

wi′

2) = xsym)

∀i (yi +hi

2= yi′ +

hi′

2)

where the lower left coordinates of modules i and i' are represented by (xi, yi) and (xi’, yi’), respectively. Width and height of module i are wi and hi, respectively. Width and height of module i' are wi' and hi', respectively. The x-coordinate of the symmetry axis is xsym.

C. Common Centroid Constraints

Common centroid constraints can be formulated, as shown in the following. If the coordinates of the center of gravity (COG) of a module m are defined as

xCOG(m) = xm + wm

2

yCOG(m) = ym + hm

2

where for every module m, the lower left corner coordinates are described by xm and ym, and the width and height are referred to as wm and hm, respectively. Using vectors, the center of gravity can be formulated as XCOG(m):

XCOG(m) = (xCOG(m)

yCOG(m))


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Hence for groups of modules, a center of gravity can be defined as:

XCOG(G) = (∑ wm .hm .X(COG)(m) m∈modulesOf(G)

∑ wm .hmm∈modulesOf(G))

For two groups A and B the common centroid constraint dictates that the two groups of modules have the same center of gravity, or in other words the centers of gravity of the two groups should coincide.

Hence, for example, given two groups A and B, each composed of 8 blocks; this should yield the structure depicted in Fig. 1 as one of the many possible solutions.

IV. IMPLEMENTATION

A. System flow diagram

Fig. 2 shows the operation of the flow of the proposed system:

1) The “Define constraints” module The first module defines the set of constraints according to

equations (1)—(7). It defines the set of constraints according to an argument that is passed to the module that defines whether the system is dealing with minimum separation, mirror symmetry, or common centroid constraints. This is depicted in Fig 3. The “Sep Utility”, “MS Utility” and “CC Utility” handle the minimum separation, mirror symmetry, and common centroid constraints, respectively. The utilities are coded in shell scripts and generate the equations that model the corresponding constraints. This module provides an important feature of the proposed system. This feature is the system modularity or the capability to add more constraints handling to the system by just adding a plug-in “constraint utility”. For example if a perfect symmetry constraint should be added to the system; the generating Perfect Symmetry Utility (PS Utility) should be added to the system by adding a script that models its equations.

2) The “Call Z3 SMT solver” module After the proper constraints are echoed –in the form of

equations– and passed to the Z3 solver; the solver defines

whether the problem is satisfiable [7] or not. If it is satisfiable the solver recommends the values that solve the problem.

3) The “Output parser” module There is a module that parses the output of the Z3 solver

and converts it into commands that physically place the geometries on a layout sheet. This module is coded in Perl.

4) The “Place geometries” module This final module uses the output of the parser to invoke an

IC layout tool and draw the geometries. The tool that was used for drawing the resulting geometries is Mentor Graphics Pyxis Layout (IC Station Layout Editor) [12].

B. Minimum Separation Constraint

The minimum separation equation (1) can be broken down into the following rules between any two blocks. The two blocks should:

1) not overlap horizontally 2) not overlap vertically 3) be separated by a minimum separation in the horizontal

direction 4) be separated by a minimum separation in the vertical

direction

This can be translated into the following: The x-coordinate of the second (first) block is greater than the x-coordinate of the first (second) block + its width + minimum separation. On the other hand, the y-coordinate of the second (first) block is greater than the y-coordinate of the first (second) block + its height + minimum separation. Therefore, this translates to the following assertions:

assert that (x_Bn > (x_Bm + (BlockWidth[m] + MinSeparation))) or (x_Bm > (x_Bn + (BlockWidth[n] + MinSeparation)))

assert that (y_Bn > (y_Bm + (BlockHeight[m] + MinSeparation))) or (y_Bm > (y_Bn + (BlockHeight[n] + MinSeparation)))

where Bm is the first block, Bn is the second block, x_B# is the x-coordinate of the left of B# block and y_B# is the y-coordinate of the down side of B#, MinSeparation is the minimum allowed spacing between two devices.

Z3 accepts prefix mathematical notation. Therefore these equations will be coded as follows:

(assert (or (or (> x_Bn (+ x_Bm (+ BlockWidth[m] MinSeparation))) (> x_Bm (+ x_Bn (+ BlockWidth[n]

Fig. 3. System utilities for defining constraints.

Fig. 1. 2-D Common centroid.

Fig. 2. System flow diagram.


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MinSeparation)))) (or (> y_Bn (+ y_Bm (+ BlockHeight[m] MinSeparation))) (> y_Bm (+ y_Bn (+ BlockHeight[n] MinSeparation))))))

The following constraints should follow the same procedure to extract the corresponding SMT equation.

C. Symmetry Constraint

The argument “ms” causes the tool to invoke a utility called “MS utility”, refer to Fig. 3. It implements (2) and (3)

1/2 [x1 + w1/2 + x2 + w2/2] = xsym

y1 + h1/2 = y2 + h2/2 where:

(x1, y1) are the coordinates of the left below corner of the first block

(x2, y2) are the coordinates of the second block

w1, w2, are the widths of the first block and second block, respectively.

h1, h2 are the heights of the first block and second block, respectively.

This resolves to the assertion of two ANDed conditions:

(assert (and (= (+ (+ x1 (/ w1 2)) (+ x2 (/ w2 2))) xsym) (= (+ y1 (/ h1 2)) (+ h2 (/ h2 2)))))

D. Common-Centroid Constraint

The tool accepts an argument “cc” for common-centroid. Accordingly, it calls the “CC utility”, which implements the common centroid function.

For example, given two groups A and B, each composed of four devices, there is a total of eight devices that should be coded according to (4)—(6). For eight devices: four for group “A” and four for group “B”, (7) holds:

XCOG(A) = XCOG(B)

If the widths of blocks a1…a4 and b1…b4 are w_a1, w_a2, w_a3, w_a4, w_b1, w_b2, w_b3, and w_b4 respectively, and the heights of blocks a1…a4 and b1…b4; are: h_a1, h_a2, h_a3, h_a4, h_b1, h_b2, h_b3, and h_b4, respectively, and left x-coordinates of blocks are x_a1, x_a2,… x_a4, x_b1,… x_b4, and the below y-coordinates of blocks are y_a1, y_a2,… y_a4, y_b1…y_b4; therefore (4)—(7) should be:

w_a1*h_a1*(x_a1+w_a1/2) + w_a2*h_a2*(x_a2+w_a2/2) + w_a3*h_a3*(x_a3+w_a3/2) + w_a4*h_a4*(x_a4+w_a4/2) /

(w_a1*h_a1 + w_a2*h_a2 + w_a3*h_a3 + w_a4*h_a4) = w_b1*h_b1*(x_b1+w_b1/2) + w_b2*h_b2*(x_b2+w_b2/2) + w_b3*h_b3*(x_b3+w_b3/2) + w_b4*h_b4*(x_b4+w_b4/2) / (w_b1*h_b1 + w_b2*h_b2 + w_b3*h_b3 + w_b4*h_b4) AND w_a1*h_a1*(y_a1+h_a1/2) + w_a2*h_a2*(y_a2+h_a2/2) + w_a3*h_a3*(y_a3+h_a3/2) +

w_a4*h_a4*(y_a4+h_a4/2) / (w_a1*h_a1 + w_a2*h_a2 + w_a3*h_a3 + w_a4*h_a4) = w_b1*h_b1*(y_b1+h_b1/2) + w_b2*h_b2*(y_b2+h_b2/2) + w_b3*h_b3*(y_b3+h_b3/2) + w_b4*h_b4*(y_b4+h_b4/2) / (w_b1*h_b1 + w_b2*h_b2 + w_b3*h_b3 + w_b4*h_b4)

The utility will generate the following equation to be passed to the Z3 solver:

(assert (and (= (/ (+ (+ (* w_a1 (* h_a1 (+ x_a1 (/ w_a1 2)) ) ) (* w_a2 (* h_a2 (+ x_a2 (/ w_a2 2)) ) )) (+ (* w_a3 (* h_a3 (+ x_a3 (/ w_a3 2)) ) ) (* w_a4 (* h_a4 (+ x_a4 (/ w_a4 2)) ) ))) (+ (+ (* w_a1 h_a1) (* w_a2 h_a2)) (+ (* w_a3 h_a3) (* w_a4 h_a4)) ) ) (/ (+ (+ (* w_b1 (* h_b1 (+ x_b1 (/ w_b1 2)) ) ) (* w_b2 (* h_b2 (+ x_b2 (/ w_b2 2)) ) )) (+ (* w_b3 (* h_b3 (+ x_b3 (/ w_b3 2)) ) ) (* w_b4 (* h_b4 (+ x_b4 (/ w_b4 2)) ) ))) (+ (+ (* w_b1 h_b1) (* w_b2 h_b2)) (+ (* w_b3 h_b3) (* w_b4 h_b4)) )) ) (= (/ (+ (+ (* w_a1 (* h_a1 (+ y_a1 (/ h_a1 2)) ) ) (* w_a2 (* h_a2 (+ y_a2 (/ h_a2 2)) ))) (+ (* w_a3 (* h_a3 (+ y_a3 (/ h_a3 2)) ) ) (* w_a4 (* h_a4 (+ y_a4 (/ h_a4 2)) ) ))) (+ (+ (* w_a1 h_a1) (* w_a2 h_a2)) (+ (* w_a3 h_a3) (* w_a4 h_a4)) ) ) (/ (+ (+ (* w_b1 (* h_b1 (+ y_b1 (/ h_b1 2)) ) ) (* w_b2 (* h_b2 (+ y_b2 (/ h_b2 2))) )) (+ (* w_b3 (* h_b3 (+ y_b3 (/ h_b3 2)) ) ) (* w_b4 (* h_b4 (+ y_b4 (/ h_b4 2)) ) ))) (+ (+ (* w_b1 h_b1) (* w_b2 h_b2)) (+ (* w_b3 h_b3) (* w_b4 h_b4)) ) ) ) ) )

V. RESULTS

The proposed system is implemented in a command line

tool that accepts several arguments. These arguments define

the following:

The constraint(s): mirror symmetry and/or common-centroid.

The maximum area that can be defined by each group of blocks.

The value of the minimum separation between blocks.

The number of generated layouts.

A. Minimum Separation

Minimum separation constraint is a constraint that should be satisfied in parallel with other constraints, such as symmetry and common-centroid.

B. Mirror Symmetry

The result of running the mirror symmetry constraints on two sub-devices is shown in Fig 4.

The tool was invoked again but this time with defining 2

groups of sub-devices, each constituted of 4 sub-devices. An

argument defines that up-to-5 layouts can be generated. The

output of the tool in this case is shown in Fig. 5.

Fig. 4. Output of solver for mirror symmetry constraint for 2 devices.


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C. Common-Centroid

The result of running the common-centroid constraints for 2

groups each of them constituted of 4 subdevices is shown in

Fig 6. The subdevices are not aligned because no alighnment

constraint is used. Supporting other constraints such alignment

constraint is a part of the future work.

The result of running the common-centroid constraint for 2

groups each of them constituted of 8 sub-devices, while

defining the number of generated layouts to be up-to-9

layouts. The output layouts of the tool in this case are shown

in Fig 7.

D. Simultaneous Common-Centroid and Mirror Symmetry

The tool is used to work simultaneously on common centroid

and mirror symmetry. The tool was invoked with two

constraints. A common-centroid constraint is to be applied on

two groups each of them is constituted of 8 sub-devices. A

mirror symmetry constraint is to be applied on other two

groups each of them is constituted of 8 sub-devices. The

number of generated layouts in this example was defined to be

up-to-9. However, the system will try generating a higher

number if the user specifies a higher limit. No upper value is

expected by the system for this argument. The output of the

tool using these arguments is shown in Fig. 8, 9, 10.

E. Discussion

Results that were achieved using the SMT solver accomplish

the purpose of finding valid placements according to some

given analog constraints. The solver uses the satisfiability

mathematics to move from coding of constraints to placement

in a manner that can be easily expanded. The easiness of

expanding this system can be shown by comparing it to the

several intermediate structures that are formed in the

“Plantage” algorithm [10] for instance. Our proposed system

needs only to form equations and inequalities that describe the

given analog constraints. In addition, in this work we use

quantifier free nonlinear real arithmetic (QFNRA) theory for

representing these formulae. This theory has doubly

exponential complexity in the worst case. In all the examples

that were presented, the time for generating a layout did not

exceed several seconds. Future work should define time for

real benchmarks. Because QFNRA is a decidable theory and

Z3 has a complete decision procedure for it, it always

guarantees generating a solution if one exists. It also secures

that the placement has formal guarantees of conforming to the

user constraints.

VI. CONCLUSION

The proposed system is implemened in scripts and Perl. It

creates a wrapper that translates the analog constraints into

mathematical equations needed for the Z3 SMT solver.

Afterwards, it parses the output of the solver and translates it

into geometries that correspond to a placement that satisfies

the analog constraints. The system is extensible since it allows

any “Constraint Utility” plugin to be added to the system. We

claim that the simplicity of expandability of the system gives

it an edge over other proposed systems, in addition to using a

method that provides formal guarantees of having a placement

that is conforming to the user constraints.

Future work would include expanding the sytem by adding

more modules in the “define constraints” section to support

other constraints such as alignment and perfect symmetry. In

addition the program would be coded in C and use Z3 API’s

instead of scripting, and the running time can be then assessed

using real benchmarks.

Fig. 6. Output of solver for common-centroid constraints for 2 groups

each of 4 sub-devices.

Fig. 7. Output of solver for common centroid constraints for 2 groups

each constituted of 8 sub-devices. Nine layouts are generated.

Fig. 5. Output of solver for mirror symmetry constraints for 2 groups.

Each group has 4 sub-devices. Five layouts are generated.


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REFERENCES

[1] J. Rijmenants, J. B. Litsios, T. R. Schwarz and M. G. R. Degrauwe,

“ILAC: An Automated Layout Tool for Analog CMOS Circuits”, IEEE Journal of Solid State Circuits, vol. 24, no. 2, pp. 417–425, April 1989.

[2] M. Kayal, S. Piguet, M. Declercq and B. Hochet, “SALIM: A Layout Generator Tool for Analog ICs”, in Proc. IEEE Custom Integrated Circuits Conference, pp. 751–754, May 1988

[3] S. Koda, C. Kodama and K. Fujiyoshi, “Improved Method of Cell Placement with Symmetry Constraints for Analog IC Layout Design”,. Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006

[4] R. Morse, “Interoperable Design Constraints for Custom IC Design”, IEEE Design & Test of Computers, vol. 29, Issue 2, pages 53-61, March/April 2012, .

[5] N. Bjørner and L. de Moura. “z310: Applications, enablers, challenges and directions”. In CFV ’09 Sixth International Workshop on Constraints in Formal Verification, 2009.

[6] Z3: provided by Microsoft, Open source at: http://z3.codeplex.com

[7] L. de Moura and N. Bjørner. “Satisfiability modulo theories: An appetizer. In Formal Methods: Foundations and Applications, 12th Brazilian Symposium on Formal Methods”, SBMF 2009, Gramado, Brazil, August 19-21, 2009, Revised Selected Papers, vol. 5902 of Lecture Notes in Computer Science, pages 23-36. Springer, 2009.

[8] The Satisfilability Modulo Theories Library, http://www.smtlib.org/

[9] F. Gecseg, M. Steinby, Tree Languages, In: vol. 3: Beyond Words. Handbook of Formal Languages. pp. 1-68, Springer, Berlin, Heidelberg, 1997.

[10] M. P. Lin and Y. Chang, “Hierarchical Placement with Layout Constraints”, in “Analog Layout Synthesis: A Survey of Topological Approaches , by Helmut E. Graeb, Editor. Springer. 2011

[11] M. Strasser, M. Eick, H. Graeb, U. Schlichtmann, and F. M. Johannes. “Deterministic Analog Circuit Placement using Hierarchically Bounded Enumeration and Enhanced Shape Functions”. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 306–313, November 2008.

[12] IC Station: for Analog Layout, provided by Mentor Graphics Corporate, http://www.mentor.com

Fig. 8. Output of solver for common centroid and mirror symmetry

– layouts no. 1,2 out of 9.


– layouts no. 5,6,7,8 out of 9.


– layouts no. 3,4 out of 9.


– layout no. 9 out of 9.


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Exploiting Satisfiability Modulo Theories for Analog Layout Automation