Logical circuit gate sizing using MPSO guided by Logical Effort - an examination of the 12-stage ripple carry adder circuit

Logical Circuit Gate Sizing using MPSO guided by Logical Effort – An Examination of the 8-Stage Full

Adder Circuit A. Johari#1, S. Mohamed#2, A. K. Halim#3, I. M. Yassin#4, H. A. Hassan*5,

#Faculty of Electrical Engineering, Universiti Teknologi Mara Shah Alam, Selangor, Malaysia [email protected] [email protected]

[email protected] [email protected]

*Faculty of Engineering, Universiti Industri Selangor

Bestari Jaya, Selangor, Malaysia [email protected]

Abstract— Automated Complementary Metal Oxide Semiconductor (CMOS) logic circuit design leads to the reduction in costs associated with manpower and manufacturing time. Conventional methods use repetitive manual testing guided by Logical Effort (LE). Our previous works have shown the applicability of the Particle Swarm Optimization (PSO) algorithm guided by LE in searching for optimal gate widths for CMOS design. In this paper, we present a PSO variant called Mutative Particle Swarm Optimization (MPSO) to automate the sizing process of CMOS circuit design on an 8-stage full adder circuit. In our work, we choose gate widths inside the circuit as parameters to be optimized in order to achieve the target delay, with the solution fitness guided by the LE method. Various parameters, such as swarm size and iterations were tested under different initialization conditions to verify MPSO’s performance on a 8-stage full-adder circuit. Results have indicated that the MPSO algorithm was an effective method to apply to the circuit design problem, with high convergence rates observed.

Keywords- Logical Effort, Automated circuit design, Particle swarm optimization, Mutative Particle swarm optimization, full-adder

I. INTRODUCTION Logical Effort (LE) [1] is a method for fast evaluation of

delays in logic paths. This method is a straightforward technique to estimate delay and to choose the best number of stages in a Complementary Metal Oxide Semiconductor (CMOS) circuits [2]. LE has since been adopted as a basis for many Computer-Aided Design (CAD) tools. It helps designer to quickly estimate the minimum possible delay in a circuit, and to choose the appropriate gate sizes to achieve this delay. However, the sizing process still requires repetitive tests by the designer to achieve the desired delay [3].

Particle Swarm Optimization (PSO) is a population-based

stochastic optimization technique based on swarm theory and evolutionary computation [4]. It is inspired by the seemingly intelligent swarming behavior of animals in nature [5]. PSO has a successful track record in solving many optimization problems [6-10]. The algorithm is simple and computationally inexpensive, yet fast and efficient [11-14].

Our previous works [15, 16] have successfully applied the

PSO to the gate sizing problem of simple circuit topologies. In this paper, the application of the Mutative Particle Swarm Optimization (MPSO) variant is proposed as an alternative to PSO, while applying the algorithm to a more complex and widely used circuit topology – the 8-stage full adder circuit. Experiments were performed to determine the solution quality and convergence over different MPSO parameter settings, and the results are presented.

This paper is organized as follows: Some previous works

are presented in Section II. The theoretical background to the proposed approach is presented in Section III. The experimental setup is presented in Section IV, and the results and discussions are presented in Section V. Finally, Section VI presents the conclusions of this paper.

II. PREVIOUS WORKS

A. Logical Effort (LE) Circuit delay is an important factor to consider in digital

circuit design. Failure to consider the delay may lead to circuit malfunctions and non-compliance to timing specifications. Such failures are called delay faults [17].

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The LE method [3] has been introduced

quick and accurate analysis of digital cidefines the overall circuit delay in concrterms, combined to a linear Resistance-Cdelay mode [3]. This method can be usedanalysis of existing circuits, as well as tosizing and estimate the optimal number of sta

B. Adders and previous works on adders Fast adders are widely used in CMOS circ

Arithmetic-Logic Unit (ALU). Various typbeen designed: half-adder, full-adder and rAll adders offer different tradeoffs betweenpower consumption. Analytical delay modeevaluate these tradeoffs, but simply countiinadequate because circuit delay also depend

Full-adder is a type of adder that perform

operation. It constructed of basic gate such aNAND and NOR gates. Based on CMOS gates are constructed using PMOS as pull NMOS as pull down transistor. The time gates (normally known as delay) to prodmainly affected by the area of the transistoon adders design involves increasing its speetopologies [19], gate sizing and routing [18sizing is most preferable since only mirequired from the previously created libraries

C. PSO PSO is a population-based stochas

technique inspired by animal swarming behaThe exploration of the solution space is peragents called particles. The solution is competitive and cooperative behavior of agenis simple and computationally inexpensiefficient [5, 12-14].

PSO has a successful track record i

optimization problems [20]. Since PSO ageparallel in nature, PSO allows efficient andof the problem [21]. Furthermore, PSO remathematical operators (plus, minus and muoptimization [5]. It is memory-inexpensive [parameters need to be stored to update Another benefit of PSO is that it rcomputational and memory costs for each ite

III. THEORETICAL BACKGRO

A. Implementation of Logic Gates at TransisTransistors form the basis of any logic

these transistors can be arranged of ways to logic function. A list of several logic gate imshown in Table I.

This work is sponsored by Universiti Teknologi Ma

to allow for both ircuit design. LE rete mathematical Capacitance (RC) d for comparative o guide transistor ages in the circuit.

cuits as part of the es of adders have ripple-carry adder. n delay, area, and els help designers ing logic levels is ds on fan-out [18].

ms a full addition as inverter, buffer, technology, these up transistor and

required by these duce an output is or. Previous works ed by adjusting its ] and others. Gate inor changes are s.

stic optimization avior in nature [6]. rformed by simple achieved by the nts. The algorithm ve, yet fast and

in solving many ents (particles) are d fast optimization equires only basic ultiply) to perform [14], as only a few

future iterations. requires constant eration [12].

OUND

stor Level gate. In CMOS, perform a desired mplementations is

TABLE I. TRANSISTOR-LEVEL

Symbol

Inverter B

uffer N

AN

D

NO

R

Transistors are annotated wi

units so that each pull down st[18]. The size of these characteristics of the logic gatein a logic circuit, these transistoachieve the desired circuit dela

B. The Full- Adder Logic CircA full-adder is a logic circu

(with carry), and is implemdescribed in Table I.

A full adder takes three inp

two outputs and . Aadder is shown in Fig. 1 [22].

Fig. 1. Modified Ei

C. LE for the full adder circuitThe logical effort LE is the r

the gate input to the input capawith the same unit effective relogical effort and parasitic delacircuit. The parasitic delay (total transistor width on the o

ara, Malaysia.

L IMPLEMENTATIONS OF LOGIC GATES

Transistor Level

ith widths measured in arbitrary ack has unit effective resistance transistors affects the delay e. When the gates are combined ors must be sized accordingly to

ay.

cuit uit that performs 1-bit addition

mented using the logic gates

puts, , and and produces An implementation of the full-

ight-stage Full-Adder

t ratio of the input capacitance of acitance (3 units) of an inverter esistance [18]. Table II lists the ay of each gate in the full adder ) is estimated by counting the utput node, assuming diffusion


405

For each particle: 1) Do a velocity update as directed by Eq. (5). 2) Modify the particle position as Eq. (6). 3) Check the particle value, xid:

a) If the value is more than xMax, then pull the value of xid back to xMax, and set vid to 0 to stop searching in that direction.

b) If the value is less than xMin, then pull the value of xid back to xMin, and set vid to 0 to stop searching in that direction.

4) Rescale the solution using Eq. (7) and evaluate the fitness function.

5) Compare particle’s fitness with gBest. If the fitness is better than gBest, then update gBest with the new fitness value.

6) Kill off half of the particle population with the worst fitness, then replace them with mutated versions of gBest using Eq. (8).

7) Resume optimization for next particle at 1). 8) Finish optimization either when the maximum

iterations reached, or when the objective has been met

and gate capacitance are approximately equal [18].

TABLE II. LE & PARASITIC DELAY OF LOGIC GATES IN MODIFIED FULL ADDER CIRCUIT

Gate # of Input LE PD Inverter 1 1 1 Buffer 1 1 1 NAND 2 4/3 2 NOR 2 4/3 2

The single stage delay, , is measured by adding the stage

effort ( ) and together: ,/ (1)

where and are the logical and electrical effort of the gates. Eq. (1) can be extrapolated to cater for multi-stage circuits. In the case of multi-stage circuits, must be multiplied by the branching effort, : / (2)

where is the capacitance in the critical path, and is the capacitance which doesn’t lay in the critical path. The branching effort ( ) is important in multistage design, because it allows us to model a branch in a given network as its single-path equivalent. Eq. (1) thus becomes:

(3)

where the uppercase letters denote multi-stage application.

To find the minimum path delay, , the effort for each stage must be equal. This is done by setting to . Re-arranging Eq. (1) produces:

(4)

Once is known, this value can be distributed among

transistors in the stage.

D. The MPSO algorithm The MPSO variant is a modification of the constriction

factor variant of the PSO (PSOCF). PSOCF improves particle convergence by gradually decreasing particle velocities as iterations progress, so that particle movements near the optimum are localized.

The PSOCF algorithm search is directed by its velocity ( )

which modifies the particle’s position ( ): (5)

(6)

= particle velocity. = particle position.

= particle’s best fitness so far. = best solution achieved by the swarm so far.

= cognition learning rate = social learning rate.

, = uniformly distributed random numbers between 0 and 1.

=constant set according to and . Particle mutation was used to prevent particles from being

trapped in suboptimal points during a search [23]. Consider a swarm with N particles. After the particle positions have been updated after each iteration, the worst-performing N/2 particles were eliminated, and were replaced with mutated versions of gBest. The mutation was performed by making N/2 copies of gBest, and adding small random values to them so that they are placed near gBest. Therefore, the new particle positions:

(8) where is the mutation factor (which controls

how closely the new particle positions are place near gBest) and is a random value between 0 and 1. The pseudocode for MPSO is shown in Fig. 2.

Fig. 2 Pseudocode for MPSO algorithm.

E. Modifications on PSOCF to perform delay optimization Works by [4, 15] have used a scaling equation to rescale the

particle values in Eq. (2) with significant success in optimization of discrete variables. In this paper, a similar method was used. However, since the optimization was done


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in continuous form, the scaling equation in [4, 15] was modified by removing the rounding operator, which produces Eq. (7). Eq. (7) was originally used in [24] to transform neural network datasets to between a predefined range:

(7) where:

= particle position. = lowest integer value position. = highest integer value position.

= lowest range for continuous-valued solution. = upper range for continuous-valued solution.

Using Eq. (7) the particle solution, will always generate a solution between the predefined acceptable gate widths range.

IV. METHODOLOGY

A. Description of Experiments For the problem presented, several experiments were

performed. For all experiments, the initial swarm was uniformly distributed inside [0.5, 7]D, where D is 8, the corresponding dimension for the number of gate widths to be optimized. The swarm sizes tested is shown in Table III.

For each swarm size, the experiments were repeated 5 times

(using different random initialization values generated using the Mersenne-Twister Algorithm (MTA)). The initial MTA state (for the first repetition) starts from 0 and increased by 50,000 for next repetitions. This was done to measure the convergence with different initial particle values, as well as to ensure repeatability of the experiments.

TABLE III. SWARM SIZES USED FOR PSO OPTIMIZATION

Swarm size Max. Iteration Interval [ymin, ymax] 5 10, 15, 20, 25, 30 [0.5, +7]

10 10, 15, 20, 25, 30 [0.5, +7] 15 10, 15, 20, 25, 30 [0.5, +7] 20 10, 15, 20, 25, 30 [0.5, +7] 25 10, 15, 20, 25, 30 [0.5, +7] 30 10, 15, 20, 25, 30 [0.5, +7]

B. PSO Parameter Settings For the MPSO algorithm, the values of and were both

set to 2.05 [25]. The minimum and maximum values of were set to 0 and 1, respectively, to constrain the particle values between 0 and 1. The dynamic range of was set to between -1 (when moves from 1 to 0) and +1 (when moves from 0 to 1). The optimization process is represented with the flowchart in Fig. 3.

Fig. 3. MPSO optimization process

C. Fitness function The optimization objective was set to 28.909τ based on

electrical effort where the input capacitance, Cin, and output capacitance, Cout, were 1 and 16, respectively. However, this delay value can be set according to the requirements of the circuit design. The delays for several types of are shown in Table IV.

During optimization, the gate widths were set according to

MPSO values, and the corresponding delay is calculated. The difference between the calculated delay ( ) and the desired delay ( ) was determined as:

| | (8) A low fitness value indicates a good solution (as the fitness

minimizes the difference between the desired delay and the delay calculated using MPSO), and vice versa. This fitness value was then fed back to the MPSO algorithm for it to optimize its search in the following iterations.

TABLE IV

DELAY OF 4-STAGE FULL ADDER Electrical Effort

(H) Delay

16 28.909τ 8 27.50τ 4 26.22τ 2 25.04τ 1 23.96τ

V. RESULTS & DISCUSSIONS The convergence of the MPSO algorithm was tested for

different swarm sizes, iterations and initial seeds. For each swarm size, the experiment was repeated 5 times with different initial particle values generated using MTA. If MPSO managed to achieve the optimal the optimization is considered a success. Else, the optimization is considered a failure.

From the full adder circuit in Fig. 1, the path delay was first

minimized with maximum electrical effort in Table IV. Then


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we used this minimum delay as our timing constraint for minimizing area. The best convergences plots of the full adder delay by using MPSO algorithm are shown in Fig. 4 and summarized in Table V.

Fig. 4. Convergence plot for the best delay found using MPSO.

TABLE V

SUMMARY OF CONVERGENCE PLOT Result Particles Seed Iteration Difference Best 1 25 50000 30 3.20 10Best 2 20 150000 30 5.05 10Best 3 30 150000 30 1.41 10Best 4 25 0 15 1.99 10Best 5 15 50000 25 2.03 10

From Table V, it can be seen that the swarm size of 25

particles and 30 iterations at seeds equal to 50,000 gave the optimum delay since it gave the lowest difference between the MPSO-optimized delay and the objective delay, which was 3.20 10 τ . The convergence of MPSO with different swarm sizes was relatively consistent, indicating that small swarm sizes were sufficient to approximate the solution to the given problem. The values of swarm size and iterations are adjustable for more difficult circuit topologies.

After optimization, all trials converged to 28.909τ., which

was the optimal fitness value. All trials managed to find the optimal gate sizes for all logic gates in the full adder path. This result indicates that the proposed method has successfully been implemented to solve the test problem, even with different initialization values.

A comparison between the MPSO algorithm with the PSO

algorithm when applied to the 8-stage full adder circuit is shown in Table VI. It can be seen that MPSO managed to find better solution compared to PSO. The best MPSO solution was 3.20 10 while PSO method found it at 7.1710 .

TABLE VI

COMPARISON OF CONVERGENCE PLOT BETWEEN MPSO AND PSO Result MPSO PSO

Iteration Difference Iteration Difference Best 1 30 3.20 10 30 7.17 10Best 2 30 5.05 10 25 2.80 10 Best 3 30 1.41 10 20 3.21 10Best 4 15 1.99 10 25 3.21 10 Best 5 25 2.03 10 30 3.21 10

The gate widths (in terms of capacitance, not considering

wire capacitance), for the best MPSO and PSO solutions are shown in Table VII, with LE as a reference. The area used for every gate by using the MPSO method is larger compared to the PSO method. These observations indicate that while MPSO can minimize the delay more, it requires a larger gate width (area) in order to achieve it.

TABLE VII

FULL ADDER DELAY

Gate LE PSO MPSO

Delay Delay Delay Buf3 7.5701 3.1135 6.638 3.4102 5.8973 3.7131

Nand5 4.7755 4.1135 4.8785 3.8143 4.5810 3.7164 Buf2 4.5189 3.1135 4.1597 3.3209 1.8075 6.1764

Nand3 2.8507 4.1135 4.0769 3.3604 7.0000 2.3443 Not2 2.1918 3.1135 2.0234 3.8954 4.7752 2.8390

Nand2 1.3826 4.1135 1.7633 3.5300 6.1494 3.0354 Buf1 0.7674 3.1135 0.5000 5.0053 1.8524 4.4489

Nand1 0.4841 4.1135 1.1644 2.5725 3.8863 2.6355 Total Delay 28.909 28.909 28.909

VI. CONCLUSIONS

A novel MPSO variant by [4] was extended to find the gate widths of an 8-stage full adder circuit. The method uses the MPSO algorithm to automatically find the gate widths for the full adder logic gates based on a predefined delay. Experiments show that the MPSO method was capable to solve the LE problem well, even with increased complexity of the test circuit, with consistent results throughout different swarm sizes, iterations and initial conditions.

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Logical circuit gate sizing using MPSO guided by Logical Effort - an examination of the 12-stage ripple carry adder circuit