Calhoun: The NPS Institutional Archive

Theses and Dissertations Thesis Collection

1998-03-01

Re-engineering of a mission critical satellite

communications component TD-1271B/U

Hirschfelder, Joe T.

Monterey, California. Naval Postgraduate School

http://hdl.handle.net/10945/8896

SXSESCHOOtToNTEREY CA 93943-5101

MONTEREY CA 93943-510.

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1 . AGENCY USE ONLY (Leave blank) 2. REPORT DATEMarch 1998

REPORT TYPE AND DATES COVEREDMaster's Thesis

title and subtitle RE-ENGINEERING OF A MISSIONCRITICAL SATELLITE COMMUNICATIONS COMPONENTTD1271B/U

6. AUTHOR(S) Joe T. Hirschfelder and Laurence M. Nixon

FUNDING NUMBERS

7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES)

Naval Postgraduate School

Monterey CA 93943-5000

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11. SUPPLEMENTARY NOTES The views expressed in this thesis are those of the author and do not reflect the

official policy or position of the Department of Defense or the U.S. Government.

12a. DISTRIBUTION/AVAILABILITY STATEMENTApproved for public release; distribution is unlimited.

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1 3 . ABSTRACT (maximum 200 words)

Legacy software in general, and in the DoD environment in particular, presents an ever-

growing maintenance challenge to program managers. The software is cumbersome, written in arcane

languages and hosted on aging technology hardware. One of the options that is available to the

program manager to alleviate this problem is to re-engineer the existing software product and update it

to a newer language software hosted on modern equipment.

We review existing research, select a re-engineering methodology, develop an implementation

strategy and then perform a 'case study' examination of this methodology and strategy. For the case

study, we take a legacy system, the Navy satellite communications multiplexer, the TD1271B/U

Multiplexer, examine its existing documentation, develop a code analysis tool, perform the re-

engineering on one of its sub-systems, and analyze the results. We provide observations,

recommendations and conclusions on changes, enhancements and pitfalls to the methodology that will

be of assistance in future re-engineering efforts of legacy systems.

14. SUBJECT TERMS Reverse Engineering, Re-Engineering, Legacy Systems.

TD1271B/U.

15. NUMBER OFPAGES 176

16. PRICE CODE

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TION OF REPORT

Unclassified

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CATION OF THIS PAGEUnclassified

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NSN 7540-01-280-5500 Standard Form 298 (Rev. 2-89)

Prescribed by ANSI Std. 239-18 298-102

11

Approved for public release; distribution is unlimited.

RE-ENGINEERING OF A MISSION CRITICAL SATELLITE

COMMUNICATIONS COMPONENT TD1271B/U

Joe T. Hirschfelder

B.A., San Diego State University, 1979

Laurence M. Nixon

B.A.. University of California at San Diego, 1983

Submitted in partial fulfillment

of the requirements for the degree of

MASTER OF SCIENCE IN SOFTWARE ENGINEERING

from the

NAVAL POSTGRADUATE SCHOOLMarch 1?98

DUDLEY KNOX LIBRARYNAVAL POSTGRADUATE SCHOOLMONTEREY CA 93943-5101

ABSTRACT

Legacy software in general, and in the DoD environment in particular, presents an

ever-growing maintenance challenge to program managers. The software is cumbersome,

written in arcane languages and hosted on aging technology hardware. One of the

options that is available to the program manager to alleviate this problem is to re-engineer

the existing software product and update it to a newer language software hosted on

modern equipment.

We review existing research, select a re-engineering methodology, develop an

implementation strategy and then perform a 'case study' examination of this

methodology and strategy. For the case study, we take a legacy system, the Navy satellite

communications multiplexer, the TD1271B/U Multiplexer, examine its existing

documentation, develop a code analysis tool, perform the re-engineering on one of its

sub-systems, and analyze the results. We provide observations, recommendations and

conclusions on changes, enhancements and pitfalls to the methodology that will be of

assistance in future re-engineering efforts of legacy systems.

VI

TABLE OF CONTENTS

I. INTRODUCTION 1

A. BACKGROUND 1

B. RE-ENGINEERING 3

C. OUR THESIS 4

II. TD1271 B/U MULTIPLEXER 7

A. BACKGROUND 7

B. TIME DEVISION MULTIPLE ACCESS (TDMA) 8

C. TD 1271 B/U MULTIPLEXER 8

D. TD-1271B/U MULTIPLEXER DESIGN 12

III. THE RE-ENGINEERING PROCESS 15

A. PROCESS PHASES 15

/. Phase One: Abstraction 16

2. Phase Two 18

3. Phase Three 20

4. Phase Four 20

IV. THE CASE STUDY 21

A. THE TD1271B/U MULTIPLEXER DATA BUFFERING PROCESSOR 21

B. DBP INPUT/OUTPUT SIGNALS 21

C. THE RE-ENGINEERING STRATEGY 21

/. Code review 22

2. Extracting the Structure 23

3. Extracting the Control Flow 23

4. Data Flow 26

D. Use of the TD-1271 as an Engineering Guide 28

E. Documentation Review 28

/. Phase One: Architecture Definition 29

2. Phase Two: Requirements Definition 31

F. RECOMMENDATIONS 33

V. CONCLUSIONS 35

APENDIX A BIBLIOGRAPHY 37

APPENDIX B TD-1271B/U SUBROUTINE CALL TREE 41

APPENDIX C PARSER.ADA 63

APPENDIX D DATA BUFFER PROCESSOR SOURCE CODE LISTING 69

APPENDIX E DATA BUFFER PROCESSOR LABEL CROSS REFERENCE 145

APPENDIX F PHOTOS 163

INITIAL DISTRIBUTION LIST 165

vn

Vlll

LIST OF FIGURES

Figure 2-1 Time Division Multiplexing 9

Figure 2-2 Typical TD1271B/U Frame Configuration 9

Figure 2-3 A Basic TD-1271B/U Configuration 13

Figure 3-1 The Re-Engineering And Implementation Process 15

Figure 4-1 Inputs and Outputs To DBP Module 22

Figure 4-2 DBP Control Flow Diagram 25

Figure 4-3 Multiple Entrances and Exits 26

Figure 4-4 101A Control Flow 27

Figure 4-5 DBP High Level Structure Chart 30

Figure 4-6 Control Flow Diagram 32

IX

I. INTRODUCTION

A. BACKGROUND

One of the more complex issues associated with a software organization of

significant size is the existence of large amounts of legacy software. This software

typically was developed years ago, modified extensively by a variety of programmers,

and is currently operating on obsolete systems hardware. The programmers that worked

on the various modifications have moved on to new projects or left the organization

entirely. In most instances, limited or no documentation updates have occurred. These

factors all build upon each other until the software is no longer supportable. The

hardware is typically old and all of the original processor reserve has been consumed,

making the hardware as unsupportable as the legacy software that runs on it. The overall

system is so bad that it has but one single saving grace. It works.

The program manager is charged with the responsibility of continuing to provide

the services of the program while watching his ability to support the program fading.

This leaves the program manager few options.

One option is to live with the system as it exists and continue to 'Band-Aid' any

problems as best one can. This tends to be an expedient answer early in the life of the

program, but sooner or later, this will no longer be a viable option. At some point in time

the program manager will not be able to continue to support this legacy code due to

physical constraints or expense.

A second option is to completely replace the existing system. This involves

reviewing the current program requirements and documentation, as well as the

organization operations and goals, and then to factor in those enhancements that may

have forced this change in the first place. Based upon this review, a new set of

requirements are generated. From these new program requirements, the program

manager will need to select hardware, programming language(s). design architecture, and

finally implement the software. This is then followed by a training curve to allow the

operator to learn the new system. This approach has several drawbacks. The first is

1

usually a lack of current documentation to start the review from. It is commonplace for

organizations to try to limit their maintenance costs at the expense of the quality

documentation updates. Another problem are the 'hidden' enhancements; functions that

are routinely use by operators, but are not documented as requirements or options even in

well maintained documentation. A third is the amount of time needed to implement a full

development. And, of course, there is the cost. Often for large systems the costs of a full

development run hundreds of thousands of dollars, and it is not unknown for a single

program's development to cost millions of dollars.

A third option is to scrap everything except for the working code and perform an

in-depth analysis on the code to extract the requirements. This will tell the analyst what

the code is actually doing. To this must be added the additional requirements not

currently implemented. The state of the legacy code can be a drawback to this method.

The success of this method is dependent upon the standards and practices used while

maintaining the code. If the code was maintained by a series of programmers, each with

their own standards and practices, the analyst may find extracting the information to be

quite a challenge and extremely time consuming.

The fourth option is a combination of the last two, extracting the best features of

each of the two options to limit the cost and time associated with updating the system.

This is implemented by performing a code review and using the existing documentation

as a guide to the software's basic architecture. This combination of methods reduces the

amount of time required to perform the code analysis, while providing a quality

requirements trace.

Each of these options has it's own advantages and drawbacks. Early in the life

cycle of a software system it is fairly inexpensive to correct and fix an immediate

problem. As more changes are made it becomes more expensive to correct defects or

make changes. It is estimated that in a large data processing shop, 70 to 80 percent of the

budget is consumed by maintenance of legacy programs [40]. Eventually the legacy

system will need to be modernized.

When planning the modernization of a computerized information processing

system, there are two basic items to consider: the hardware and the software that

comprise the system. In the normal course of events finding a new target platform is the

easier process. The speed, power, and memory capacities of computer hardware have

been increasing; while hardware size and costs have been steadily falling. Replacing the

software itself is another question. As the costs of hardware have fallen, the costs of

software development have been rising.

This contrast of costs, cheap hardware and expensive software development, leads

the program manager to look at ways of lowering the cost of the software while updating

the hardware platform. The first approach would be to take the working software and

port it to a new, more powerful platform. This can be done in limited circumstances, but

he will normally be restricted to remaining within the existing family of processors (i.e.

going from a Motorola 68030 to a Motorola 68040). In the general case, he will run into

the problem of incompatibility. The existing legacy software will not run on the

processor in the new platform. This places the program manager at the crossroads noted

above: which of the four options is best for the project?

In this thesis we will examine the 'option four* method of modernization, that of

utilizing both the existing code and documentation to develop a new baseline program

hosted on a more modern hardware platform; the process of Re-Engineering.

B. RE-ENGINEERING

There are several definitions for re-engineering in the literature today [4 1 ] as

described in the following:

• "Software reengineering is any activity that (1) improves one's understanding

of software, or (2) prepares or improves the software itself, usually of increased

maintainability, reusability, or evolvability".

• "The process of modifying the internal mechanisms of a system or program

the data structures of a system or program without changing its functionality."

• "The examination and alteration of a subject system to reconstitute it in a new

form and subsequent implementations of that form."

• "Re-engineering changes the underlying technology of a system without

affecting the overall function, while reverse engineering is the backward

engineering of a system to the specification stage. ... Re-engineering ... is the first

step toward reverse engineering"

As can be seen from these quotes, the terminology of the process is not clearly

defined. Some believe that Re-engineering is the beginning of the Reverse Engineering

process, other that Reverse Engineering is the beginning of the Re-engineering process.

For our purpose within this thesis, we will look upon reverse engineering as the

systematic review and analysis of existing code to establish an information base from

which to re-implement the system i.e., the first step in the re-engineering process.

Even within these somewhat conflicting terms, there are levels of re-engineering.

If the only requirement is to "copy" the existing system onto a new platform, it will only

be necessary to extract the architecture from the existing code and documentation before

you can re-implement the same architecture in a new environment. If you want to update

the architecture, then you will need to extract up to the design level before re-coding can

start. Depending on the level of re-design you wish to implement you will need to extract

to one level higher to allow a baseline for forward engineering at the level you want to

implement.

C. OUR THESIS

For our thesis we selected a re-engineering methodology from existing research

that we thought had the best application to legacy systems. We then examined this

methodology of re-engineering by performing a case study. We took a legacy system,

examined the existing documentation, performed the re-engineering on one of it's sub-

systems and then analyzed the results. Based on this analysis and other observations we

will recommend modifications to the methodology that will assist in future re-engineering

efforts. Our legacy code for this procedure is a Navy satellite communications

multiplexer: the TD1271B/U Multiplexer.

II. TD1271B/U MULTIPLEXER

A. BACKGROUND

Until the space age, the high frequency (HF) spectrum was the only means of

passing messages over long distances by radio. Although other frequency spectrum

radios were available, their characteristics limited their use to iine-of-sight' operations or

limited data rates. With the space age came the ability to place an Ultra High Frequency

(UHF) radio repeater in a geosynchronous orbit. By placing a transmitting station high

above the earth, it's iine-of-sight' earth coverage was greatly expanded. The

characteristics of the UHF Satellite Communications lended itself well to the needs of the

Navy. It provided dependable over-the-horizon communications capability at accelerated

data rates. The high data rates allow the transfer of data and voice. As the capabilities

became more developed and terminals became more prolific, time lags and data delays

became more regular. System throughput began to suffer. This left the Navy with a

limited number of options. One was to reduce the number of users and the amount of

data they were sending. This was an extremely unpopular option to the Fleet. They had

grown to depend on the types and levels of data being supplied, and their effectiveness

would suffer if any of the data were discontinued. The second option was to acquire

more UHF channels. This was not a viable option either. The commercial world was

rapidly expanding into the UHF spectrum, and lobbying congress to decrease the number

of channels reserved for military use and sell them to commercial interests. The only

option left was to find ways to utilize the existing channels more efficiently. To meet the

need for more efficient usage of the UHF channels the Navy developed the TD-1271B/U

Multiplexer.

The basic philosophy behind the TD1271B/U Multiplexer, or MUX. is to use

Timed Division Multiple Access (TDMA) principals to integrated multiple nets, each

operating on an independent channel, onto a single channel. By multiplexing several

channels onto a single channel more data transmission path options become available.

B. TIME DEVISION MULTIPLE ACCESS (TDMA)

In TDMA, data streams at moderate to slow data rates are input via baseband data

ports and buffered. At a point in time, predefined for each data port relative to a time

marker, this data is transmitted out at a data rate that is significantly faster that the input

data rates. While one baseband port's data is being burst out to the satellite, the other

ports data streams are being buffered, awaiting their burst opportunity. Using appropriate

bursting speeds, none of the baseband units will suffer any loss of continuity in their data.

Each will transmit and receive data just as if on a dedicated channel, without realizing the

data was multiplexed. This concept is illustrated in Figure 2-1 . The key to this process is

being able to transmit at a faster data rate than all of the baseband ports data rates

combined. The elapse time between the start of one timing mark and the beginning of the

next timing mark is generally referred to as a frame. The period of time allocated for a

transmission burst is often referred to as a time slot. Depending on the particular protocol

for the system, the TDMA Frame may contain a series of time slots with equal time

periods or may have time slots with varying time periods.

C. TD1271B/U MULTIPLEXER

In the TD1271B/U Multiplexer (MUX) operating in the TDMA-1 25 kHz mode, a

frame is defined as a period of time equaling 1 .38666 seconds.1

This frame not only has

varying time slot periods, but is re-configurable based on users needs. The allocation of

time slots is determined by the definition of a three digit (hex) Frame Format code. Each

of the digits defines the configuration of one of the three user segments contained in the

frame. A typical MUX frame is diagrammed in Figure 2-2.

The MUX waveform accommodates multiple input/output (I/O) bit rates and

radio frequency (RF) symbol burst rates, as well as dynamic assignment of users between

channels. Operation of the MUX waveform is transparent to the user baseband

equipment, except for TDMA frame-time delays.

1 The TD1271 MUX is also capable of a secondary waveform (TDMA-2 or TDMA-3) that utilizes a 5kHz

channel. Discussion of this 5 kHz waveform is beyond the scope of this thesis.

TIME

TIMINGMARK USER 1 DATA USER 3 DATA USER 2 DATA

TIMINGMARK

TDMA MULTIPLEXER

y~i I

BASEBANDUSER#1

BASEBANDlUSER #2

BASEBANDUSER #3

Figure 2-1

Time Division Multiplexing

K-1.3866 SECONDS -1

50 mSH 75 781mS 45.521 mSM HR R

c AL T

rc •A'

NI E

CB' 'C

SEGEMENT N S SEGEMENT SEGEMENTG i >wE

K T w

136.667 mS H67.344 mS

729.375 mS ->w-281,979 mS

Figure 2-2

Typical TD1271B/U Frame Configuration

The MUX waveform is organized as a repetitive frame structure with

1.386-second frames, as depicted in Figure 2-2 (Frame Type 2 is depicted2

). Frames are

subdivided into slots assigned for: (a) orderwire communications [channel control

orderwire (CCOW) and return channel control orderwire (RCCOW)]; (b) system support

functions (range time slot and link-test time slot); and (c) user segments A, B, and C.

User segments A, B, and C comprise multiple user slots. Each of the 5 slot types in the

MUX waveform is identified below:

1

.

CCOW slot . The CCOW slot is used by the channel controller to

broadcast CCOWs. One of the 20 defined CCOWs is transmitted by the

Channel Controller in each frame. The CCOW contains the information

required to control operation of the waveform and provides a timing mark

for the frame.

2. RCCOW slot . The RCCOW slot provides users the opportunity to

send data, including requests for access, to the channel controller.

3. Range slot . The range slot provides time for users (including the

channel controller) to transmit and receive a data burst for the purpose of

calculating the range to the satellite, based on measured round-trip delay

time.

4. Link test slot . The link test slot provides time for users (including

the channel controller) to transmit and receive a test data stream to

determine the current operating conditions, based on the measured bit

error ratio (BER). The link test slot is also used to perform dedicated

range measurements, when the link test slot is in an even-numbered

receive frame. This is known as an even link test (ELT) slot.

2In order to support half duplex terminals, the MUX waveform supports a Frame Type 1 that moves the

'C segment slots between two halves of the 'B' segment. The half duplex network would transmit in the

first 'ET segment and receive in the second 'B' segment.

10

5. User slot . User slots are allocated for transferring data between

users. Associated with each user slot is a specific baseband data rate,

encoding schema, and burst rate.

Each slot within the MUX waveform consists of three elements: (1) a preamble

for receiver carrier, bit, and data synchronization; (2) data; and (3) guard time to avoid

user-to-user interference. The receiving equipment achieves carrier and bit

synchronization for each slot in the waveform.

The MUX waveform is designed to operate on 25-kHz non-processed channels of

current and planned UHF SATCOM satellites.

The MUX accepts input from digital communications systems via it's four

baseband data ports. The baseband data ports will accept data at rates of 75, 300, 600,

1200, 2400, 4800, and 16000 bits per second. In order to maintain data integrity,

Forward Error Correction (FEC) encoding is used. This FEC coding is convolutional,

with interleaving. Encoding rates of lA or V* are used. The MUX will output the data to

the radio for transmission at one of three burst rates; 9,600, 19,200 or 32.000 symbols per

second. The interface between the radios and the MUX is over 70 MHz intermediate

frequency carrier lines. Reception of data is processed in a similar, but reversed, fashion.

One of the most critical functions of the MUX in this process is to maintain

consistent timing within the frame. This timing begins with the reception of the timing

mark to begin the frame. In the MUX system, all timing is based on the reception of the

Channel Control OrderWire (CCOW). The primary CCOW is the Master Frame CCOW

and contains the current frame format number, frame sequence number, and

cryptographic data needed to define operations on this channel. The Master Frame is

transmitted every eight frames. Other CCOWs are available to direct net operations,

request data from the various terminals3operating on the net and maintain timing.

J

Although we are only concerned with software and hardware of the TD1271B/U, there are other terminals

that are operating on nets with the TD1271BAJ. When discussing operations in general, we will use the

term terminal to include all of the possible systems operating on a channel.

11

CCOWs are generated and broadcast by a specifically designated terminal. Each channel

will only have a single terminal generating CCOWs at a time (the Primary Channel

Controller (PCC)) although other stations could be designated as alternate controllers

(ACC).

Once the MUX has successfully received the CCOW, the next critical event is to

calculate the terminals distance to the satellite in units of time. The standard time unit in

the MUX is the 'time chip'. There are 19,200 time chips in one second. In order for all

terminals on the net to receive data in the proper locations within the frame, all

transmissions are timed to be correctly placed within the frame at the satellite. In order to

insure this 'perfect' frame at the satellite, and by extension at each receiving terminal, the

distance to the satellite must be known. This is achieved first at power-up by sending a

ranging burst during the designated ranging slot, and updated periodically using the Even

Link Test (ELT) slots.

D. TD-1271B/U MULTIPLEXER DESIGN

The basic TD-1271B/U installation comprises a TD-1271B/U multiplexer, a

KGV-1 1 encryption device, a radio transceiver (a Navy WSC-3 pair is typical) and from

one to four baseband user devices (ANDVT, ON- 143 or teletypewriters would be

typical). Figure 2-3 provides a block diagram of a basic TD-1271B/U's configuration.

The software in the MUX is divided into three Computer Software Configuration

Items (CSCI); the System Control Processor (SCP), the System Timing Processor(STP)

and the Data Buffer Processor (DBP).

Each CSCI has a Memory Program Unit (MPU), an interface board, and at least

one 24 k byte Ultra Violet Erasable/Programmable Read Only Memory (UVEPROM)

board that contains the executable program. The SCP CSCI utilizes two UVEPROM

boards.

12

The Memory Program Unit (MPU), hosts the Central Processor Unit (CPU), a

Motorola 6800, along with the System Random Access Memory.

^ w

Radio

TXRadio

RX

j L

rBaseband

User#l

i Baseband

User #3^

TD-1271B/U^

,4Baseband

User #2

Baseband

User #4

^ p ^ ^

v ir

Optional

Controller KGV-11

Figure 2-3

A Basic TD-1271B/U Configuration

13

14

III. THE RE-ENGINEERING PROCESS

A. PROCESS PHASES

Re-engineering begins with the assembly of all resources of a software system.

This includes, but is not limited to the software source code, design documents, software

development folders, test reports, software trouble reports, sample inputs, sample outputs,

and, if practical, interviews of the implementers and/or maintainers. Typically the only

reliable source of information is the software source code and for that reason re-

engineering of an existing software system starts at the code level. The software

documentation, many times, are not kept current with the software; however, it can still

be a useful source of information and can be used as an engineering guide. The process

in which existing software is transformed into a new implementation can be described in

the Figure 3-1 [30].

Abstraction / /

Transformation

\ \ Re-Implementation

w

Design

///Implementation

V\Old Implementation New Implementation

Figure 3-1

The Re-Engineering And Implementation Process

15

There are three phases to the re-engineering process. The first phase, abstraction,

extracts the detailed design information from the documentation and the code. For those

familiar with MIL-STD-498, this is analogous to creating a Software Design Document

from the existing system. The second phase allows for the modification of the design by

adding, deleting, or modifying requirements. The third phase is a re-implementation of

the system. The focus of this thesis is the reverse engineering process that recovers the

design from the old implementation. This methodology will be validated by executing

the re-implementation of the recovered design using a different language and different

processor than the old implementation.

1. Phase One: Abstraction

In this phase, the documentation and code can be used to provide the information

needed to support the re-creation of the system design. Since the TD-1271

documentation has been shown to be unreliable, the source code will take precedence in

this phase with the documentation providing background information. The products

developed during abstraction are as follows [30]:

1

.

Structure Chart. This is a hierarchy of the modules as extracted from

the program where each node in the chart corresponds to a procedure or function

in the program. Since the goal of abstraction is to remove the language

dependencies from the code, it is important to treat library calls as part of the

system and include them in the structure chart. The language selected for the re-

implementation phase may not provide the same library services. Any language

dependent library calls may need to be manually re-implemented. The structure

charts for this thesis are based upon the structure charts identified in reference

[37]. The structure charts provide a visual representation of the software system

that is useful in determining organization and dependencies. This information,

once derived, is used to develop the structure charts for the enhanced system.

16

2. Module Description . This description is a combination of the module's

inputs, processing, and outputs, with the algorithms and constraints identified.

This description is produced for each module in the structure chart. In addition to

a narrative of the module's processing, a language independent form using a

specification language such as SPEC [42] or a Program Design Language (PDL)

is used to capture the requirements of the module. For this documentation to be

useful it is important to verify, through code reading, that the supporting

documentation is up-to-date. A case tool that allows this information to be tagged

to each element in a structure chart would be very helpful. One of the original

goals was to identify a tool to preserve this information as part of this thesis, but

due to budgetary considerations no tool was procured.

3. Data Flow Diagram . At a module level the data flow diagram shows the

flow of data between the modules. Within the module that the data flow diagram

is decomposed, showing at each successive decomposition level the

transformations that occur. This information is also used to develop the

algorithms that need to be documented when the design is re-implemented. These

algorithms can be described using mathematical notation, a Program Design

Language, or other notation. These algorithm descriptions are added to the

module description in step 2. The process consists of constructing the DFD of

level i+1 from level i. Each level explodes the data into transforms, data

repositories, and data flows [37]. Data repositories will be represented as boxes,

data transforms as circles, and data flows as connecting lines between transforms

and data repositories. The transforms are then used in phase 2 to develop the

detailed design.

4. Control Flow Diagram . This will identify the control structure of the

program between the modules. This information is used to identify the logical

relationships between the modules, verses the physical relationship described in

step 1 . [39] will be used to create this diagram.

17

5. State Transition Diagram. This will identify the states and modes in

which the software can reside and identify the events that cause a change in the

state of the software and the processing that is to occur due to the state change,

and will identify the modules active for each state. There may be more than one

state transition diagram depending upon the concurrency of the system. The

notation for this diagram will follow those in [39].

Once the design information has been extracted, the resulting recovered design is

reviewed for consistency. Any missing items of information should be investigated and

added to the recovered design [30]. While it is the goal of this first phase to extract the

design and leave behind the vestiges of the language and platform, the design may still

have an organizational structure that was due to the implementation language and

platform. Before entering phase two, the extracted design information can be modified to

refine the design for portability. For example, the TD1271B/U uses multiprocessors with

serial communications between them to perform the processing required. When the

system is re-engineered, it is anticipated that this system will be implemented using Ada

tasking on a single microprocessor. The detailed design should be abstract enough to

make this possible.

2. Phase Two

Phase one used the supporting documents and the code to extract the detailed

design information. This phase attempts to link the detailed design information with the

requirements through the use of a requirements traceability table. This table binds the

modules with the requirements that they partially or fully implement. This table will

need to support one to many and many to one. That is, one requirement may be spread

out over one or more modules and many requirements may be identified with one

module. Depending upon the state of the supporting documentation this can be an easy

task or a major effort. Requirements are needed if the system being reengineered is also

having the requirements modified as well. Once the requirements have been modified,

the modules affected need to be updated. It is not unusual at this phase to add and delete

18

modules from phase one. This phase is identified for completeness only; this thesis will

not attempt to construct a requirements traceability table.

The TD1271B/U was developed under DOD-STD-1679 and any re-engineering of

the TD1271B/U would use a tailored MIL-STD-498 approach. The purpose of the re-

engineering effort is to develop, using the existing resources of the project, those products

necessary to pass the exit criteria of the detailed design phase and allow the system to be

coded. The primary product that is developed during the detailed design phase is the

Software Design Document. When looking at the data item description (DID) the

following sections are used to provide the programmer with the information necessary to

code the system. From the re-engineering activities performed on the TD1271B/U in the

three phases described above, the following module information will be developed:

Module Name

Module Description

Constraints, Limitations, or Unusual Features in the Design

Special or Unique Algorithm Description

Called by

Calls

Triggering Event (tasks only)

Implicit Inputs

Explicit Inputs

Implicit Outputs

Explicit Outputs

Hardware Dependencies

Sizing and Timing

Informal Test Procedures

19

If computer aided design tools were used during phase two, such as the Computer-

Aided Prototype System (CAPS), much of the information needed for the SDD is

contained within the various reports that the tools produce.

3. Phase Three

At the completion of phase two the design of the current system has been

extracted. Before starting the re-implementation of the system for the new target

language and hardware, any changes to the design is done in this phase. This could be a

re-organization to take advantage of any special capabilities of the compiler or hardware.

In addition, this would be the time to modify the requirements of the system and fold

those changes into the design. Upon completion of this phase the design should reflect

the system as wanted by the customer.

4. Phase Four

The output of phase three is used in this phase. This is the coding of the extracted

and possibly modified design. The detail design is re-implemented using the desired

methodology (i.e. OOD, structured design, etc.) in the desired language for the desired

target platform. This phase is executed in the same manner as any new development.

20

IV. THE CASE STUDY

A. THE TD1271B/U MULTIPLEXER DATA BUFFERING PROCESSOR

The Data Buffer Processor (DBP) provides the elastic buffering required to pass

continuous data between the Systems Control Processor (SCP) and I/O ports while

transmitting or receiving data in bursts over the satellite channel. The heart of the DBP

consists of 24K bytes ofEPROM containing the software program. The program is a

loop structure which sequentially scans internal control points and the baseband users to

determine the actions is required. If, for example, a user terminal has entered a transmit

request at the baseband I/O port, a check is made of the port requirements, the port is

configured to receive data and the transmit acknowledge is sent to the baseband

device[43]. Figure 4-1 provides a block diagram of the relevant input and output signals

to the DBP. 4

B. DBP INPUT/OUTPUT SIGNALS

The DBP[49] data flow is described in Figure 4-1. Figure 4-1 is a description of

data and control signals that are input to or output from the DBP[49].

C. THE RE-ENGINEERING STRATEGY

One of the primary goals of this re-engineering effort was an attempt to use the

existing source code to extract the design of the system and to produce well designed,

portable code. Ada was used as the target language during the extraction process. Since

this software was originally written before the advent of structured design, we didn't

attempt to use an Object-Oriented Design approach, but used a structured design

approach.

4This listing is not complete for the TD1271. Certain hardware control lines are system dependent and

would not be applicable to this re-engineering effort.

21

BASEBAND USER

A A A A ATX TX XMIT TX SLOT SIG RX RX

DATA CLOCK REQ ACK TIME ACK CLOCK DATAMARK

v \r V

DBP MODULE

T

CLC

X)CK

1

TXCCOWRCCOW

r J

TXDATA

r i

A A A ARX RX RX STATUS

DATA CLOCK CCOWRCCOW

r

A ASTATUS RX TX PREAMBLE

STATUS STATUS CODECONTROL CONTROL

V

SCP MODULE STP MODULE

Figure 4-1

Inputs and Outputs To DBP Module

As outlined in Chapter 3, the first phase of the re-engineering effort is to develop

Structural Diagram s, Module Descriptions, Data Flow Diagrams, Control Flow

Diagrams, and State Transition Diagrams. The code was used to extract the structure,

control flow, and state transition diagrams. The documentation was used to develop the

module descriptions, provide a high level data-flow diagram and to verify the control

flow and state transition diagrams whenever possible.

1. Code review

As noted by T. Bigerstaff [10], a key objective of design recovery is to develop

structures that will enable a software engineer to understand the program. Our first step

in this process was to identify and partition the code into procedures. This proved to be a

task of greater difficulty that we had anticipated. Not only were we dealing with a

22

somewhat cryptic language, we were also faced with a coding style that extensively

utilized 'jump' and 'branch' commands to navigate from one set of instructions to

another. This programming style was intended to reduce the total size of the code by

reusing existing code rather than re-writing it. Programmers coding during this period of

time were highly praised if they could reduce the length of the overall program by even a

few bytes, regardless of the long term maintenance problems created.

2. Extracting the Structure

The first step was to extract the modules from the code. Modules were defined as

a section of code referenced in a Jump to Subroutine (JSR) or Branch to Subroutine

(BSR). Even though it was recognized early on that this effort would focus only on part

of the TD-1271 system it was important to extract the structure of the entire system to

identify the areas in which the rest of the re-engineering effort would focus.

The code for the three major sub-systems were examined and mapped using a

Microsoft Excel spreadsheet to record the results (see Appendix B - Subroutine Call

Tree). It should be noted that this Subroutine Call Tree is not complete. The TD-1271 is

not a procedural based design, that is it makes extensive use ofGOTO statements for

control between subroutines. The effort to extract the subroutine calls using the JSR/BSR

opcodes was sufficient to identify which sub-system to apply the more rigorous code

examination to. To produce the Subroutine Call Tree each file comprising the TD-1271

was opened in a word processor and a search was conducted on the words JSR and BSR.

At each occurrence the subroutine containing the call and the subroutine that was being

called were entered into the Subroutine Call Tree. Duplicate entries, the same subroutine

call from the same subroutine, were not noted. The Subroutine Call Tree contains 1 183

subroutine calls. After examining the results of this effort the Data Buffer Processor was

selected for further investigation.'fc1-

3. Extracting the Control Flow

In order to extract the control flow from the code it would be necessary to have

some sort of cross reference available to consult. There weren't any tools available to do

this so one was developed. A parser was written in Ada using an Alsys host compiler for

23

the IBM-PC. This parser uses two passes to build a cross reference for the labels in the

source code and a source code listing with line numbers. The first pass identifies each

label and the line of code where it is defined. The second pass identifies the line number

of code where each reference occurs. References to labels that are not found are reported

as errors. The only errors encountered were relative indexes based upon a label (e.g.

LABEL 1+2). The source code listing is in Appendix D and the Cross Reference Listing

is in Appendix E. There will be references to line numbers in the source code from

Appendix D later on.

A detailed examination of the DBP code identified the inter-subroutine control

flow and a disturbing software design methodology, or to be more accurate - lack of one.

As you can see by the control flow diagram, Figure 4-2, the designers used some

programming practices that made it very difficult to extract the control flow. The first

difficulty encountered was the use of multiple return from subroutine (RTS). Rather than

having one entrance and exit from the subroutine there were multiple exits. This was

further complicated by the use ofGOTO statements where a JSR was used to enter a

subroutine and both a RTS and a GOTO statement was used to return (IOIPT to IOILF

in Figure 4-2). There were subroutine calls where the called subroutine executed a

GOTO statement to pass control, not back to the caller, but to another routine (IOIPT -

IOILS - I02PT in Figure 4-2). There were manipulations of the return stack to short

circuit the return from a subroutine call (Appendix D, line numbers 1044-1045 and 1099-

1 100 in IOIPT and repeated for the other three channels). There are examples in which a

routine has multiple entrances and exits (Figure 4-3). The way this code was designed

made it extremely difficult to convert to Ada, and impossible to meet the goal of having

code that is well designed following this conversion. The result was becoming as poorly

designed as the original. As stated earlier, this software was designed prior to the

introduction of what is now considered modern programming standards. Design

decisions were made based more upon memory usage and execution speed than having a

system that was easy to maintain.

The subroutine IOIPT was examined for developing the inter-subroutine control

flow. This was based upon the conditional statements within the code. This inter-

24

h.

Start

iTDMA

1561 INIT

68

W

V

RBI195

STUFF4299*>>

tl BITRAT642TBI

692 SOFAA2914

VIOILF1065 IOIPT

984

LD11107

IOILS1030

<*. ^>

VI02LF

1511

^I02PT

1430

LD21553

w

I02LS1476

->

1 r

I03LF1968

I03PT1887

LD32010

I03LS1933

-**

1 r

I04LF2425

I04PT2344

LD42467

1

I04LS2390

J*

^ r

BSERV2801

SOFA2906

+SOF2883

^>

Subroutine call ^ ..

Return from Subroutine ;

Jump/Branch

LEGEND

>•

>-

VSOFAA

29141SIF3746

\ r

1

Figure 4-2

DBP Control Flow Diagram

25

TBI^JSR

RTSSOFAA ^ This subroutine call is in the middle

of the thread executed by SOF

SOFBSR SOFA

^ This subroutine call has a number of^

return points depending upon

conditional statements within the

... code.

RTS

The use of the jump instead of a

SOFA . . . <4 subroutine call makes conversion to

BEQ SOFAA Ada very difficult.

RTS

SOFAAJMP SOFY ^

Again, depending upon the outcome

^ of a conditional statement the return

. . . from subroutine can come from

RTS SOFAA or SOFY

SOFY

Figure 4-3

Multiple Entrances and Exits

subroutine control flow was found to be as difficult to convert as the intra-subroutine

control flow. The control flow for subroutine IOlA can be visualized with Figure 4-4.

As Figure 4-4 depicts, this would be an example of "spaghetti code". In order to

overcome this spaghetti code problem it became necessary to reduce the code to 'mini'

routines, adding 'jumps' to the end of each code fragment, so each fragment would be a

stand alone routine. Each fragment could then be moved at will to try to untangle the

subroutine's control flow. It too was far more difficult than it was worth. The result was

a subroutine that was poorly designed.

4. Data Flow

The data was analyzed to attempt to produce a data flow diagram. The primary

data flow used ringed buffers. The declared buffer started at its own starting address and

ended at the starting address of the next declared buffer (e.g. an index pointer was set to

26

I01A

J^* IOIY

I01AA\l/

IOIYB

IOIB

101 YD

I01YE I01YF

I01YEO <J^_

IOIYEI

I01XQ«£-

I01E

3EI01F

IOIFA

IOIYG

3EIOIYH

^e:

I01YI

3EIOIYJ

3_IOIYK

3EIOIYL

3LIOIYM

31IOIYN

~^7~

IO1Y0

I01YP

JLIOIYQ

<-

<^

<-

-3> I01YA

I01XP

2> I01CA

I01D

^_-> I01YC1

I01H

±.IOIHA

i^_

I01HB

~1T~

101 YA1

IOIO

IOIP

I01YC ^-

ion

3EIOIK.

iz:

ion

3EIOIK.

31IOIM

3HI01N2

31I01N3

I01N4

I01N5

JLI01N6101N9

lL1O1N10

I01G

Figure 4-4

101A Control Flow

27

the starting address of a buffer and was incremented until it equaled the starting address

of the next buffer). This hard coding is the easiest to overcome, but it is a glaring

example of the way the software written. These ringed buffers can be easily defined

using a ring buffer generic package in Ada where the data is inserted and extracted using

procedure and function calls. Error handling can be included to cover the cases of

underflow and overflow. The size of each buffer is then easily established during

elaboration based upon the size specified. It was determined that the best source of

information to establish a high level data flow diagram was the documentation. This data

flow is shown in Figure 4-1 . The data flow between the modules of the DBP are

primarily indirect by using data stores. It was decided that the effort to describe this data

flow was of little use and was not done.

D. USE OF THE TD-1271 AS AN ENGINEERING GUIDE

It was during the effort to establish the control and data flow diagrams that the

determination was made that the TD-1271 should be redesigned from the top down. The

source code as designed didn't support the re-engineering effort except as an engineering

guide during the redesign processes.

The interrupt handlers can be used to establish the tasks responsible for the input

and output of data to the DBP subsystem. While the modules are not suitable for re-

engineering, the organization of the main modules can be useful in partitioning the new

system. You can see by Figure 4-2 that there are four channels that are serviced in a

round robin method. The new system can also use this organization. The most valuable

asset the current TD-1271 has is by providing a system that works. A comparison

between the behavior of the system to various inputs and what is specified in the

documentation can give a good indication on the state of the documentation. It provides

a strong baseline between stimulus and response that can assist in the formation of the

new design.

E. DOCUMENTATION REVIEWAs was noted in the previous section, attempts to extract the requirements directly

from the code became a prohibitively tedious and difficult task. This left only the

28

original documentation with which to attempt to baseline the requirements. The primary

documentation available for the Data Buffer Processor program includes the Program

Performance Specification (PPS) [49], the Program Design Specification (PDS) [50].

Also available are the system level PPS [46] and PDS [47] for the TD1271B/U. The

factors and problems noted about documentation in Chapter I are evident in the

TD1271B/U's documentation, and bring it's overall accuracy into question. The

documents do however provide the basic requirements as they were known as late as

1987. It is these requirements that we shall briefly examine within this section relative to

the re-engineering plan detailed in Chapter III.

1. Phase One: Architecture Definition.

a. Structure Chart

The DBP PDS [50, page 3-1] provides a basic structure chart. This is

reproduced here as Figure 4-5. This structure chart does not include the modules for

initialization and setup.

b. Module Description

Module descriptions for the six 'run time' modules are provided in both

the PPS and in the PDS for the DBP. Setup and initialization are not specifically listed.

Briefly these six modules are:

1

.

Receive Burst Initialization Module (RBI) . This function

processes the receive burst notification from the System Timing Processor.

It initializes the DBP's hardware, the I/O ports flags and pointers, and the

Service Receive Burst FIFO function.

2. Transmit Burst Initialization Module (TBI) . This function

processes the receive burst notification from the System Timing Processor.

It initializes the DBP's hardware, the I/O ports flags and pointers, and the

Service Transmit Burst FIFO function.

29

Receive Burst

Initialization

Module

I/O Port

Service

Module

Transmit Burst

Initialization

Module

i

ik A

rr

•

i

Service

Receive Burst

FIFO Module

kInterrupt

Service

Module

wService

Transmit Burst

FIFO Module

P W

Figure 4-5

DBP High Level Structure Chart

3. I/O Port Service Module (IQ1PT-IQ4PT) . These four modules

services each of the four baseband ports. If the I/O Transmit Request

input is true, the DBP will accept I/O port data and store it in the port's

data buffer. If the I/O Transmit Request input is false and there is receive

burst data for the port, then the I/O port service will output this data from

the data buffer to the baseband equipment.

4. Service Receive Burst FIFO Module (SIFV This module inputs

receive burst channel data and stores it in the data buffer.

5. Service Transmit Burst FIFO Module fSOF) . This module

outputs the I/O port's transmit data from the data buffer to the burst

channel.

6. Interrupt Service Module (IRS) . This module communicates

with the System Control Processor. It receives I/O port bit rate and

connection status, and it receives/transfers orderwire messages on an

interrupt basis [49].

30

c. Dataflow

The Data Flow is somewhat more difficult to extract from the

documentation. By definition in the DOD-STD-1679A [51], the full definition of data

variables would be documented either in the Program Design Document or in the

Database Design Document. To date we have not found any reference to either of these

documents. It is our belief that they were tailored out of the documentation package for

the original development. This leaves some of the inputs and outputs listed in the DBP

PPS and PDS open to question as to their origin and content. Clearly this is an area

where it would be necessary to track the variables through out the code to ascertain their

design and functions. In addition to the program variables, there are an assortment of

Key Lines, Clocks, and Interrupts that need to be processed and input. Figure 4-1

provides a block diagram of the inputs and output from the DBP module.

d. Control/low

From the DBP PDS we were able to extract the basic control flow

diagram. This diagram (Figure 4.6) would provide the sequencing of tasks in the new

software module. It would also provide the basis for the modules for the Data Flow

diagram. In addition to this 'basic' control flow, there is also an Interrupt handling

module capable of stopping current processing and shifting control to another module.

2. Phase Two: Requirements Definition.

The second part of the re-engineering effort is to utilize the data gathered from the

first phase to develop requirements. The high level requirements can be easily extracted

from the module descriptions.

Rl : Will receive burst timing from System Timing Processor.

R2: Will initialize hardware and software flags and statuses

R3: Will input data from the Baseband ports and store.

R4: Will receive data from the channel and store.

R5: Will forward input data from storage to the channel.

31

r START ^\

u

INITIALIZATION ^̂

VRBI

INITIALIZE FOR RXBURST FROM CHANNEL

VTBI

INITIALIZE FOR TXBURST FROM CHANNEL

IIOxPT

I/O SERVICE FORPORTS 1,2, 3. THEN 4

^ r

SOFTX BURST SERVICE

TO CHANNEL

i r

SIF

RX BURST SERVICEFROM CHANNEL

Figure 4-6

Control Flow Diagram

J>Z

R6: Will output receive data from storage to the Baseband port.

R7: Will receive and transfer orderwires to and from the System Control

Processor.

R8: Will receive port status and connection information from the System

Control Processor.

From this point, development of more detailed requirements would progress along

normal development lines. The advantage that would be gained in this area would be the

ability to check the foundation of a requirement in the code. In this way the 'forward'

engineering effort would have a existing system to validate the responses against.

F. RECOMMENDATIONSEffort can be expended to convert the TD-1271 to a high order language and have

it run on any number of modern day processors. To do so without reengineering the

system from the top down will in effect doom this system to the same fate it has fallen to

today: unstructured and not maintainable.

One of the obvious recommendations would be to use a modern programming

language. Because of the use of ring buffers between the subsystems, a method that is

valid in a new design, Ada would be the best choice. This would allow the use of generic

packages to handle the buffers. Ada's tasking and the ability to tie the task's entry point

to a hardware interrupt would be another valuable feature that makes Ada the first choice.

The original thesis called for timing studies to be conducted on the re-engineered

code. Since the code never reached the state where these studies could be performed

there aren't any hard numbers to address. However, the current system runs on three

Motorola 6800 microprocessors. The increase in the processors throughput since the

Motorola 6800 introduction would give a good indication that the entire system could fit

on any number of modern day microprocessors. The hard real time requirement is

handling the input from the modem. This data is transmitted at a maximum rate of 1 6K

bits/second. Most real-time embedded applications use Wind River's VxWorks operating

system. This operating system allows the application to read a serial port with a variable

input size. The programmer specifies the file descriptor for the serial port, the address in

33

which the data is to be read, and the number of bytes to read. In addition, VxWorks

provides an optimized task switch for interrupt handlers that has the overhead of a

function call. Once the data has been read in the data is output as processed. By proper

scaling of the input data from the modem, the processing percentage spent on handling

the interrupt can be less than 10%. With these considerations our recommendation would

be either the Motorola 68040 or the Motorola Power-PC.

34

V. CONCLUSIONS

This thesis was originally planned to be a fairly straight forward application and

review of the re-engineering process. We very rapidly ran into problems of scope and

time. There is a tremendous amount of data written on the subject of re-engineering. The

re-engineering data not only covered software, but also included business, hardware, and

other re-engineering topics. The first problem we faced was separating out the relevant

topics. After narrowing* the scope to software re-engineering, we were still faced with a

daunting amount of information to review. We found a great deal of information

presented on the general theory of re-engineering, but very little concrete information on

the application of these theories. We were able to locate a methodology to try [30].

The first phase of this methodology is the extraction of data from the existing

code. As noted by Byrne (30), tool support for this portion is a major necessity. With

appropriate tools it is possible to statically analyze and document an extensive program in

a relatively short period of time. He estimates a 150 to 1 time ratio difference between

manual analysis to an automated tool approach. Based on our experience, we would

concur with this evaluation. We were unable to locate any tool support to automate the

extraction of basic calling trees or other data from the legacy system we were looking at.

Although some were found for high order languages, there were very few listings for any

Assembly language, and none of these were for the Motorola 6800. This we believe will

be prevalent in most legacy systems. Most of the legacy systems will be in some form of

Assembly language, but there are not enough in any one language to make it

commercially feasible to develop a tool to automate this portion of the re-engineering

process.

When faced with poorly designed software it is important to start the re-

engineering work at the lowest level in which the design is masked. For example, the

preliminary design may be adequate and it was in the execution of the design that the

poor design decisions were made. However, it is more likely that the designers, knowing

the constraints of the environment in which they have to operate, like available memory,

35

will design to make optimum use of the resources available. There are examples in which

the software was written with self-modifying code in order to recover memory space used

for initialization as scratch pads for data. However, when re-engineering the system these

type of design decisions need to be abandoned and the software needs to be designed to

the standards of the times.

With the TD-1271, a tremendous amount of time was used in just trying to

understand and decipher the source code. The software, with little or no comments (see

Appendix D) and poorly designed control structure, cannot be recommended for re-

engineering. Time and effort could be expended to re-engineer the source code: It's not

an impossible task, but it is not cost effective. Nor would the result have enhanced the

supportability of the software.

The only reasonable approach for the TD1271B/U would be to start at the

requirements documentation, establish a testing criteria for each requirement, and

perform those tests on the existing system. These tests would demonstrate if there have

been modifications to each requirement that would warrant further investigation to

determine the current state of that requirement. Once the modifications to the

requirements have been made and a suitable target system identified, the task of re-

writing the software would be considered a small to medium effort when weighed against

current Navy communications systems currently under development.

36

APPENDIX A

BIBLIOGRAPHY

1 "A Conceptual Foundation for Software Re-engineering", E. Byrne, IEEE 0-8186-

2980-0/92

2 "A Framework for Reverse Engineering DoD Legacy Information Systems'", P. Aiken,

A. Muntz. R. Richards, IEEE 0-8186-3780-3/93

3 "A Software Re-engineering Process Model", E. Byrne, D. Gustafson, IEEE 0730-

33157/92

4 "A Suzuki Class in Software Reengineering", Kozaczynski,-Wojtek, IEEE-Software,

v. 8 Jan. '91 p. 97-8

5 "An Economic Model to Estimate Software Rewriting and Replacement Times",

Chan,-Taizan; Chung,-Siu-Leung; Ho,-Teck-Hua, IEEE-Transactions-on-Software-

Engineering. v. 22 Aug. '96 p. 580-98

6 "Analyzing Empirical Data from a Reverse Engineering Project", P. Fiore, F.

Lanubile, and G. Visaggio, IEEE 0-8186-71 1 1-4/95

7 "Automated Support of Software Maintenance", K. Bennett, Information AndSoftware Technology, 33(l):74-85, Feb. 1991

8 "Cash Cow in the Tar Pit: Reengineering a Legacy System", W. Adolph, IEEE

Software, May 1996

9 "Concept of the Re-engineering Life-Cycle", J. Manzella, B. Mutafelija, IEEE 0-8186-

2697-6/92

10 "Design Recovery for Maintenance and Reuse", T. Biggerstaff, Computer, July '89

11 "DoD Legacy Systems; Reverse Engineering Data Requirements", Aiken,-Peter;

Muntz,-Alice; Richards,-Russ, Communications-of-the-ACM. v. 37 May '94 p. 26-41

12 "Improving Software Maintenance Through Measurement", Rombach,-H.-Dieter;

Ulery,-Bradford-T,

Proceedings-of-the-IEEE. v. 77 Apr. '89 p. 581-95

13 "Investigating Reverse Engineering Technologies for the CAS Program Understanding

Project", Buss,-E; De-Mori,-R; Gentleman,-W.-M, IBM-Systems-Joumal. v. 33 no3

'94 p. 477-500

14 "Mandrake: A Tool for Reverse-Engineering IBM Assembly Code", P. Morris, R.

Filman, IEEE Proceedings of WCRE '96

15 "Measurement: the key to application development quality", Walrad,-C; Moss,-E,

IBM-Systems-Journal, v. 32 no3 '93 p. 445-60

16 "Planning the Reengineering of Legacy Systems", Sneed, Harry M., IEEE Software v

12 n 1 Jan 1995

17 "Program and Interface Slicing for Reverse Engineering", J. Beck D. Eichmann, IEEE

0270-5257/93

18 "Pros and Cons of Reverse Engineering", http://www.tailormade.com

19 "Recovering Design and Specifications from Source Code", Prywes,-Noah, IEEE-

Software, v. 13 Nov. '96 p. 109-1 1 +

20 "Reengineeing Procedural Into Data Flow Programs", P. Newcomb, IEEE 0-8186-

7111-4/95

21 "Reengineering Definitions", http://www.stsc.hill.af.mil

22 "Retrieving Information from Data Flow Diagrams", G. Butler, P. Grogono, R.

Shinghal, I. Tjandra, IEEE 0-8186-71 1 1-4/95

23 "Reverse Engineering and Design Recovery: A Taxonomy", E. Chlkofsky. J. Cross II,

37

IEEE Software, Vol. 7, No. 1 Jan. 1990

24 "Reverse Engineering Programs via Dynamic Analysis", H. Ritsch, H. Sneed,

Proceedings ofWCRE '93

25 "Reverse Engineering through Formal Transformation: Knuths 'Polynomial Addition'

Algorithm", Ward,-M.-P, The-Computer-Journal, v. 37 no9 '94 p. 795-813

26 "Reverse Engineering: Algorithms for Program Graph Production", Cimitile,-Aniello;

De-Carlini,-Ugo, Software:-Practice-and-Experience. v. 21 May '91 p. 519-37

27 "Software Measurement: A Necessary Scientific Basis", Fenton,-Norman, IEEE-

Transactions-on-Software-Engineering. v. 20 Mar. '94 p. 199-206

28 "Software Reengineering: A Quick History", R. Arnold, Communications of the

ACM, May 1994

29 "Software Reengineering: Context and Definitions", R. Arnold, Software

Reengineering, IEEE Computer Society Press, 1993. Pp. 25

30 "Software Reverse Engineering: A Case Study", Byme,-Eric-J, Software:-Practice-

and-Experience. v. 21 Dec. '91 p. 1349-64

31 "The Evolutionary Growth of Software Reengineering and the Decade Ahead", W.

Ulrich, American Programmer, Oct 1990, pp 14-20

32 "Using an Enabling Technology to Reengineer Legacy Systems", Markosian,-

Lawrence; Newcomb,-Philip; Brand,-Russell, Communications-of-the-ACM. v. 37

May '94 p. 58-70

"Using Data Abstraction to Guide the Restructuring of FORTRAN". R. Ellis, L. Liu,

Class handout - source unknown

34 "Using Informal and Formal Techniques for the Reverse Engineeing of C Programs",

G. Gannod, B. Cheng, IEEE Proceedings ofWCRE '96

35 "Using metrics to evaluate software system maintainability", Coleman,-Don; Ash,-

Dan; Lowther,-Bruce, Computer, v. 27 Aug. '94 p. 44-9

36 Untitled reverse engineering article, R. Waters, E. Chikofsky, Communications of the

ACM, May 1994

37 "A Reverse Engineering Methodology to Reconstruct Hierarchical Data Flow

Diagrams for Software Maintenance", P. Benedusi, A. Cimitile, U. De Carlini,

Proceedings of the IEEE Conference on Softwar Maintenance, Oct 1998, pp 180-189

38 A Method for Re-Engineering in Structured Programs", A. Hevner, R. Linger, 22 nd

Annual Hawaii International Conference on System Sciences, 1989, p. 1025-1034

39 "Object-Oriented Modeling and Design", J. Rumbaugh, M. Blaha, W. Premerlani, F.

Eddy, W. Lorensen, Prentice Hall, 1991.

40 "Re-3' Re-Engineering , Restructuring, Reverse Engineering Part 1", E. Yourdon,

American Programmer, Vol 2, No. 4, Apr 1989 p. 3-10, reprinted in R. Arnolds

"Software Reengineering" IEEE Computer Society Press, 1992.

41 "A road map guide to Software Reengineering Technology", R. Arnold, Software

Reengineering IEEE Computer Society Press, 1992.

42 "Software Engineering with Abstractions", Berzins and Luqi, Addison-Wesley

Publishing Company, 1991

43 EE163-GA-OMI-010/E106-TD1271B, Operation And Maintenance Instructions,

Organizational Level, Multiplexer TD-1271B/U, Change 2 dtd 07 June 1994,

44 FSCS-21 1 74, Command And Staff Manual For The UHF DAMA Subsystem, dtd 19

April 1985

45 FSCS-21 1-24-1 Revision A, UHF Demand Assigned Multiple Access (DAMA)Systems Interface Design Specification For The UHF Satcom Satellite Waveform, dtd

15 January 1985

46 FSCS-21 2- 16 Revision D, UHF DemandAssigned Multiple Access (DAMA) System TD-1271B/U Multiplexer Program

Performance Specification, dtd 01 September 1987

38

47 FSCS-2 12-17 Revision A, UHF Demand Assigned Multiple Access (DAMA) Systesm

TD-1271B/U Multiplexer Program Design Specification, dtd 01 September 1987

48 FSCS-212-26-2 (CH-1), Interface Control Document For The TD-1271B/U

Multiplexer (Distributed Control Mode), dtd 30 September 1990

49 FSCS-2 12-7 Revision A, UHF Demand Assigned Multiple Access (DAMA) Systesm

TD-1271B/U Multiplexer Program Performance Specification Data Buffer Processor,

dtd 1 5 May 83

50 FSCS-2 12-8 Revision A, UHF Demand Assigned Multiple Access (DAMA) Systesm

TD-1271B/U Multiplexer Program Design Specification Data Buffer Processor, dtd 01

September 1987

51 DOD-STD-1679A(Navy) Military Standard Software Development, dtd 22 October

1983

39

40

APPENDIX B

TD-1271B/U SUBROUTINE CALL TREE

Module Name Located in Is Called by Located in

O.X FPANEL FP

SRX STPV06

STXO STPV06

ACK_CC_RCCOW PRECLA EXAM_CCOW_OVRHED PRECLAADJUST_FCOUNT_GS GS DBP_MSG_INTRPRT DCEXEC

DBPMSGJNTRPRT PREALTEXAM_CCOW_OVRHED PRECLA

ALARM_ON_GS GS FPANEL FP

BEEP_ALARM_GS GSALPHA_ONOFF_A_GS GS FPANEL FP

GLIST_DISPLY_FP FP

RECALL_FP FP

DC_HOME_FREQ_FP FP

AC_HOME_FREQ_FP FP

QUEUE_TIME_FP FP

CMDJRJESPONSEJFP FP

FREQ_TO_DSPLY_FP FP

KG_TIME_TO_DSPLY FP

STATUS_RPT_B_FP FP

ZEROIZE_FP FP

CONFER_CALL_FP FP

INFOJREQUESTJFP FP

PAGING_REQ_FP FP

KG_MEM_CHANGE_FP FP

CONFIG_CODE_FP FP

DISP_INFO_REQ_GS GSLAMP_TEST_GS GSLNK_TST_RES_GS GSERR_GS GSSHOWJPORTJ3S GS

ALPHA ONOFF B GS GS FPANEL FP

INFO_REPORT_FP FP

R£CALL_FP FP

ZEROIZE_FP FP

PORT RELEASE FP FP

DC_HOME_FREQ_FP FP

AC_HOME_FREQ_FP FP

SELECT_PORT_FP FP

PREC ENTER FP FP

KG_MEM_FILL_FP FP

INFO_REQ_CHK_FP FP

EXIT_FP FP

LINK_TEST_REQ_FP FP

CALL_COMPLETE_FP FP

CHANCONTROLFP FP

OUT OF SERV FP FP

TO PARITY GALL FP FP

FORMAT_FREQ_FP FP

CONFER CALL FP FP

KG_TIME_FP FP

41

Module Name Located in Is Called by Located in

ALPHA ONOFF B GS GS CALL_CANCEL_FP FP

rNFO_REQUEST_FP FP

PAGING_REQ_FP FP

KG MEM CHANGE FP FP

STG_CONTROL_FP FP

CONFIG_CODE_FP FP

ALPHA ONOFF B GS GS LNK_TST_RES_GS GSCALL_CC_GS GSDISP_FCNT_GS GS

AUDIO ALARM 01 FP FPANEL FP

AUDIO ALARM 02 FP INFO_REQ_CHK_FP FP

AUDIO ALARM OFF FP FPANEL FP

KG_MEM_FILL_FP FP

BCD TO BIN GS GS INFO_REQUEST_FP FP

YZ_TO_BrN_FP FP

AC_HOME_FREQ_FP FP

VWXYZ_TO_BrN_FP FP

BCD TO YZ FP FP FPANEL FP

FREQ_TO_DSPLY_FP FP

DC_HOME_FREQ_FP FP

BEEP ALARM GS GS FPANEL FP

INFO_REPORT_FP FP

PORT_RELEASE_FP FP

DC_HOME_FREQ_FP FP

AC_HOME_FREQ_FP FP

SELECT PORT FP FP

PREC_ENTER_FP FP

KG_MEM_FILL_FP FP

CMD_RESPONSE_FP FP

PRE_DCKA_CHK_FP FP

CHAN_CONTROL_FP FP

LFNK_TEST_REQ_FP FP

ZEROIZE_FP FP

STATUS RPT B FP FP

CALL_COMPLETE_FP FP

OUT OF SERV FP FP

TO_PARITY_CALL_FP FP

FORMAT_PARITY_FP FP

CONFER_CALL_FP FP

KG_TIME_FP FP

CALL_CANCEL_FP FP

INFO_REQUEST_FP FP

PAGING_REQ_FP FP

EXTEND_XMIT_FP FP

KG_MEM_CHANGE_FP FP

STG CONTROL FP FP

CONFIG CODE FP FP

PORT DETECT GS GSLNK_TST_RES_GS GSERR GS GS

BfN TO BCD CL GS GS FPANEL FP

DC_HOME_FREQ_FP FP

AC_HOME_FREQ_FP FP

QUEUETIMEFP FP

DISCOTIME_DISPLAY FP

FREQ_TO_DSPLY_FP FP

KG_TIME_TO_DSPLY FP

42

Module Name Located in Is Called by Located in

BIN TO BCD GS GS FPANEL FP

RECALL FP FP

INFO_REQ_CHK_FP FP

FREQ_CODE_CHK_FP FP

GLIST DISPLY FP FP

LNK TST RES GS GSBIT_RATE_FIND DCMOW CALL_REQUEST DCMOWBITE CLEAR DCMOW RRUJNTRPRT DCMOW

CALLREQUEST DCMOWDATAXFER DCMOWGLIST_DISP DCMOWCALL_COMPLETE DCMOWINFO_REPORT DCMOWRRU_INTRPRT PREINTRRU_STATUS_RPTB PREINTDATA_XFER PREINTGLIST_DISPLAY_05 PREINTCALL_COMPLETE PREINTRRU_PRTY OUT_05 PREPWTINFO_REPORT_05 PREPWTCALL_REQ_05 PREPNTCONFIG_ENTRY_05 PREINTRRU_CALLCAN_05 PREFNTGLIST_ENTDEL_10 PREINTPAGING_RCOW PREINTCONF_REQUEST PREINT

BITRAT |DBPV4 RBIJ DBPV4RBIT DBPV4

BLINK_SCULITE_GS GS EXEC_DCEXEC DCEXECEXEC_PREALT PREALTCHECKSUM_CHK_GS GS

BRX STPV06 CONFIG STPV06

BSB STPV06 EXEC STPV06

PSA STPV06

BTX STPV06 CONFIG STPV06

CALC PARITY GS GS XFER_CCOW_TO_DBP DCEXECIN_CCOW_FROM_DBP DCEXECENCRYPT CCOW DCEXECDECRYPT_CCOW DCEXECXFER_RCOW_DBP_GS GSDECRYPT_RCOW_GS GSREAD DBP RCOW GS GSENCRYPT_RCOW_GS GSIN_CCOW_FROM_DBP PREALTENCRYPT_CCOW PREALTDECRYPT CCOW PREALTXFER_OW PREALT

CALL CC GS GS PORTDETECTGS GSCALL_COMPLETE_FP FP JUMP_COMPLETE_GS GS

CALL_QUE_UPDATE PREINT CALL_fN_QUE_ACK PREINT

CALL_IN_QUE PREINT

CALL_REQ_DCMOW FP CALL_REQUEST DCMOWr

TO_PARITY_CALL_FP FP

CC EXEC DCCNTR DCCNTR EXEC_DCEXEC DCEXECCC_EXEC_PRECLA PRECLA EXEC_PREALT PREALT

43

Module Name Located in Is Called by Located in

CCOW INTP DCMOW DCMOW EXEC_DCEXEC DCEXECUSEREXEC DCEXEC

CCOW INTP PREINT PREINT USEREXEC PREALTCHECK A RANGE DCMOW/PREINT PORT_DISCONNECT DCMOW

PORT_DISCONNECT PREINT

CHECK B RANGE PREINT PORT_DISCONNECT DCMOWPORTDISCONNECT PREINT

CHECK_C_RANGE DCMOW/PREINT PORTDISCONNECT DCMOWPORTDISCONNECT PREFNT

CHECKSUM_CHK_GS GS INITJDCEXEC DCEXECPNIT PREALT

CHK FRAME COUNT PRECLA FRAME_CHK_PRECLA PRECLACHK GLIST PREINT SLOT_DISCONNECT PREINT

CALL_WAITPNG PREINTHOME_CHAN_CHANG PREINTSLOT_CONNECT PREINTFORMAT_CHANGE PREINT

CLEAR DBPV4 PWRON DBPV4SETUP DBPV4

CLEAR CONT COUNT PREFNT BUSY_ACK PREINT

CALL_PN_OUE_ACK PREINTUSER_OUT_ACK PREINTCALLBACK PREINT

CLEAR_DISP_GS GS FPANEL FP

SHOW_PORT_GS GSCLEAR_GNUM PREINT RPT_GLIST1 PREINT

RPT_GLIST2 PREPWTRPT_GLIST3 PREINTRTP_GLIST4 PREINT

CLEARGUARDJJST DCMOW FRAME_FMT_UPDATE DCMOWCLEAR_LITES_TIME PREINT CALL_CANCEL PREPNTCLEAR_QUE_TIME PREINT SLOT_CON_UPDATE PREINT

RRU_CALLCAN_15 PREINTCLEAR_SLOTS_GS GS PORTDISCONNECT DCMOW

CHAN_CONTROL_FP FP

STATUS_PRECLA PRECLAZEROIZE PREINTPORT_DISCONNECT PREINT

CLR_RRU_05 PREALT RRU_MSG_UPDATE DCEXECCLR_RRU_PREC_DSP DCEXEC/PREALT RRU_MSG_UPDATE DCEXEC

RRU_MSG_UPDATE PREALTCLRTIM PREPNT BUSY_ACK PREINT

USER_OUT_ACK PREPNTSLOT_CON_UPDATE PREINT

CALL_CANCEL PREINTPARTY_OUT_OF_SYNC PREINT

44

Module Name Located in Is Called by Located in

CMD RESPONSE FP FP ZEROIZE FP FP

INFO_REPORT_FP FP

TO PARITY CALL FP FP

FORMATFREQFP FP

CONFER_CALL_FP FP

DC_HOME_FREQ_FP FP

AC_HOME_FREQ_FP FP

KG_TIME_FP FP

INFO_REQUEST_FP FP

GLIST_ENTER_FP FP

PAGING_REQ_FP FP

KG_MEM_CHANGE_FP FP

GLIST_DELETE_FP FP

STG_CONTROL_FP FP

CONFIG_CODE_FP FP

CHAN_CONTROL_FP FP

COMMAND_FRAME PREINT CCOW_INTP_DCMOW DCMOWCCOW INTP 05 PREINT

COMP_FRAME_GS GS FRAME_CHK_DCCNTR DCCNTRFRAME_CHK_PRECLA PRECLAMASTER_FRAME PREINT

CONFIG_CODE_GS GS INFOREQCHKFP FP

CONS STPV06 CONFIG STPV06CONT_CHK_PREINT PREINT RCOW_PREP_XMIT PREALT

CLEAR_CONT_COUNT PREINTREAD_CALL_ACK PREINT

CORRECT_ONE_BCD GS BCD_TO_BIN_GS GSCORRECT TWO BCD GS BIN_TO_BCD_GS GSCYCLELITES_DCMOW DCMOW ZEROIZE DCMOW

TS_PREP DCMOWINFO_REQUEST_GS GS

DBP_MSG_INT_30 DCEXEC/PREALT EXEC PREALT PREALTDBP_MSG_rNT_35 DCEXEC/PREALT EXEC_DCEXEC DCEXECDBP MSG PNTRPRT DCEXEC/PREALT USEREXEC DCEXEC

USERPREAC DCEXECUSERPREAC PREALTUSEREXEC PREALT

DCKPORTOFFGS |GS INFO_REQUEST_GS GSPORT_DETECT_GS GS

DECODEFP |FP FPANEL FP

KG_MEM_FILL_FP FP

DECRYPT_CCOW |DCEXEC/PREALT DBP_MSG_rNTRPRT DCEXECDBP_MSG_INTRPRT PREALT

DECRYPT RCOW GS GS DBP_MSG_INTRPRT DCEXECDBP_MSG_INTRPRT PREALT

DEL_FROM_GLIST |PREINT DELET GUARD LIST PREINTGLIST_ENTDEL_30 PREINT

DELAY TOGGLE GS GS STATUS_DCCNTR DCCNTRCC_EXEC_PRECLA PRECLARCVCCOWBLOCK PRECLASTATUS_PRECLA PRECLA

DID STPV06 RNGEXC STPV06LTEXEC STPV06

45

Module Name Located in Is Called by Located in

DISCO_SLOT_CHK DCMOW/PRErNT CHECK_A_RANGE DCMOWCHECK_B_RANGE DCMOWCHECK_C_RANGE DCMOWCHECK_A_RANGE PREINTCHECK_B_RANGE PREINTCHECK_C_RANGE PREINT

DISCOTIME DISPLY FP FPANEL FP

RECALL_FP FP

DISP FCNT GS GS ZEROIZE_FP FP

CHAN_CONTROL_FP FP

DC_HOME_FREQ_FP FP

AC_HOME_FREQ_FP FP

SELECTPORTFP FP

CALL_COMPLETE_FP FP

STATUS_RPT_B_FP FP

GLIST_DISPLY_FP FP

LINK_TEST_REQ_FP FP

rNFO_REPORT_FP FP

TO_PARITY_CALL_FP FP

FORMAT_FREQ_FP FP

CONFER_CALL_FP FP

KG_TIME_FP FP

CALL_CANCEL_FP FP

INFO_REQUEST_FP FP

GLIST_ENTER_FP FP

PAGING_REQ_FP FP

KG_MEM_CHANGE_FP FP

GLIST_DELETE_FP FP

STG CONTROL FP FP

CONFIG_CODE_FP FP

OUT_OF_SERV_FP FP

LNK_TST_RES_GS GSDISP_INFO_REQ_GS GS FPANEL FP

DISP VWXYZ GS GS FPANEL FP

RECALL FP FP

LNK_TST_RES_GS GSDISPLAY_EEEEE_GS GS GLIST_DISPLY_FP FP

ERRGS GSDISPLY_TO_BCD_GS GS FORMAT_FREQ_FP FP

AC_HOME_FREQ_FP FP

VWXYZ_TO_BIN_FP FP

YZ_TO_BrN_FP FP

WX_TO_BCD_FP FP

YZ_TO_BCD_FP FP

CONFIG_CODE_FP FP

ENCRYPT CCOW DCEXEC/PREALT EXEC_DCEXEC DCEXECEXEC_PREACT PREALT

ENCRYPT RCOW GS PREALT RCOW_PREP_XMIT DCEXECRCOW PREP XMIT PREALT

EQUIPLED_REDO FP FPANEL FP

46

Module Name Located in Is Called b\ Located in

ERR_GS GS ZEROIZE_FP FP

INFO_REPORT_FP FP

TO_PARITY_CALL_FP FP

FORMAT_FREQ_FP FP

CONFER CALL FP FP

KG TIME FP FP

INFO_REQUEST_FP FP

GLIST_ENTER_FP FP

PAGING_REQ_FP FP

EXTEND_XMIT_FP FP

GLIST DELETE FP FP

GLIST DISPLAY FP FP

EVEN_PORT_STORE PREINT RRU_STATUS_RPTB PREINTEXAM_CCOW_OVRHED PRECLA RCV_CCOW_BLOCK PRECLAEXIT FP FP TIMECHKDCCNTR DCCNTRFIND_GLIST PREINT ENTER_GUARD_LIST PREINT

DELET_GUARD_LIST PREINTFIND_GLIST_05 |PREINT GLIST_DISPLAY_05 PREINT

GLIST_ENTDEL_10 PREINTGLIST_ENTDEL_30 PREINT

FIND_PREMPT_ADR PREINT PREMPTCOUNT_REDO PREINTSLOT_CON_UPDATE PREINTRRU_DISCO PREINT

FIND_RRU_BUF_GS |GS SETUP1 DCMOWCALLREQUEST DCMOWLITES_OFF_DCMOW DCMOWDATA_XFER DCMOWLNK TST LAMP GS GSLNK TST RES GS GSRRU_ACPT_ON_GS GSINFO_REQUEST_GS GSRRU_DISCO PREINTR£AD_CALL_ACK PREINTCALL_IN_QUE_ACK PREINTUSER_OUT_ACK PREINTRRU_OUT_ADR PREINTSLOT_CON_UPDATE PREINT

CALL_CANCEL PREINTCALL_WAITING PREINT

CALL_IN_QUE PREINTCCOW_DATA_XFER PREINTPARTY_OUT_OF_SVC PREINT

LITES OFF PREINT PREINT

RRU_CALL_CAN_05 PREINTDATA_XFER PREINT

FIND RRU_QUE PREINT DEDICATEDSLOT PREINT

BUSY_ACK PREINT

CALL_WAITING PREINTFIND_RCOW_QUE PREINT

CALL_QUE_UPDATE PREINT

FIND_RRUQUE_ADR PREINT OUT_SVC_UPDATE PREINTCLEAR_QUE_TIME PREINT

47

Module Name Located in Is Called by Located in

FIXA GS GS FPANEL FP

CONFER_CALL_FP FP

QUEUE_TIME_FP FP

DISCOTIME_DISPLAY FP

KG_MEM_FILL_FP FP

FR£Q_TO_DSPLY_FP FP

PAGING_REQJFP FP

KG_MEM_CHANGE_FP FP

LINK_TEST_REQ_FP FP

FIXAB_GS GSFIXAB GS GS FPANEL FP

SHOW_YZ_GS GSSHOW_WX_GS GSFIXA_GS GS

FIXB_GS GS QUEUE_TIME_FP FP

DISCOTIME_DISPLAY FP

CMD_RESPONSE_FP FP

FREQ_TO_DSPLY_FP FP

DISPLY_TO_BCD_GS GSFMT_GLIST_RCW_05 PREINT SET_GLIST_PTR PREINTFMT_GLIST_RCW_15 PREINT SET_GLIST_PTR PREINTFMT_GLIST_RCW_40 PREINT SET GLIST PTR PREINTFMT_GLIST_RCW_55 PREINT CLEAR GNUM PREINTFORMATUPDATE PREINT FORMAT CHANGE PREINTFORMAT GLIST RCW PREINT RPTGLIST1 PREINTFP RCOW DCEXEC/PREALT USEREXEC DCEXEC

USERPREAC DCEXECUSERPREAC PREALTUSEREXEC PREALT

FPANEL FP FP USEREXEC DCEXECUSERPREAC DCEXECUSEREXEC PREALTUSERPREAC PREALT

FRAME_CHK_DCCNTR DCCNTR USEREXEC DCEXECUSERPREAC DCEXECDBP MSG INTRPRT DCEXEC

FRAME_CHK_PRECLA PRECLA USEREXEC PREALTUSERPREAC PREALTDBP_MSG_rNTRPRT PREALT

FRAME_FMT_UPDATE DCMOW MASTER_FRAME DCMOWFREEZE_DISPLAY FP FORMAT_FREQ_FP FP

DC_HOME_FREQ_FP FP

KG_TIME_FP FP

KG_MEM_CHANGE_FP FP

FREQ_CODE_CHK_5 FP KG_TIME_FP FP

FREQ_CODE_CHK_FP FP FORMAT _FREQ_FP FP

DC_HOM :_FREQ_FP FP

FREQ_TO_DSPLY_FP FP FORMAT_FREQ_FP FP

FSLOT STPV06 SRX STPV06

GET_RANDOM_NR_GS GS RCOW_PREP_XMIT PREALTCOMP_RRU_PREC PREINT

48

Module Name Located in Is Called by Located in

GETRCOWADRGS GS DATA_XFER DCMOWINFO_REQUEST DCMOWANY_MSG_IN_QUE DCMOWFRAMECHKPRECLA PRECLARRU_STATUS_RPTB PREINTDATA_XFER PREINTCALL_COMPLETE PREFNTRRU_PRTY_OUT_05 PREINTINFO REPORT 05 PREINTRRU_CALLCAN_05 PREINTRRU_CALL_CAN_15 PREINTPAGING_05 PREINTFIND_RRU_QUE PREINTANY_MSG_IN_QUE PREINTCONFIRLISTRTP PREINTDEDICATEDSLOT PREINTCLRTIM PREINTCALL_REQ_05 PREINTCONF_REQ_05 PREINT

GET_RRU_INADR_GS GS RRUJNTRPRT DCMOWCALL_REQUEST DCMOWDATA-XFER DCMOWGLISTDISP DCMOWCALLCOMPLETE DCMOWINFO_REQUEST DCMOWRRU_INTRPRT PREINTCONF_REQUEST PREINTCALL_REQUEST PREINTRRU_STATUS_RPTB PREINTDATA_XFER PREINTGLISTJMSPLAY PREINTCALLCOMPLETE PREINTRRU_PRTY_OUT_05 PREINTINFO_REPORT PREINTRRU_CALL_CANCEL PREINTGLIST_ENTR_DEL PREINTGLIST_ENTDEL_05 PREINTPAGING_RCOW PREINTCONFIG_ENTRY PREINT

GET_TIME_CODE FP OUT_OF_SERV_FP FP

CONFER_CALL_FP FP

GLIST_COMPARE |PREINT GLIST_DISP_05 PREINTCHKGLIST PREINT

GLISTCOUNTER |PREINT ENTERGUARDLIST PREINTGLIST_ENTDEL_10 PREINTGLIST_ENTDEL_30 PREINTDELET_GUARD_LIST PREINT

HI_GUARD_CHK_FP |FP ZEROIZEFP FP

INFO_REPORT_FP FP

TO_PARITY_CALL_FP FP

CONFER_CALL_FP FP

INFO_REQUEST_FP FP

GLIST_ENTER_FP FP

PAGING_REQ_FP FP

IN CCOW FROM DBP DCEXEC DBPMSGJNTRPRT DCEXECDBP_MSG_INTRPRT PREALT

49

Module Name Located in Is Called by Located in

INFO REPORT FP FP CALL_CC_GS GS

INFO_REQ_05_GS GS HOME_CHAN_05 PREINT

rNFO_REQ_CHK_45 FP SELECT_PORT_FP FP

INFO_REQ_CHK_50 FP PORT_RELEASE_FP FP

INFO_REQ_CHK_FP FP FPANEL FP

INIT PREALT/DBPV4 (LABEL) PWRON DBPV4TDMA DBPV4

FNITIAL ENTRY PREINT RRU_STATUS_RPTB PREINTDATA XFER PREINTCALL_COMPLETE PREINTRRU_PRTY_OUT_05 PREINTINFO_RPT_05 PREINT

RRU_CALL_CAN_15 PREINTPAGING_05 PREINTSTATUS_RPT_A PREINTLINK_RESULT PREINTFORMAT GLIST RCW PREINTCALL_REQ_05 PREINTCONF_REQ_05 PREINT

IOILF DBPV4 IOIA DBPV4IOILS DBPV4 IOIA DBPV4I02LF DBPV4 I02A DBPV4I02LS DBPV4 I02A DBPV4I03LF DBPV4 I03A DBPV4I03LS DBPV4 I03A DBPV4I04LF DBPV4 I04A DBPV4I04LS DBPV4 I04A DBPV4JUMP COMPLETE GS GS DCKPORTOFF_GS GSJUMP SELECT 1 GS GS DCKPORTOFF_GS GS

SHOW PORT GS GSCALL_CC_GS GS

JUMP SELECT 2 GS GS DCKPORTOFFGS GSSHOW PORT GS GSCALL_CC_GS GS

KB TIME INIT GS GS ZEROIZEFP FP

OUT OF SERV FP FP

STATUS_RPT_B_FP FP

GLIST DISPLY FP FP

LINK_TEST_REQ_FP FP

INFO_REQUEST_FP FP

TO PARITY CALL FP FP

CONFER CALL FP FP

CALL_CANCEL_FP FP

rNFO_REQUEST_FP FP

GLIST ENTER FP FP

PAGING_REQ_FP FP

CONFIG CODE FP FP

CALL_COMPLETE_FP FP

KG INITIAL GS GS EXEC_DCEXEC DCEXECEXEC PREALT PREALTENCRYPT_CCOW PREALT

50

Module Name Located in Is Called by Located in

KG_INITIAL_GS_05 GS ENCRYPT_CCOW DCEXECDECRYPT CCOW DCEXECDECRYPT_RCOW_GS GSENCRYPT_RCOW_GS GSENCRYPT_CCOW PREALTDECRYPT_CCOW PREALT

KG_LOAD_GS GS USERPREAC DCEXECENCRYPT_CCOW DCEXECUSERPREAC PREALT

KG_MEM_CHANGE_GS GS EXEC_DCEXEC DCEXECTS_PREP_DCEXEC DCEXECEXEC_PREALT PREALTTS_PREP_PREALT PREALTKG_LOAD_GS GS

KG_MEM_FILL_20 FP KG_MEM_FILL_FP FP

KG_MEM_FILL_FP FP FPANEL FP

KG MEM TEST GS GS EXAMJXOWOVRHED PRECLAKG_MEM_CHANGE_GS GS

KG READY GS GS EXAM_CCOW_OVRHED PRECLAKG_RESET_GS GSKG_INITIAL_GS GS

KG_RESET_GS GS EXEC_DCEXEC DCEXECTS_PREP_DCEXEC DCEXECENCRYPT_CCOW DCEXECDECRYPT CCOW DCEXECDECRYPT_RCOW_GS GSENCRYPT_RCOW_GS GSKG_MEM_CHANGE_GS GSEXEC_PREALT PREALTTS_PREP_PREALT PREALTENCRYPT_CCOW PREALTDECRYPT_CCOW PREALT

KG TIME 75 FP KG_TIME_FP FP

KG TIME TO DSPLY FP KG_TIME_FP FP

KG ZEROIZE GS GS STATUS_DCCNTR DCCNTRSTATUS_PRECLA PRECLA

LD1 DBPV4 IOIA DBPV4LD2 DBPV4 I02A DBPV4LD3 DBPV4 I03A DBPV4LD4 DBPV4 I04A DBPV4LITES OFF DCMOW DCMOW STATUS_DCCNTR DCCNTR

ZEROIZE DCMOWFRAME_FMT_UPDATE DCMOWCHAN_CONTROL_FP FP

LITES OFF GS GS RECALL_FP FP

INFO_REQUEST_FP FP

PORT RELEASE FP FP

INFO_REQ_CHK_FP FP

CALL_COMPLETE_FP FP

LINK_TEST REQ FP FP

ZEROIZE_FP FP

STATUS_RPT_B_FP FP

GLIST_DISPLY_FP FP

CHAN_CONTROL^FP FP

OUT_OF_SERV_FP FP

51

Module Name Located in Is Called by Located in

LITES OFF PREINT PREfNT STATUS_PRECLA PRECLAFORMAT_UPDATE PREINTNUFMT_TO_STP PREINT

LNK TST LAMP GS GS TO_PARITY_CALL_FP FP

FORMAT_FREQ_FP FP

PORT_RELEASE_FP FP

DC_HOME_FREQ_FP FP

AC_HOME_FREQ_FP FP

QUEUE_TIME_FP FP

SELECT_PORT_FP FP

CONFER_CALL_FP FP

KG_TIME_FP FP

CALL_CANCEL_FP FP

INFO_REQUEST_FP FP

GLIST_ENTER_FP FP

PAGING_REQ_FP FP

EXTEND_XMIT_FP FP

KG_MEM_CHANGE_FP FP

GLIST_DELETE_FP FP

STG_CONTROL_FP FP

CONFIG_CODE_FP FP

LAMP_TEST_GS GSLO GUARD CHK FP FP GLIST_ENTER_FP FP

LOAD_KG_VARS_GS GS ENCYRPT CCOW DCEXECDECRYPT CCOW DCEXECDECRYPT_RCOW_GS GSENCRYPT RCOW GS GSENCRYPT_CCOW PREALTDECRYPT_CCOW PREALT

LTRXEX STPV06 EXEC STPV06

MASTER FRA 05 PREPNT MASTER_FRAME PREFNT

MASTER FRA 10 PREINT MASTER FRAME PREINTMASTER_FRAME DCMOW/PREINT/DCCNTR CCOW_INTP_DCMOW DCMOW

CCOWJNTPJPREINT PREINTMOVE_FRAME_GS GS MASTER_FR<\ME DCCNTR

FRAME_CHK_DCCNTR DCCNTRMOVE_GS GS SPECIAL_CCOW DCCNTR

RCOWJNTPDCCNTR DCCNTRINITDCEXEC DCEXECMOVE TMP TO VARS DCEXECMOVE_VARS_TO_TMP DCEXECSTP_MSG_INTRPRT DCEXECINIT PREALTMOVE VARS TO TMP PREALTMOVE_TMP_TO_VARS PREALTSTP_MSG_INTRPRT PREALTRCOW_INTP_PRECLA PRECLA

MOVE_TMP_TO_VARS DCEXEC/PREALT USERPREAC PREALTUSERPREAC DCEXEC

MOVE_VARS_TO_TMP DCEXEC/PREALT USERPREAC DCEXECUSERPREAC PREALT

NETNUMXCHNG DCEXEC DECRYPT CCOW DCEXECNUFMT_TO_STP PREINT MASTER_FRAME PREINT

FORMAT_CHANGE PREINTODD_PORT_STOR£ PREINT RRU_STATUS_RPTB PREPNT

52

Module Name Located in Is Called by Located in

OFFSET_BY_3_GS GS CC_EXEC_DCCNTR DCCNTRCOMMAND FRAME DCMOW

OFFSET_BY_6_GS GS CC_EXEC_DCCNTR DCCNTRCOMMAND FRAME DCMOW

OUT_SVC_UPDATE PREINT USER_OUT_ACK PREINTPART OUT OF SVC PPvEFNT

PLACE_CALL_PRTY PREINT CONF_REQ_05 PREINTPLACEPORT PREINT CONFER_LIST_RPT PREINT

STATUS RPT B PREINTPOINT_TO_GLISTl PREINT SET_GLIST_PTR PREINTPOINT_TO_GLIST2 PREINT SET GLIST PTR PREINTPOINT_TO_GLIST3 PREINT SET_GLIST_PTR PREINTPOINT_TO_GNUM PREINT POINT_TO_GLISTl PREINT

POINT_TO_GLIST2 PREINTPOINT_TO_GLIST3 PREINT

PORTDETECTGS GS DBP_MSG_INTRPRT DCEXECPORTDISCOJJPDATE PREINT RRU UPDATE PREINT

ZEROIZE PREINTPORT_DISCONNECT DCMOW FRAMEJFMTJUPDATE DCMOW

FORMAT_UPDATE PREINTNUFMT_TO_STP PREINT

PORT RELEASE 15 FP FPANEL FP

PORT RELEASE FP FP DCKPORTOFFGS GSSHOW_PORT_GS GSCALL_CC_GS GS

PORTCCADR_05 PREINT CONFIG_ENTRY_05 PREINTPORTCCADRPREINT PREINT CONFIG_CODE_FP FP

SLOT_CON_UPDATE PREINTRRU_STATUS_RPTB PREINTCALL_REQ_05 PREINTCONF_REQ_05 PREINTCONFIG_ENTRY_05 PREINT

PRE_DCKA_CHK_FP FP TO_PARTY_CALL_FP FP

PREC CONVERT FP FP FPANEL FP

TO_PARITY_CALL_FP FP

PREC_ENTER_25 FP FORMAT_FREQ_FP FP

PREC_ENTER_30 FP GLIST_DISPLY_FP FP

PREC_ENTER_FP FP OUT_OF_SERV_FP FP

TO_PARITY_CALL_FP FP

CONFER_CALL_FP FP

PREC_TO_RCOW_GS GS DATA_XFER DCMOWDATAXFER PREINTRRU_PRTY_OUT PREINTCALL_REQ_05 PREINTCONF_REQ_05 PREINT

PREEMPT LITE PRINT RRU_DISCO PREINT

PREEMPT UPDATE PRECLA TIME CHK PRECLA PRECLAPREMPTCOUNT 05 PREINT PREMPTCOUNT_REDO PREINT

PREMPTCOUNT_REDO PRErNT SLOT_CON_UPDATE PREINTSLOT_DISCONNECT PREINTCALL_COMPLETE PREINT

PRSN STPV06 SRX STPV06

PRTCNFIGCHNG PREINT RRU_STATUS_RPTB PREINT

PSA STPV06 EXEC STPV06CONFIG STPV06

PTSN STPV06 STX STPV06

53

Module Name Located in Is Called by Located in

PVR STPV06 SRX STPV06

BRX STPV06

PVRA STPV06 SRX STPV06

PVT STPV06 STX STPV06

BTX STPV06

RAMT DBPV4/STPV06 COLDS STPV06

RCCOW PORTADR GS GS DATA_XFER DCMOWINFO_REPORT DCMOWRRRU_STATUS_RPTB PREFNTDATA_XFER PREINTCALLCOMPLETE PREINTRRU_PRTY_OUT_05 PREINTINFO_RPT_05 PREINTRRU_CALLCAN_15 PREINT

PAGING_05 PREINTSTATUS_RPT_A PREINTLINK_RESULT PREINTCALL_REQ_05 PREINT

CONF_R£Q_05 PREINT

RCOW ASSIGN FMT PREINT CALL_ACK_05 PREINT

RCOW ASSIGN 05 PREFNT

RCOW INTP DCCNTR DCCNTR USEREXEC DCEXECRCOW_INTP_PRECLA PRECLA USEREXEC PREALTRCOW OUT PREINT PRINT USEREXEC PREALTRCOW PREP XMIT DCEXEC/PREALT USEREXEC DCEXEC

USEREXEC PREALTRCOW XMIT DCMOW DCMOW USEREXEC DCEXECRCV CCOW BLOCK PRECLA CC_EXEC_PRECLA PRECLAREAD ACIA GS TEST_ACIA GSREAD_CALL_ACK PREINT MASTER_FRAME PREINT

COMMAND_FRAME PREINT

|READ_DBP_RCOW_GS GS DBP MSG PNTRPRT DCEXECDBPMSGJNTRPRT PREALT

REDO DBP PORT GS GS DISCO_SLOT_CHK DCMOWCALL_REQUEST DCMOWCALL COMPLETE DCMOWINIT PREALTRRU_TURNOFF PRECLASLOTCONJJPDATE PREINTPORT_DISCONNECT PREINTCLEAR_SLOTS_GS GS

REDO_RRUl_GS GS REDO_RRUS_DCMOW DCMOWREDO_RRUS_PREINT PREINT

WRITE_ACIA GSREDO_RRU2_GS GS REDO_RRUS_DCMOW DCMOW

REDO RRUS PREINT PREINT

WRITE ACIA GSREDO RRU3 GS GS REDO_RRUS_DCMOW DCMOW

REDO_RRUS_PREINT PREINT

WRITE ACIA GSREi)0_RRU4_GS GS REDO RRUS DCMOW DCMOW

REDORRUSPREINT PREINT

WRITE_ACIA GS

|REDO_RRUS_DCMOW DCMOW USEREXEC DCEXEC

CCOW_INTP_DCMOW DCMOW

54

Module Name Located in Is Called by Located in

REDO_RRUS_PREINT PREINT USEREXEC PREALTCCOWINTPPREINT PREINT

REINITDELAY DCMOW MASTER_FRAME DCMOWRESET_ACIAS_GS GS [NTT DCEXEC DCEXEC

INIT PREALT|RESET_BLACK_GS GS ENCRYPT_CCOW DCEXEC

DECRYPTCCOW DCEXECDECRYPT_RCOW_GS GSENCRYPT_RCOW_GS GSKG_INITIAL_GS GSDECRYPTCCOW PREALTENCRYPTCCOW PREALT

RESET_RRU_PTR_GS GS RRU INTRPRT DCMOWCALL_REQUEST DCMOWDATA_XFER DCMOWGLIST DISP DCMOWCALL_COMPLETE DCMOWrNFO_R£PORT DCMOWRRU_INTRPRT PREINTRRU_STATUS_RPTB PREINTDATA_XFER PRErNTGLIST_DISPLAY PREINTGLIST_DISPLAY_05 PREINTCALL_COMPLETE PREINTRRU_PRTY_OUT PREINTINFO_REPORT PREINTINFO_REPORT_05 PREINT

CALLJREQUEST PREINT

CALL_REQ_05 PREINT

CONFJREQUEST PREINTRRU_CALL_CANCEL PREINTRRU_CALLCAN_05 PRErNTGLIST_ENTR_DEL PREPWTGLIST_ENTDEL_05 PREINT

GLISTJENTDELJO PREINTPAGING_RCOW PREINTPAGING_05 PREINTCONF_REQ_05 PREINTCONFIG_ENTRY PREINT

RGRXEX STPV06 EXEC STPV06

ROMTST DBPV4 PWRON DBPV4RPT B OUT PREINT PREINT FP RCOW PREALT

STATUSRPTB PRErNT

RQST_CODE_GS GS FNFO_R£PORT DCMOWFPANEL FP

INFO_REPORT_FP FP

INFO_REQUEST_GS GSINFO_RPT_05 PREINT

55

Module Name Located in Is Called by Located in

RRU ACPT ON GS GS DATA_XFER DCMOWCALL_R£QUEST DCMOWCALL_COMPLETE DCMOWrNFO REPORT DCMOWRRU_STATUS_RPTB PREINTDATAXFER PREFNT

CALL COMPLETE PREINTRRU PRTY OUT 05 PREINTINFO_RPT_05 PREINTRRU CALLCAN 15 PREINTPAGING05 PREFNTCALL_R£Q_05 PREFNTCONF_REQ_05 PREINT

RRU B2 LOOP CHK DCEXEC/PREALT RCOW_PREP_XMIT DCEXECRCOW_PREP_XMIT PREALT

RRU CLEAR BIT GS GS STP_MSG_rNTRPRT DCEXECCLR_RRU_PREC_DSP DCEXECFPANEL FP

CLR_RRU_PREC_DSP PREALTSTP MSG INTRPRT PREALTMASTER_FRAME PRErNT

|RRU_DISCO PREINT CHK USER NR1 PREINTCHK_USER_NR2 PREINT

RRU INTRPRT DCMOW/PREINT RRU_MSG_IN_DCMOW DCMOWRRUMSGINJPREFNT PREINT

RRU MSG IN DCMOW DCMOW USERPREAC DCEXECRRU MSG UPDATE PREALT USEREXEC DCEXEC

USERPREAC DCEXECUSEREXEC PREALTUSERPREAC PREALT

RRU OUT ADR PREINT BUSY_ACK PREINTCALL_ACK PREINT

RRU SET BIT GS GS STP_MSG_INTRPRT DCEXECRRU_MSG_UPDATE DCEXECFPANEL FP

STP MSG INTRPRT PREALTRRU_MSG_UPDATE PREALTMASTERFRAME PREFNT

RRU_TURNOFF PRECLA TIME_CHK_PRECLA PRECLARRU XMIT SET GS GS USEREXEC DCEXEC

USERPREAC DCEXECUSEREXEC PREALTUSERPREAC PREALT

RRUMSG FN PREINT PREINT USEREXEC PREALTUSERPREAC PREALT

RRUOUTAD2 PREINT PREPWT FRAME_CHK_PR£CLA PRECLABUSY ACK PREINT

CALL-ACK 05 PREFNTCALLACK PREINT

SAVE STP11 GS GS DISCO_SLOT_CHK DCMOWFNIT PREALTRRU TURNOFF PRECLASLOT CON UPDATE PREINTPORT_DISCONNECT PREFNT

56

Module Name Located in Is Called by Located in

SAVE_STP12_GS GS SWITCH REDO DCEXECAC_HOME_FREQ_FP FP

EXEC_PREALT PREALTUSEREXEC PREALTEXAMJXOWOVRHED PRECLAHOME CHAN 05 PREINT

SAVE_STP13_GS GS TIME_CHK_DCCCNTR DCCNTREXEC_DCEXEC DCEXECUSEREXEC DCEXECSTP_MSG_INTRPRT DCEXECMASTER_FRAME DCMOWSETUP PREALTUSERPREAC PREALTSTP_MSG_INTRPRT PREALTEXAM_CCOW_OVRHED PRECLASTATUS_PRECLA PRECLACC_EXEC_PRECLA PRECLA

SAVE_STP18_GS GS TIME_CHK_DCCCNTR DCCNTRSTATUS DCCNTR DCCNTRUSEREXEC DCEXECUSERPREAC DCEXECSTP_MSG_INTRPRT DCEXECMASTER FRAME DCMOWRCOW_XMIT_DCMOW DCMOWUSEREXEC PREALTSTP_MSG_INTRPRT PREALTEXAM_CCOW_OVRHED PRECLATIME_CHK_PRECLA PRECLASTATUSPRECLA PRECLARCOW_OUT_PREINT PREINTMASTER FRAME PREFNTLINK_TEST_ASIGN PREINT

SAVE_SW3_GS GS SETUP_MISC DCEXECAC_HOME_FREQ_FP FP

INIT PREALTSETUP PREALTEXAMJXOWOVRHED PRECLAHOME_CHAN 05 PREINT

SCCNV STPV06 EXEC STPV06

SEL PORT DISCO PREINT SLOTDISCONNECT PRErNTRRU_DISCO PREINTSLOT_CON_UPDATE PREINTCALL_COMPLETE PREINT

SELECT PORT FP GP JUMP_SELECT_1 GS GSJUMP_SELECT_2_GS GS

SEND CCOW BLOCK PRECLA CC_EXEC_PRECLA PRECLASEND RCOW TO SAC PRECLA CCEXECPRECLA PRECLASEQUENCEJLITES DCCNTR FRAME_CHK_DCCNTR DCCNTRSET_DBPSTAT_MSG DCCNTR/PRECLA STATUS_DCCNTR DCCNTR

STATUS_PRECLA PRECLASET_GLIST_FLAG PREINT GLIST_ENTDEL_10 PREINT

GLIST_ENTDEL_30 PREINT

SET_GLIST_PNTR PREINT RPTGLIST1 PREINTRPT_GLIST2 PREINTRPTGLIST3 PREINTRPTGLIST4 PREINT

57

Module Name Located in Is Called by Located in

SET MSG CODE PREINT RPT_GLIST1 PREINTRPT_GLIST2 PREINTRPTGLIST3 PREINTRPT_GLIST4 PREINT

SET PORT CC DCCNTR/PRECLA STATUS_DCCNTR DCCNTRSTATUS_PRECLA PRECLA

SET PREMPT FLAG PREINT RRU_DISCO PREINTSLOT_CON_UPDATE PREINT

SET SC FLAG PREINT SET_XMIT_FLAG PREINTSET TIME CODE PREINT RRU_DISCO PREINT

SLOT_CON_UPDATE PREINTSETUP DBPV4/STPV06 INIT PREALTSETUP_MISC DCEXEC/PREALT INITJDCEXEC DCEXECSETUP

1

DBPV4/DCMOW PWRON DBPV4TDMA DBPV4

SHIFT EVEN PORT PREINT STATUS RPT A PREINTSHIFT ODD PORT PREINT STATUS RPT A PREINTSHIFTLEFT GS LOAD_KG_VARS_GS GSSHIFTRIGHT GS LOAD_KG_VARS GS GSSHOW_PORT_GS GS PORT_DETECT_GS GSSHOW_WX_GS GS KG_TIME_TO_DSPLY FP

DISP_VWXYZ_GS GSSHOWYZGS GS BCD_TO_YZ_FP FP

AC_HOME_FREQ_FP FP

KG_TIME_TO_DSPLY FP

DISP_VWXYZ_GS GSDISP_INFO REQ GS GS

SHOWOUT_YZ_GS GS FPANEL FP

CONFIG CODE FP FP

SLOT_CON_UPDATE PREINT SLOT_CONNECT PREINTSOFA DBPV4 SOF DBPV4SOFAA DBPV4 RBIT DBPV4SRX STPV06 CONS STPV06

SST STPV06 RCW1 STPV06RR2 STPV06

STATUS_DCCNTR DCCNTR EXEC_DCEXEC DCEXECSTATUSPRECLA PRECLA EXEC_PREALT PREALTSTC STPV06 CONFIG_CODE_FP STPV06

STC4 STPV06 STC STPV06

STG_LITE_UPDATE FP STG_CONTROL FP FP

STPMSGJNTRPRT DCEXEC/PREALT USEREXEC DCEXECUSERPREAC DCEXECUSEREXEC PREALTUSERPREAC PREALT

STRAP_05 GS STRAP_READ_GS GSSTRAP READ GS GS INIT_DCEXEC DCEXEC

SETUP_MISC DCEXECINIT PREALT

STUFF DBPV4 TDMA DBPV4STX STPV06 CONS STPV06

SUB_KG_TIME_GS GS PORT_DETECT_GS GSSWAPLITES_DCEXEC DCEXEC EXEC_DCEXEC DCEXEC

USEREXEC DCEXECSTP_MSG_INTRPRT DCEXECMASTER_FRAME DCMOWCHAN_CONTROL_FP FP

58

Module Name Located in Is Called by Located in

SWITCH REDO DCEXEC EXEC DCEXEC DCEXECSWITCHIT_GS GS EXEC_DCEXEC DCEXEC

SWITCH REDO DCEXECEXEC_PREALT PREALT

TEST ACIA GS INTERUPT GS GSTIME CHK DCCNTR DCCNTR USEREXEC DCEXEC

USERPREAC DCEXECTIME CHK PRECLA PRECLA USEREXEC PREALT

USERPREAC PREALT(TIME_DELAY |DCMOW/PREINT INFO_REPORT DCMOW

RRU STATUS RPTB PREINTPAGING_05 PREINTINFO RPT 05 PREINTCALL_COMPLETE PREINT

TIME FMT PRELNT RRU_DISCO PREINTSLOT CON UPDATE PREINTCALL QUEJJPDATE PREINTPORTDISCOJJPDATE PREINT

TS PREP DCEXEC DCEXEC FRAME CHK DCCNTR DCCNTRUSERPREAC DCEXEC

TS_PREP_PREALT | PREALT USERPREAC PREALTFRAME_CHK_PRECLA PRECLA

TST_XMITD_QUE PREINT BUSY_ACK PREINTREAD_CALL_ACK PREINT

|UNPACK_GS |GS FPANEL FP

INFO_REQ_CHK_FP FP

FREQ_TO_DSPLY_FP FP

CONFIG_CODE_FP FP

SHOW_YZ_GS GSSHOW WX GS GS

USER1 SETUP GS GS ZEROIZE DCMOWINFO_REQUEST_GS GSSLOT_DISCONNECT PREINTPARTY OUT OF SVC PREINTUSER1_SETUP_GS PREINTZEROIZE PREINTCCOW DATA XFER PREINTCALL_IN_QUE PREINTCALL_WAITING PREINTDELET_GUARD_LIST PREINTENTER_GUARD_LIST PREINTHOME_CHAN_CHANG PREINTCALLCANCEL PREINTFORMAT CHANGE PREINTSLOT_CONNECT PREINTLINK_TEST_ASIGN PREINT

59

Module Name Located in Is Called by Located in

USER2 SETUP PREPNT ZEROIZE DCMOWSLOT DISCONNECT PREINTSLOT_CONNECT PREFNTFORMAT_CHANGE PREPNTCALL_CANCEL PREFNTHOME_CHAN_CHANG PREINTENTER_GUARD_LIST PREFNTDELET_GUARD_LIST PREFNTCALL_IN_QUE PREINTZEROIZE PREINTPARTY_OUT_OF_SVC PREINT

|USER3_SETUP PREINT CALL_CANCEL PREINTHOME_CHAN_CHANG PREINTENTER_GUARD_LIST PREINTDELET_GUARD_LIST PREINT

USEREXEC DCEXEC/PREALT EXEC_DCEXEC DCEXECEXEC_PREALT PREALT

USERPREAC DCEXEC/PREALT EXEC_DCEXEC DCEXECEXEC_PREALT PREALT

VWXYZ_TO_BIN_FP |FP ZEROIZE_FP FP

GLIST_DELETE_FP FP

PAGrNG_REQ_FP FP

GLIST_ENTER_FP FP

INFO_REPORT_FP FP

TO_PARITY_CALL_FP FP

CONFER_CALL_FP FP

WRITE_ACIA GS TEST_ACIA GSWX_TO_BCD_FP FP KG_TIME_FP FP

INFOJREQUESTJFP FP

XFER CCOW TO DBP DCEXEC EXEC_DCEXEC DCEXECXFER_OW PREALT EXEC_PREALT PREALTXFER_RCOW_DBP_GS GS EXEC_DCEXEC DCEXEC

RCOW_PREP_XMIT DCEXECRCOW_PREP_XMIT PREALT

XPLUSA_GS GS FRAME CHK DCCNTR DCCNTRCALL_REQUEST DCCNTRSEQUENCE_LITES DCCNTRRCOW PNTP DCCNTR DCCNTRRRU_B2_LOOP_CHK DCEXECSWAPLITES_DCEXEC DCEXECCALLREQUEST DCMOWINFO_REQ_CHK_FP FP

rNiT PREALTRRU B2 LOOP CHK PREALTRCOW_INTP_PRECLA PRECLAFORMAT GLIST RCW PREINTMASTER_FRAME PREINTRRU_DISCO PREINTCHK_GLIST PREINT

XPLUSB_GS GSRRU_CLEAR_BIT_GS GSRRU_SET_BIT_GS GS

60

Module Name Located in Is Called by Located in

XPLUSBGS GS FORMAT FREQ_FP FP

DC_HOME_FREQ_FP FP

FREQ_TO_DSPLY_FP FP

CALL COMPLETE DCMOWCALL_REQUEST DCMOWBIT RATE FIND DCMOW

YZ TO BCD FP FP OUT_OF_SERV_FP FP

DC_HOME_FREQ_FP FP

KG_TIME_FP FP

INFO_REQUEST_FP FP

YZ TO BIN FP FP CONFER_CALL_FP FP

ZERO_SLOTS_GS GS STATUS_DCCNTR DCCNTRZEROIZE DCMOW

61

Module Name Located in Is Called by Located in

ZEROFILL GS GS SPECIAL_CCOW DCCNTRTIME_CHK_DCCNTR DCCNTRSTATUS_DCCNTR DCCNTREXEC_DCEXEC DCEXECSTP_MSG_rNTRPRT DCEXECRCOW_XMIT_DCMOW DCMOWCHAN_CONTROL_FP FP

EXEC_PREALT PREALTSTP_MSG_INTRPRT PREALTTIME_CHK_PRECLA PRECLASTATUSPRECLA PRECLAMASTER FRAME PREINT

CONF_REQ_05 PREINT

REDO RRU1 GS GSCLEAR_SLOTS_GS GS

62

APPENDIX C

A. PARSER.ADA

with text_io; use text_io;procedure parser is

package int_io is new integer_io (integer)

;

use int_io;

subtype label_range is integer range 1..-6;

subtype opcode_range is integer range 8.. 13;subtype operand_range is integer range 15.. 20;

subtype str6 is string (1 .. 6)

;

subtype strl20 is string (1 .. 120)

;

type call_node;type call_node_jptr is access call_node;

type call_node is recordcaller : integer;next : call_node_ptr

;

end record;

type label_node;type label_node_ptr is access label_node;

type label_node is recordlabelcalled_bylinenext

end record;

str6 ;

call_node_ptr

;

integer;label_node_ptr;

label_listnew_labelsearchlabelopcodeoperandcol_nbrnew_callerinput_f ileoutput_f ile

label_node_ptr := nulllabel_node_ptr

;

label_node_ptr;str6

;

str6str6natural

;

call_node_ptr ;

file_type;file type;

procedure establish_label_list is

lineline_nbrcountdebugfound

beginwhile not end_of_f ile (input_f ile) loop

strl20;integer : = ;

natural

;

boolean := false;boolean;

63

get_line (input_f ile, line, count)

;

line_nbr := line_nbr + 1;

put (output_f ile, line_nbr, 4)

;

put_line (output_f ile, " " & line (1 .. count) )

;

-- CHECK IF THE LINE HAS A LABELif count > then

if line(l) >= 'A' and lined) <= 'Z' thenif count >= 7 then

label := line (label_range)

;

if debug then put_line ( "LABEL IS & label) ; end if;

-- CHECK AND SEE IF THE LABEL EXISTSsearch := label_list;found := false;while search /= null loop

if search. label = label thenfound : = true

;

end i f

;

search := search. next;end loop;if debug then put_line ( "SEARCHED FOR LABEL - " &

boolean ' image (found) ) ; end if;

if not found then-- ENTER THE LABEL INTO THE END OF THE LINKED LIST

= new label_node;= label;= null;= line nbr;

new_labelnew_label . labelnew_label . nextnew_label . linesearch := label_list;if search = null then

-- FIRST ITEM IN THE LISTlabel_list := new_label;

elsewhile search. next /= nul'l loop

search := search, next ,-

end loop;search. next := new_label;

end if;

end i f ,-

end if; -- count > 7

end if; -- 'A' or '

Z'

end if; -- count >

end loop;end establish label list;

procedure parse_control is

linecountline_countdebugfoundcaller

strl2 0;

natural

;

integerbooleanboolean;call_node_ptr

;

= 0;

= false;

function control_opcode (opcodedebug : boolean := false;

beginif debug then put (opcode) ; end if;

str6) return boolean is

64

if opcode = "BCCopcode = "BCSopcode = "BEQopcode = "BGEopcode = "BGTopcode = "BHIopcode = "BLEopcode = "BLSopcode = "BLTopcode = "BMIopcode = "BNEopcode = "BPLopcode = "BRAopcode = "BSRopcode = "BVCopcode = "BVSopcode = "JMPopcode = "JSR

orororororororororororororororororthen

if debug then put_line(" - TRUE"); end if;

if debug then skip_line; end if;

return true;else

if debug then put_line(" - FALSE"); end if;

if debug then skip_line,- end if;

return false;end if;

end control_opcode ,-

beginwhile not end_of_file (input_f ile) loop

get_line (input_f ile, line, count);for i in count + 1 .. line 'last looplined) := ' ';

end loop;

line_count := line_count + 1;

if debug then put_line (line (1 .. count) ) ; end if;-- CHECK IF THE LINE ISN'T A COMMENTif line(l) /= '*' then

-- NOT A COMMENT

opcode := line (opcode_range)

;

operand := line (operand_range) ,-

if control_opcode (opcode) thenif debug then put_l ine (" FOUND BRANCH OPCODE - LOOKING FOR

operand) ; end if;-- SEARCH THE LABEL LIST FOR THE OPERANDsearch := label_list;found := false;while not found loop

--if debug then put_l ine ( "COMPARING " & operand & " TO '

search. label) ; end if;

if operand = search. label then-- FOUND MATCH, ADD CURRENT LINE NUMBER TO LISTif debug then put_l ine ( "FOUND MATCHING LABEL - ADDING

LINE NUMBER"); end if;

65

-- ADD TO ENDnew_caller := new call_node;new_caller .next := null;new_caller. caller : = line_count;if search. called_by = null then

search. called_by := new_caller;else

caller := search. called_by;while caller. next /= null loop

caller := caller. next ,-

end loop;caller. next : = new_caller;

end i f

;

found : = true;else

search := search. next;if search = null thenput_line ("COULD NOT FIND LABEL " & operand & " AT LINE

" & integer ' image (line_count) )

;

found := true;end i f

;

end i f

;

end loop;end if;

end if;

if debug then skip_line; end if;end loop;

end parse_control

;

procedure report_results isbegin

while label_list /= null loopput (label_list. label & " (");

if label_list . line < 10 thenput (label_list . line, 1)

;

elsif label_list . line < 100 thenput (label_list . line, 2);

elsif label_list . line < 1000 thenput (label_list . line, 3)

;

elseput (label_list . line, 4);

end i f ,-

put (

" ) ")

;

while label_list . called_by /= null loopput (

" ")

;

put (label_list . called_by. caller, 4)

;

label_list .called_by := label_list . called_by .next

;

end loop;label_list := label_list .next ,-

new_l ine

;

end loop;end report_results

;

beginopen (input_f ile, in_file, "s_dbp . src" )

,-

create (output_f ile, out_file, "s_dbp . 1st " )

;

establish label list;

66

close (input_file)

;

close (output_f ile)

;

open (input_f ile, in_file, "s_dbp. src"

)

parse_control

;

close (input_f ile)

;

report_results

;

end parser;

67

68

APPENDIX D

A. DATA BUFFER PROCESSOR SOURCE CODE LISTING

1 *********************************************

2 *

3 * BEGIN POWER ON INIT4 *

5 ORG 0DC00H6 PWRON LDS #0 0FFFH7 SEI8 LDX #IRS9 STX 0FFF8H

10 STAA MPUB11 JSR INIT12 STAA BRATE1 SET BIT RATES = 75 BPS13 STAA BRATE214 LDAA #055H **TEST RAM**15 CLRB16 RAMT LDX #0FFCH17 RAMTST STAA 0,X18 CMPA 0,X19 BNE RAMERR20 STAA MPUB21 DEX22 BNE RAMTST23 TSTB24 BNE TSTROM25 LDAA #0AAH TEST OTHER RAM BITS26 INCB27 BRA RAMT28 TSTROM JSR ROMTST **NOP FOR TESTING**29 JSR CLEAR30 BRA PWRON131 RAMERR LDAA #020H **RAM ERROR**32 STAA LATCH2 *****

33 STAA MPUB CRASH34 BRA RAMERR *****

35 *********************************************

36 *

37 *

38 ROMTST CLRA **TEST ROM**39 CLRB40 LDX #PWRON41 ROMTSA ADDA 0,X42 ADCB #0

43 STAA MPUB44 INX45 CPX #PGMTOP46 BNE ROMTSA47 CMPA CKSMA48 BNE ROMERR49 CMPB CKSMB

69

50

5152

53

54

5556

57

58

59606162

63

64656667

686970

7172

7374

757677

78

79808182

83

84

8586

87

88

8990

9192

93

94

95

96

97

98

99100101102103104105106

BNERTS

*

ROMERR LDAASTAASTAABRA

ROMERR

#040HLATCH2MPUBROMERR

**ROM ERROR*******

CRASH*****

CLEAR LATCHED INPUTS

ENABLE INTERRUPTS ON AC I

A

PWRON1 JSR SETUP1LDAA PIA1ADLDAA PIA1BDLDAA #09DHSTAA ACIACSCLIJMP TDMA

***********************************************************

INIT LDAASTAALDAASTAACLRASTAASTAASTAASTAASTAASTAASTAASTAASTAASTAASTAASTAASTAASTAACOMASTAASTAASTAASTAASTAASTAALDAASTAALDAASTAASTAASTAASTAASTAASTAASTAASTAASTAALDAA

#01FHACIACS#0FHLATCH3

PIA1ACPIA1BCIOl + l

101 + 3

102 + 1

102 + 3

103 + 1

103 + 3

104 + 1

104 + 3

101102103104

PIA1ADPIA1BD101 + 2

102 + 2

103 + 2104 + 2

#03EHPIA1AC#02EHIOl + l

101 + 3

102 + 1

102 + 3

103 + 1

103 + 3

104 + 1

104 + 3

PIA1BCPIA1AD

MASTER RESET ACIADISABLE INTERRUPTS

RESET I/O FIFOSI/O PORT Sc PIA INIT

SET DATA DIRECTION REGA - SIDE = INPUTSFOR I/O PORT

B-SIDE = OUTPUTSFOR I/O PORT

SET CONTROL REG

CLEAR LATCHED INPUTS

70

107 LDAA PIA1BD108 CLRA10 9 STAA PIA1AD110 STAA LATCH1 CLEAR SIGNAL ACQ. LINES111 STAA LATCH2112 RTS113 ***********************************************************

114 *

115 *

116 CLEAR CLRA CLEAR RAM MEMORY117 LDX #0FF8H118 CLEARA STAA 0,X119 DEX12 BNE CLEARA121 STAA INPT1122 RTS123 ***********************************************************

124 *

125 *

126 SETUP BSR CLEAR12 7 SETUP

1

INCA12 8 STAA TDMAFG SETUP RCCOW & CCOW PORTS12 9 INCA13 STAA MSDOl131 STAA MSD02132 STAA MSD0313 3 STAA MSD04134 LDAA #0FH INIT FIFO MR INFO13 5 STAA MRFTA136 STAA LATCH313 7 LDX #ERCRX13 8 STX RCRXPT13 9 LDAA DATA1 CHECK FOR 'TEST 1' MODE140 BITA #010H141 BEQ SETUP3142 LDAA #0FH143 STAA PTONRX144 LDAA #024H145 STAA BRATE1 INIT BIT RATES146 STAA BRATE2 FOR TEST #1 MODE:147 LDAA #020H ALL = 2400 BPS14 8 STAA CHRAT114 9 STAA CHRAT215 STAA CHRAT3151 STAA CHRAT4152 SETUP3 RTS153 ***********************************************************

154 *

155 *

156 TDMA STAA MPUB ***BITE OUTPUT***15 7 LDAA DATA1 CHECK TDMA SWITCH FLAG158 BITA #020H OF T&C PROCESSOR159 BNE TDMA116 LDAB TDMAFG161 BNE TDMAI162 ***********************************************************

163 *

71

164 *NON-TDMA SERVICE165 *

166 BITA #01H167 BEQ TDMAA168 LDAA #01FH169 BRA TDMAB170 TDMAA LDAA #0FH171 TDMAB STAA LATCH3172 BRA TDMA173 *

174 TDMAI SEI175 JSR INIT176 CLR TDMAFG177 CLR PIA1BD178 LDAA DATA3179 LDAA #036H180 STAA PIA1AC181 LDAA #03EH182 STAA PIA1AC183 BRA TDMA184 *

185 TDMAI LDAA TDMAFG186 BNE RBI187 STAA PTONRX188 BSR SETUP1189 LDAA #09DH190 STAA ACIACS191 CLI192 *********************

193 *

194 *

195 RBI LDAA PIA1AC196 BMI RBIA197 JMP TBI198 RBIA LDAB SIEN199 BEQ RBIB200 LDAB BITELT201 ORAB #020H202 STAB BITELT203 CLR SIEN204 CLR SELFTR205 CLR FILLFG206 CLR INPTRC207 *

208 ***** BEGIN RECEIVE209 *

210 RBIB LDAB PIA1AD211 LDAA DATA4212 LDAB SELFTR213 BEQ RBIBA214 LDAB BITELT215 ORAB #080H216 STAB BITELT217 RBIBA ANDA #0C7H218 TAB219 ANDA #7

220 CLR MASKIO

CHECK NON-TDMA TX REQ

SET TX ACK

CLEAR TX ACK

INIT. FOR NON-TDMA

RESET TX FIFO

STROBE "NON-TDMA START'

TURN ALL PORTS OFFINIT FOR TDMAENABLE RX INTERRUPTS

**************************************

CHECK RCV SETUP RDY

SYST INPUT FIFO BITE(RX FIFO)

CLEAR INPUT FIFO FLAGS

BURST INIT *****

CLR LATCHED STROBELOAD RCV SETUP DATA

*SELF TEST FAIL BITE*

72

221 CMPA #1

222 BEQ RBI1C223 JMP RBI2B224 *

225 RBI1C LDAA XMTRQ1226 BEQ RBI1CA227 JMP TBI228 RBI1CA LDAA PTONRX229 ANDA #1230 BNE RBI ID231 JMP TBI232 RBI ID ORAB CHRAT1233 LDAA UT1234 BEQ RBI1E235 LDAA DATA6236 BITA #8237 BNE RBI IDA238 LDAA BITELT239 ORAA #2240 STAA BITELT241 RBI IDA CLR UT1242 RBI IE LDAA #1243 STAA MASKIO244 TSTB245 BMI RBI1G246 LDAA MSDOl247 BEQ RBI1EA248 CLR FLBFG1249 LDAA #2

250 STAA MSDOl251 JMP TBI252 RBI1EA INCA253 STAA FMSDOl254 STAA MSDOl255 STAA FILLFG256 LDAA CHCT1257 LDAB CHCT1+1258 ADDB #32259 ADCA #0260 STAA MDOCT1261 STAB MDOCT1+1262 LDAB CHRAT1263 BRA RBI1H1264 RBI1G LDAA MSDOl265 CMPA #2

266 BNE RBI1H267 LDAA MRFTA268 ORAA #1269 STAA MRFTA270 STAA LATCH3271 RBI1GA LDX #SBUFF1272 STX OUTPT1273 STAA FLBFG1274 CLRA275 STAA CHCT1276 LDAA #0FFH277 TST BPS16K

**PORT #1 RX BURST INIT**

CHECK FIFO'S "O.R.

"

***I/0 FIFO #1 BITE***

INIT I/O ON/OFF MASK

TWO OR MORE MISSING DO'S

**FIRST MISSING DO SETUP**

SETUP TO STUFF"FF" INTO BUFFER

ADJ COUNT FOR I/O FIFO

TWO OR MORE MISSING DO'S?

RESET I/O #1 FIFO

INIT BUFFER #1 ANDI/O FIFO #1

**RX ELAST BUFF CH**16KBPS?

73

278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334

RBI 1GB

RBI1HRBI1H1

RBI1HA

RBI1HB

RBI2B

RBI2C

RBI2CA

RBI2D

RBI2DARBI2E

BEQJSRSTXLDXSTXBRASTAASTAASTAASTAASTAALDAASTAALDXSTXCLRLDXSTXLDAABEQLDXSTXLDXSTXBRALDXSTXLDXSTXLDAAORAASTAASTAAJMP

CMPABEQJMPLDAABEQJMPLDAAANDABNEJMPORABLDAABEQLDAABITABNELDAAORAASTAACLRLDAASTAA

RBI1GBSTUFFINPT1#256CHCT1RBI1HSBUFF1SBUFF1+1SBUFF1+2SBUFF1+3SBUFF1+4#5CHCT1+1#SBUFFl+5INPT1MSDOl#INPT1RXPNTRBPS16KRBI1HA#EBUFF4RXUVAL#SBUFF1RXLVALRBI1HB#EBUFF1RXUVAL#SBUFF1RXLVALSIGACQ#1

SIGACQLATCH1RBIS

#2

RBI2CRBI3BXMTRQ2RBI2CATBIPTONRX#2

RBI2DTBICHRAT2UT2RBI2EDATA6#4

RBI2DABITELT#4

BITELTUT2#2

MASKIO

16 KBPS ELASTIC BUF . CHARS

17 MIN. ELASTIC BUFF

RCV BURST

INIT FOR INPUTFIFO SERVICE

16 KBPS?

INIT 16 KBPS BUFFER PNTRS

.

SET "SIGNAL ACQ. I/O #1"

**PORT #2 BURST INIT**

CHECK FIFO'S "O.R.

***I/0 FIFO #2 BITE***

INIT I/O ON/OFF MASK

74

335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387

388389390391

TSTBBMILDAABEQCLRLDAASTAAJMP

RBI2EA INCASTAASTAASTAALDAALDABADDBADCASTAASTABLDABBRA

RBI2G LDAACMPABNELDAAORAASTAASTAA

RBI2GA LDXSTXSTAACLRASTAALDAATSTBEQJSRSTXLDXSTXLDXSTXBRA

RBI2GB STAASTAASTAASTAASTAALDAASTAALDXSTX

RBI2H CLRRBI2H1 LDX

STXLDAABEQLDX

RBI2GMSD02RBI2EAFLBFG2#2

MSD02TBI

FMSD02MSD02FILLFGCHCT2CHCT2+1#32#0

MDOCT2MDOCT2+1CHRAT2RBI2H1MSD02#2

RBI2HMRFTA#2

MRFTALATCH3#SBUFF2OUTPT2FLBFG2

CHCT2#0FFHBPS16KRBI 2GBSTUFFINPT2#256CHCT2#SBUFF1OUTPT2RBI2HSBUFF2SBUFF2+1SBUFF2+2SBUFF2+3SBUFF2+4#5

CHCT2+1#SBUFF2+5INPT2MSD02#INPT2RXPNTRBPS16KRBI2HA#EBUFF4

TWO OR MORE MISSING DO'S

**FIRST MISSING DO SETUP**

SETUP TO STUFF"FF" INTO BUFFER

ADJ COUNT FOR I/O FIFO

TWO OR MORE MISSING DO'S?

RESET I/O #2 FIFO

INIT BUFFER #2 ANDI/O FIFO #2

**RX ELAST BUFF CH**16KBPS?

16KBPS ELASTIC BUF . CHARS.

17 MIN ELAST BUFF

RCV BURST

INIT FOR INPUTFIFO SERVICE

16 KBPS?

75

392 STX RXUVAL393 LDX #SBUFF1394 STX RXLVAL395 BRA RBI2HB396 RBI2HA LDX #EBUFF2397 STX RXUVAL398 LDX #SBUFF2399 STX RXLVAL400 RBI2HB LDAA SIGACQ401 ORAA #2402 STAA SIGACQ403 STAA LATCH

1

404 JMP RBIS405 *

406 RBI3B CMPA #3407 BEQ RBI3C408 JMP RBI4B409 RBI3C LDAA XMTRQ3410 BEQ RBI3CA411 JMP TBI412 RBI3CA LDAA PTONRX413 ANDA #4414 BNE RBI3D415 JMP TBI416 RBI3D ORAB CHRAT3417 LDAA UT3418 BEQ RBI3E419 LDAA DATA6420 BITA #2421 BNE RBI3DA422 LDAA BITELT423 ORAA #8424 STAA BITELT425 RBI3DA CLR UT3426 RBI3E LDAA #4427 STAA MASKIO428 TSTB429 BMI RBI3G430 LDAA MSD03431 BEQ RBI3EA432 CLR FLBFG3433 LDAA #2434 STAA MSDO 3

435 JMP TBI436 RBI3EA INCA437 STAA FMSD03438 STAA MSD03439 STAA FILLFG440 LDAA CHCT3441 LDAB CHCT3+1442 ADDB #32443 ADCA #0444 STAA MDOCT3445 STAB MDOCT3+1446 LDAB CHRAT3447 BRA RBI3H1448 RBI3G LDAA MSD03

INIT. 16KBPS BUF. PNTRS

.

SET "SIGNAL ACQ. I/O #2

**PORT #3 BURST INIT**

CHECK FIFO'S "O.R.

**I/0 FIFO #3 BITE***

INIT I/O ON/OFF MASK

**FIRST MISSING DO SETUP**

SETUP TO STUFF"FF" INTO BUFFER

ADJ COUNT FOR I/O FIFO

76

449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505

RBI3GA

RBI 3GB

RBI3HRBI3H1

RBI3HA

RBI3HB

RBI4B

RBI4C

RBI4CA

CMPABNELDAAORAASTAASTAALDXSTXSTAACLRASTAALDAATSTBEQJSRSTXLDXSTXLDXSTXBRASTAASTAASTAASTAASTAALDAASTAALDXSTXCLRLDXSTXLDAABEQLDXSTXLDXSTXBRALDXSTXLDXSTXLDAAORAASTAASTAAJMP

CMPABEQJMPLDAABEQJMPLDAA

#2 TWO OR MORE MISSING DO'S?RBI3HMRFTA#4 RESET I/O FIFO #3MRFTALATCH3#SBUFF3 INIT BUFFER #3 ANDOUTPT3 I/O FIFO #3FLBFG3

CHCT3#0FFHBPS16KRBI3GBSTUFFINPT3#256CHCT3#SBUFF1OUTPT3RBI3HSBUFF3SBUFF3+1SBUFF3+2SBUFF3+3SBUFF3+4#5CHCT3+1#SBUFF3+5INPT3MSD03#INPT3RXPNTRBPS16KRBI3HA#EBUFF4RXUVAL#SBUFFIRXLVALRBI3HB#EBUFF3RXUVAL#SBUFF3RXLVALSIGACQ#4SIGACQLATCH

1

RBIS

#4

RBI4CRBIJXMTRQ4RBI4CATBIPTONRX

**RX ELAST BUFF CH**16KBPS?

16 KBPS ELASTIC BUF . CHARS

17 MIN ELASTIC BUFF

RCV BURST

INIT FOR INPUTFIFO SERVICE

INIT 16KBPS PNTRS

SET "SIGNAL ACQ. I/O #3"

**PORT #4 BURST INIT**

77

506 ANDA #8507 BNE RBI4D508 JMP TBI509 RBI4D ORAB CHRAT4510 LDAA UT4511 BEQ RBI4E512 LDAA DATA6513 BITA #1514 BNE RBI4DA515 LDAA BITELT516 ORAA #010H517 STAA BITELT518 RBI 4DA CLR UT4519 RBI4E LDAA #8

520 STAA MASKIO521 TSTB522 BMI RBI4G523 LDAA MSD04524 BEQ RBI4EA525 CLR FLBFG4526 LDAA #2527 STAA MSD04528 JMP TBI529 RBI4EA INCA530 STAA FMSD04531 STAA MSD04532 STAA FILLFG533 LDAA CHCT4534 LDAB CHCT4+1535 ADDB #32536 ADCA #0537 STAA MDOCT4538 STAB MDOCT4+1539 LDAB CHRAT4540 BRA RBI4H1541 RBI4G LDAA MSD04542 CMPA #2543 BNE RBI4H544 LDAA MRFTA545 ORAA #08H546 STAA MRFTA547 STAA LATCH

3

548 RBI4GA LDX #SBUFF4549 STX OUTPT4550 STAA FLBFG4551 CLRA552 STAA CHCT4553 LDAA #0FFH554 TST BPS16K555 BEQ RBI4GB556 JSR STUFF557 STX INPT4558 LDX #256559 STX CHCT4560 LDX #SBUFF1561 STX OUTPT4562 BRA RBI4H

CHECK FIFO'S "O.R.

"

**I/0 FIFO #4 BITE***

INIT I/O ON/OFF MASK

TWO OR MORE MISSING DO'S

**FIRST MISSING DO SETUP**

SETUP TO STUFF"FF" INTO BUFFER

ADJ COUNT FOR I/O FIFO

TWO OR MORE MISSING DO'S?

RESET I/O FIFO #4

INIT BUFFER #4 ANDI/O FIFO #4

**RX ELAST BUFF CH**16KBPS?

16 KBPS ELASTIC BUFF. CHARS

17 MIN ELASTIC BUFF

78

563564565566567568569570571572573

574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619

RBI4GB

RBI4HRBI4H1

STAASTAASTAASTAASTAALDAASTAALDXSTXCLRLDXSTXLDAABEQLDXSTXLDXSTXBRALDXSTXLDXSTXLDAAORAASTAASTAAJMP

RBI4HA

RBI4HB

SBUFF4 RCV BURSTSBUFF4+1SBUFF4+2SBUFF4+3SBUFF4+4#5CHCT4+1#SBUFF4+5INPT4MSD04#INPT4RXPNTRBPS16KRBI4HA#EBUFF4RXUVAL#SBUFF1RXLVALRBI4HB#EBUFF4RXUVAL#SBUFF4RXLVALSIGACQ#8

SIGACQLATCH

1

RBIS• ••it*******************************************

INIT FOR INPUTFIFO SERVICE

INIT 16KBPS PNTRS

SET "SIGNAL ACQ I/O #4"

*

RBIJ

RBIJA

RBIK

RBIKA

RBIL

CMPABNESTAALDAALDABJMPLDXCPXBEQPSHALDAAORAASTAAPULALDXSTXLDXCMPABNETSTBBMILDAASTAAJMP

LDAA

#7RBIJASELFTR#0#60RBITRCRXPT#ERCRXRBIK

BITELT#1BITELT

#ERCRXRCRXPT#SRCRX#6RBIN

RBIL#0A5HACIADTBI

DATA1

CHECK FOR SELF TEST RX BURS

INIT. RX FIFO COUNT

R/CCOW RX BUFFER EMPTY?

**RCCOW/CCOW ERROR**

CCOW DO?

OUTPUT CCOW DOABSENT CODE TO SCU

TX REQUEST STATUS WBR

79

620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676

RBIM

RBIN

RBIO

RBIS

ANDAORAASTAA

LDAASTAAINXSTXSTAASTAAJMPTSTBBMILDAABRALDAABRABSRBRA

#0FH#0C0HACIAD

#0A1H0,X

RCRXPTINPTRCSIENTBI

RBIO#0A6HRBIKA#0A2HRBIMBITRATRBIT

SEND C CODE TO SCP

CCOW DO PRESENT CODE

ADJ R/CCOW RX BUFFER PNTR

WBRWBRWBR

RCCOW DO?

RCCOW DO ABSENT CODE

RCCOW DO PRESENT CODE

***************************************************************

BITRAT

RBISA

RBI SB

RBISC

RBISD

RBISE

RBISF

TSTBNEASLBBMIANDBBNELDABCLRARTSCMPBBNELDABCLRARTSCMPBBNELDABCLRARTSCMPBBNELDABCLRARTSCMPBBNELDABLDAARTSLDABLDAARTSLDABLDAARTS

BPS16KRBISF

RBIU#070HRBISA#13

#010HRBISB#52

#020HRBISC#104

#030HRBISD#208

#040HRBISE#0A0H#1

#040H#3

#0D5H#0AH

TEST 16KBPS

75 BPS @ 1.386 SEC13 BYTES

300 BPS @ 1.386 SEC52 BYTES

600 BPS @ 1.386 SEC104 BYTES

1200 BPS @ 1.386 SEC2 08 BYTES

2400 BPS416 BYTES

1.386 SEC

4800 BPS @ 1.386 SEC8 32 BYTES

16000 BPS @ 1.386 SEC2 77 3 BYTES

80

677678679680681682683684685686687688689690691692693694695696697698699700701702

703704705706707708709710711712713714715716717718719720721722723724725726727

728729730731732

733

RBIU LDABCLRARTS

#78 75 BPS @ 8.32 SEC78 BYTES

***********************************************************

RBIT

*******

TBI

TBI1

TBI2

TBI3

TBI4

TBIA

STAASTABCLRASTAAINCASTAA

******

LDAABEQCLRLDAAORAABRALDAABEQCLRLDAAORAASTAASTAALDAABEQLDAAORAASTAALDAABMIJMPLDAABEQLDABORABSTAB

INCHC MSB'S OF CH . CNT

.

INCHC+1 LSB'S OF CH . CNT.

INPTRC

SIEN***********************************************

CDRDYTBI1CDRDYPA1AD#020HTBI2RDRDYTBI 3

RDRDYPA1AD#010HPA1ADPIA1ADIRSBITTBI4BITELT#01HBITELTPIA1BCTBIAIOIPTSOENTBIBBITELT#040HBITELT

TEST CCOW DATA RDY FLG

,

SET DATA RDY CCOW*

TEST RCCOW RDY FLG.

SET DATA RDY RCCOW*

IRS BITE?

CHECK TX SETUP READY

SYST OUTPUT FIFO BITE(TX FIFO)

BEGIN TRANSMIT BURST INITIALIZATION *****

TBIB

TBIBATIBA

LDAALDAALDABBITBBEQANDACMPABEQJMPJMPANDATABANDA

PIA1BDDATA3DATA5#1TIBA#7#7

TBIBAIOIPTTBIG#047H

#7

CLR LATCHED STROBELOAD TX SETUP DATACHECK TX INHIBIT

TX INHIBIT: ABORTALLOW SELF TEST BURST

81

734 CMPA #1735 BNE TBI2B736 LDAA PTONRX IS PORT ON?737 BITA #1

738 BNE TBI1BA739 JMP IOIPT ABORT: PORT IS

740 •

741 TBI1BA TST BPS16K742 BEQ TBI1E743 LDX #SBUFF1 16 KBPS744 STX TXLVAL745 LDX #EBUFF4746 STX TXUVAL747 BRA TBI1EA748 TBI1E LDX #SBUFF1 INIT FOR OUTPUT749 STX TXLVAL FIFO SERVICE750 LDX #EBUFF1751 STX TXUVAL752 TBI1EA LDX #INPT1753 STX TXPNTR754 CLRA755 STAA UT1756 STAA MDOCT1757 STAA MDOCTl+1758 STAA FMSDOl759 LDAA #2760 STAA MSDOl761 LDAA #0FEH762 STAA XMASK763 LDAA #0EFH764 STAA MASKR765 LDAA GROUP

1

766 BEQ TBI1F767 STAA GRP1FG768 TBI1F CLRA769 STAA GROUP

1

770 ORAB CHRAT1771 JMP TBIN772 •

773 TBI2B CMPA #2774 BNE TBI3B775 LDAA PTONRX IS PORT ON?776 BITA #2777 BNE TBI2BA778 JMP IOIPT ABORT: PORT IS <

779 TBI2BA TST BPS16K780 BEQ TBI2E781 LDX #SBUFF1 16 KBPS782 STX TXLVAL783 LDX #EBUFF4784 STX TXUVAL785 BRA TBI2EA786 TBI2E LDX #SBUFF2 INIT. FOR OUTPUT787 STX TXLVAL FIFO SERVICE788 LDX #EBUFF2789 STX TXUVAL790 TBI2EA LDX #INPT2

82

791 STX TXPNTR792 CLRA793 STAA UT2794 STAA MDOCT2795 STAA MDOCT2+1796 STAA FMSD02797 LDAA #2798 STAA MSD02799 LDAA #0FDH800 STAA XMASK801 LDAA #0DFH802 STAA MASKR803 LDAA GROUP2804 BEQ TBI2F805 STAA GRP1FG806 TBI2F CLRA807 STAA GROUP

2

808 ORAB CHRAT2809 JMP TBIN810 *

811 TBI3B CMPA #3812 BNE TBI4B813 LDAA PTONRX IS PORT ON?814 BITA #4815 BNE TBI3BA816 JMP IOIPT ABORT: PORT IS <

817 TBI3BA TST BPS16K818 BEQ TBI3E819 LDX #SBUFFI 16 KBPS820 STX TXLVAL821 LDX #EBUFF4822 STX TXUVAL823 BRA TBI3EA824 TBI3E LDX #SBUFF3 INIT. FOR OUPTUT825 STX TXLVAL FIFO SERVICE826 LDX #EBUFF3827 STX TXUVAL828 TBI3EA LDX #INPT3829 STX TXPNTR830 CLRA831 STAA UT3832 STAA MDOCT3833 STAA MDOCT3+1834 STAA FMSD03835 LDAA #2836 STAA MSD03837 LDAA #0FBH838 STAA XMASK839 LDAA #0BFH840 STAA MASKR841 LDAA GROUP

3

842 BEQ TBI3F843 STAA GRP1FG844 TBI3F CLRA845 STAA GROUP

3

846 ORAB CHRAT3847 JMP TBIN

83

848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904

*

TBI4B

TBI4BA

TBI4E

TBI4EA

TBI4F

TBIG

TBIG1

TBIGA

CMPABNELDAABITABNEJMPTSTBEQLDXSTXLDXSTXBRALDXSTXLDXSTXLDXSTXCLRASTAASTAASTAASTAALDAASTAALDAASTAALDAASTAALDAABEQSTAACLRASTAAORABJMP

CMPABNESTAASTAALDXSTXLDXSTXLDAALDABSTABDECABNEJMPCMPABNELDAABITA

#4TBIGPTONRX#8TBI4BAIOIPTBPS16KTBI4E#SBUFF1TXLVAL#EBUFF4TXUVALTBI4EA#SBUFF4TXLVAL#EBUFF4TXUVAL#INPT4TXPNTR

UT4MDOCT4MDOCT4+1FMSD04#2MSD04#0F7HXMASK#07FHMASKRGR0UP4TBI4FGRP1FG

GROUP4CHRAT4TBIN

#7TBIGASOENSELFTT#08000HTXPNTR#28OUTCHC#32#033HPIA1BD

TBIG1RBI#6TBIJPA1AD#020H

IS PORT ON?

ABORT: PORT IS OFF

16 KBPS

INIT. FOR OUTPUTFIFO SERVICE

CHECK FOR SELF TEST TX BURS

DUMMY VALUE FOR TXPNTR

SELF TEST CH CNT - 32

SELF TEST TX CHAR

OUTPUT 32 SELF TESTCHARS. TO TX FIFO

IF NO DATA READY, OUTPUT13 BYTES OF 11001100

84

905 BNE TBIGC906 LDAA #0CCH907 LDX #13

908 TBIGB STAA PIA1BD909 DEX910 BNE TBIGB911 BRA TBIHB912 TBIGC LDX #SCTXB913 STX CTXPT914 TBIH LDAA 0,X

915 STAA PIA1BD916 INX917 CPX #ECTXB918 BNE TBIH919 LDAA PA1AD920 ANDA #0DFH921 TBIHA STAA PIA1AD922 STAA PA1AD923 *

924 *

925 TBIHB ASLB926 BMI TBIHC927 JMP IOIPT928 TBIHC CLRA929 STAA PIA1BD930 STAA PIA1BD931 STAA PIA1BD932 JMP IOIPT933 TBIJ LDX #SRTXB934 STX RTXPT935 TBIK LDAA 0,X936 STAA PIA1BD937 INX938 CPX #ERTXB939 BNE TBIK940 LDAA PA1AD941 ANDA #0EFH942 BRA TBIHA943 TBIN JSR BITRAT944 TBIO STAA OUTCHC945 STAB OUTCHC+1946 CLRA947 INCA948 STAA SOEN949 TBIQ LDX TXPNTR950 LDAA GRP1FG951 BEQ TBIS952 TBIQ1 LDAA OUTCHC953 LDAB OUTCHC+1954 ADDB #6

955 ADCA #0

956 SUBB 5,X957 SBCA 4,X958 BCS TBIR959 BNE TBIRA960 TSTB961 BNE TBIRA

rNO CCOW DATA RDY**

PUT CHAR IN OUTPUT FIFO

CLR DATA READY CCOW

PUT CHAR IN OUTPUT FIFO

CLR DATA READY RCCOW

GET TX CH. CNT.MSB'S OF CH. CNT.

LSB ' S OF CH . CNT

.

CHECK IF FIRST GROUP

***COMPUTE FILL COUNT***

ADD ELASTIC BUFF (48 BITS)

BURST CH CNT + ELASTIC BUFF- BUFF CH CNT = FILL COUNT

85

962 TBIR CLR GRP1FG963 BRA TBIS964 TBIRA STAA FILLCT965 STAB FILLCT+1966 LDAA 4,X967 LDAB 5,X968 SUBB #6969 SBCA #0970 BCC TBIRB971 CLRA972 STAA SOEN973 LDAA BITELT974 ORAA #040H975 STAA BITELT976 BRA IOIPT977 TBIRB STAA OUTCHC978 STAB OUTCHC+1979 TBIS JSR SOFAA980 **********************

981 *

982 *

983 *

984 I01PT LDAA PTONRX985 ANDA #1986 BEQ IOlAl987 CLR PIOFF988 JMP IOIA989 I01A1 LDAA PIOFF990 BEQ I01A2991 JMP I02PT992 I01A2 STAA CHCT1993 STAA CHCT1+1994 STAA XMTRQ1995 STAA UT1996 LDX #0997 STX LGDPT1998 STAA OUFG1999 STAA EMPTY1

1000 LDAA #21001 STAA MSDOl1002 INCA1003 STAA FLBFG11004 LDAA MRFTA1005 ORAA #11006 ANDA #0EFH1007 STAA MRFTA1008 STAA LATCH31009 STAA PIOFF1010 LDAA PA1AD1011 ANDA #0FEH1012 STAA PA1AD1013 STAA PIA1AD1014 LDX #SBUFF11015 STX INPT11016 STX OUTPT11017 LDAA SIGACQ1018 ANDA #0FEH

NO FILL REQUIRED

NUMBER OF GOOD CHARS IN FIRBURST=BUFF CH CNT - ELASTICSUBT ELASTIC BUFF (48 BITS)

ERROR: ELASTIC BUFFER NOTYET FULL FOR TRANSMISSION

**TX FIFO BITE LITE ON**

SERVICE OUTPUT FIFO************************************************

PORT #1 ON?

PORT IS OFF

RESET FIFO I/O #1CLR "XMT ACK"

CLEAR "DATA RDY PORT #1"

CLR "SIGNAL ACQ. I/O #1

86

101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075

STAASTAALDXCPXBNECLR

I01A3 JMP

SIGACQLATCH1TXPNTR#INPT1101A3SOENI02PT

***********************************************************

INPUT SERVICE SUBROUTINE

#1XFER1101INPT10,X

OUTPT1IOILSXMRFTA#0EFH#1MRFTALATCH3OUFG1

I02PTBPS16KIOILSA#EBUFF4IOILSB#SBUFF1IOILSB#EBUFF1IOILSB#SBUFF1INPT1CHCT1

CHCT1

OBTAIN CHARGET PUT PNTRPUT ITINCR PUT PNTRTEST OVERFLOWBRANCH NO OVERFLOW**OVERFLOW**CLR "XMT ACK"

RESET FIFO

SET OUFG FLAG*REMOVE RETURN*

IOILS LDAASTAALDAALDXSTAAINXCPXBNELDAAANDAORAASTAASTAASTAAINSINSJMP

IOILSX LDAABEQCPXBNELDXBRA

IOILSA CPXBNELDX

IOILSB STXLDXINXSTXRTS

***********************************************************

*LOAD I/O #1 FIFO WITH 1 CHAR. ROUTINE*

16 KBPS

TEST END OF INPUTNOGET INITIAL VALUE

GET CHAR COUNTINCR COUNTPUT BACK

IOILF LDXLDAABITABNELDAASTAA

IOILFI INXLDABBEQCPXBNE

OUTPT1RXINHB#1IOILFI0,X101 + 2

BPS16KIOILFA#EBUFF4IOILFB

IS THE EXTEND TRANSMIT FLAG SET?YES:RX NOT ALLOWED

OUTPUT CH. TO I/O #1 FIFO

16 KBPS

WBRWBRWBR

87

1076 LDX #SBUFF11077 BRA IOILFB1078 I01LFA CPX #EBUFF11079 BNE IOILFB1080 LDX #SBUFF11081 IOILFB STX OUTPT11082 LDAA #11083 STAA XFER11084 LDAA FMSDOl TEST MISSING DO1085 BEQ IOILFC1086 LDX MDOCT11087 DEX1088 STX MDOCT11089 BNE IOILFC1090 LDAA SIGACQ1091 ANDA #0FEH1092 STAA SIGACQ1093 STAA LATCH11094 CLR FMSDOl1095 IOILFC LDX CHCT1 ADJUST CHAR COUNT1096 DEX1097 STX CHCT11098 BNE IOILFD1099 INS REMOVE RETURN1100 INS1101 JMP IOIYEI GO CHECK UNDERFLOW1102 IOILFD RTS1103 ***********************************************************

1104 *

1105 *LOAD :I/O #1 FIFO WITH 3 BUF. CH. ROUTINE1106 *

1107 LD1 LDX OUTPT11108 LDAA 0,X1109 STAA 101 + 2

1110 LDAA 1,X1111 STAA 101 + 2

1112 LDAA 2,X1113 STAA 101 + 2

1114 INX1115 INX1116 INX1117 STX OUTPT11118 LDX CHCT11119 DEX1120 DEX1121 DEX1122 STX CHCT11123 RTS1124 **********************************************************

1125 *

1126 ***** BEGIN SERVICING I/O PORT #1 *****

1127 *

1128 IOIA LDAA PTONRX RX ONLY?1129 BITA #010H1130 BEQ IOIAA1131 JMP IOIY1132 IOIAA LDAA DATA1

88

1133 BITA #1

1134 BNE IOIB1135 JMP IOIY1136 I01B ASLA1137 BPL IOIC1138 LDAA XMTRQ11139 BNE IOIC1140 LDAA EMPTY11141 BNE IOICA1142 LDX CHCT11143 BEQ IOIBB1144 IOIBA JMP IOIYD1145 I01BB LDAA DATA61146 BITA #8

1147 BNE IOIBA1148 I01C LDAA XMTRQ11149 BNE IOID1150 LDAA EMPTY11151 BEQ IOIE1152 IOICA CLR EMPTY11153 STAA XMTRQ11154 LDX #01155 STX LGDPT11156 LDAA MRFTA1157 ORAA #010H1158 STAA MRFTA1159 STAA LATCH

3

1160 I01D LDAA OUFG11161 BEQ IOIH1162 STAA XFER11163 JMP I02PT1164 I01E LDAA DATA51165 ANDA #1

1166 BEQ IOIF1167 JMP I02PT1168 I01F LDAA #11169 STAA XMTRQ11170 STAA GROUP

1

1171 STAA XFER11172 STAA FLBFG11173 LDAA SIGACQ1174 ORAA #010H1175 ANDA #0FEH1176 STAA SIGACQ1177 STAA LATCH

1

1178 LDAA MRFTA1179 ORAA #11180 STAA LATCH31181 CLR 101 + 2

1182 ANDA #0FEH1183 ORAA #010H1184 STAA MRFTA1185 STAA LATCH31186 LDX #SBUFFI1187 STX INPT11188 LDX #SBUFF11189 STX OUTPT1

R/T SELECTED: CHECK RCV DON

TEST: I/O FIFO UNDERFLOW

BRANCH: NO UNDERFLOW

GET HERE W/MULTIPLETX REQ PER FRAME

SET "TX ACK'

CHECK TX INHIBIT

**INIT FOR PORT #1****DATA TRANSMISSION**

SELECT I/O INPUT MODECLR "SIG. ACQ. #1"

TOGGLE FIFO'S RESET

CLR PIA B-SIDE

SET "XMT ACK" I/O #1

+ 6

89

1190 LDAA #0FFH1191 STAA 0,X1192 STAA 1,X1193 STAA 2,X1194 STAA 3,X1195 STAA 4,X1196 STAA 5,X1197 LDX #6

1198 STX CHCT11199 JMP I02PT1200 I01G LDX #SBUFFI1201 STX INPT11202 STX OUTPT11203 LDX #01204 STX CHCT11205 LDAA SIGACQ1206 ANDA #0FEH1207 STAA SIGACQ1208 STAA LATCH11209 JMP 102 PT1210 IOIH LDAA DATA51211 ANDA #11212 BEQ IOIHA1213 JMP IOIYAI1214 IOIHA LDAB FLBFG11215 BEQ IOIHB1216 JMP IOIO1217 I01HB LDAA DATA61218 BITA #8

1219 BNE IOII1220 JMP I01XP1221 IOII JSR I01LS1222 LDAA DATA61223 BITA #81224 BNE IOIK1225 JMP I01XP1226 IOIK JSR I01LS1227 LDAA DATA61228 BITA #81229 BNE IOIM1230 JMP IOIXP1231 IOIM JSR IOILS1232 LDAA DATA61233 BITA #81234 BNE I01N21235 JMP IOIXP1236 I01N2 JSR IOILS1237 LDAA BPS16K1238 BNE I01N31239 JMP IOIXP1240 I01N3 LDAA DATA61241 BITA #8

1242 BNE I01N41243 JMP IOIXP1244 I01N4 JSR IOILS1245 LDAA DATA61246 BITA #8

STUFF 6 ELASTICBUFFER CHARACTERS (CC)

CLR "SIGNAL ACQ. I/O #1

CHECK TX INHIBIT

TEST FIFO "O.R.

LOAD & STORE 1 CHAR

LOAD Sc STORE 2 CHAR

LOAD Sc STORE 3 CHAR

LOAD & STORE 4 CHAR

*16KBPS: ALLOW MORE*I/O SERVICING*

LOAD & STORE 5 CHAR.

90

1247 BNE I01N51248 JMP IOIXP1249 I01N5 JSR IOILS1250 LDAA DATA61251 BITA #8

1252 BNE I01N61253 JMP IOIXP1254 I01N6 JSR IOILS1255 LDAA DATA61256 BITA #8

1257 BNE I01N71258 JMP IOIXP1259 I01N7 JSR IOILS1260 LDAA DATA61261 BITA #8

1262 BNE I01N81263 JMP IOIXP1264 I01N8 JSR IOILS1265 LDAA DATA61266 BITA #8

1267 BNE I01N91268 JMP IOIXP1269 I01N9 JSR IOILS1270 LDAA DATA61271 BITA #8

1272 BNE IO1N101273 JMP IOIXP1274 IO1N10 JSR IOILS1275 JMP IOIXP1276 1010 LDAA DATA61277 BITA #8

1278 BEQ IOIXP1279 I01P CLR FLBFG11280 LDAA PA1AD1281 ORAA #11282 STAA PA1AD1283 STAA PIA1AD1284 JMP IOII1285 I01XP LDAA EMPTY11286 BPL IOIXQ1287 LDX INPT11288 STX LGDPT11289 LDAA #1

1290 STAA EMPTY11291 I01XQ JMP I02PT1292 I01Y LDAA XMTRQ11293 BEQ IOIYB1294 LDAA MRFTA1295 ANDA #0EFH1296 STAA MRFTA1297 STAA LATCH

3

1298 CLR XMTRQ11299 LDAA #0FFH1300 STAA EMPTY11301 LDAA PA1AD1302 ANDA #11303 BNE IOIYA

LOAD & STORE 6 CHAR.

LOAD & STORE 7 CHAR.

LOAD Sc STORE 8 CHAR.

LOAD & STORE 9 CHAR.

LOAD & STORE 10 CHAR.

LOAD & STORE 11 CHAR.

SET "DATA RDY PORT #1"

**TEST IF SETUP****LAST GOOD DATA PNTR**DO SETUP

CLEAR "TX ACK'

FIRST TIME THATTX REQ = FALSE

91

1304 STAA CHCT11305 STAA CHCT1+11306 STAA EMPTY11307 INCA1308 STAA FLBFG11309 LDAA MRFTA1310 ORAA #11311 STAA MRFTA1312 STAA LATCH31313 JMP 102 PT1314 I01YA JMP I01D1315 I01YB LDAA EMPTY11316 BNE I01YA1317 JMP I01YD1318 I01YA1 CLRA1319 STAA XMTRQ11320 STAA EMPTY11321 LDAA PA1AD1322 ANDA #0FEH1323 STAA PIA1AD1324 STAA PA1AD1325 LDAA MRFTA1326 ORAA #1

1327 ANDA #0EFH1328 STAA MRFTA1329 STAA LATCH

3

1330 I01YC LDAA MRFTA1331 ORAA #11332 STAA MRFTA1333 STAA LATCH31334 LDAA SIGACQ1335 ANDA #0EFH1336 STAA SIGACQ1337 STAA LATCH11338 I01YC1 CLR FMSDOl1339 LDAA #2

1340 STAA MSDOl1341 STAA FLBFG11342 JMP I01G1343 IOlYD LDAA FLBFG11344 BEQ I01YF1345 STAA XFER11346 LDAA CHCT1+11347 CMPA #101348 BGE IOIYE1349 JMP I02PT135 IOlYE CLR FLBFG11351 STAA UT11352 LDAA SIGACQ1353 ANDA #0EFH1354 STAA SIGACQ1355 STAA LATCH

1

1356 LDAA MRFTA1357 ANDA #0FEH1358 STAA MRFTA1359 STAA LATCH31360 JSR LD1

NO DATA: ABORT INPUT

CLEAR "DATA RDY PORT #1"

RESET I/O #1 FIFOCLR TX ACK I/O #1

**INIT I/O PORT **

**TO OUTPUT****RX BURST DATA**RESET I/O #1 FIFO

SELECT I/O OUTPUT MODE

RCV ELASTIC BUFFER FULL?

SET OUTPUT MODE

CLR RESET ON I/O FIFO

92

136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417

IO1YE0I01YE1

I01YF

I01YFA

I01YG

IOIYH

IOIYI

IOIYJ

IOIYK

IOIYL

IOIYM

IOIYN

IOIYO

JSRLDAABEQJSRJSRJSRJSRJSRJMPLDAASTAALDAABNELDAABITABEQJMPLDXBEQLDAALDABBNEBITABEQBITABEQJSRLDAABITABEQJSRLDAABITABEQJSRLDAABEQLDAABITABEQJSRLDAABITABEQJSRLDAABITABEQJSRLDAABITABEQJSRLDAABITABEQJSR

LD1BPS16KIO1YE0LD1LD1LD1LD1LD1I02PT#1XFER1UT1IO1YE0DATA6#8I01YC1I02PTCHCT1I01YE1DATA6UT1I01YFA#8

I01YC1#080HI02PTI01LFDATA6#080HI02PTI01LFDATA6#080HI02PTI01LFBPS16KI02PTDATA6#080HI02PTI01LFDATA6#080HI02PTI01LFDATA6#080HI02PTI01LFDATA6#080HI02PTI01LFDATA6#080HI02PTI01LF

LOAD FIFO W/6 BUF . CH.

16KBPS SO:

LOAD FIFO WITH 21 BUF. CH

.

CHECK FIFO UNDERFLOWBY TESTING FIFO "O.R."**UNDERFLOW**

CHECK FIFO "I.R.": FULL?

OUTPUT 1 CH. TO FIFO

CHECK "I .R. " : FULL?

OUTPUT 2 CH. TO FIFO

CHECK "I.R.": FULL?

OUTPUT 3 CH. TO FIFO

16KBPS: SERVICE 10 CHARS.CHECK "I.R.": FULL?

OUTPUT 4 CH. TO FIFO

CHECK "I.R.": FULL?

OUTPUT 5 CH. TO FIFO

CHECK "I.R.": FULL?

OUTPUT 6 CH. TO FIFO

CHECK "I.R." : FULL?

OUTPUT 7 CH. TO FIFO

CHECK "I.R.": FULL?

OUTPUT 8 CH. TO FIFO

93

1418 LDAA DATA61419 BITA #080H1420 BEQ I02PT1421 I01YP JSR IOILF1422 LDAA DATA61423 BITA #080H1424 BEQ I02PT'

1425 IOIYQ JSR IOILF1426 *********************

1427 *

1428 *

1429 •

1430 I02PT LDAA PTONRX1431 ANDA #21432 BEQ I02A11433 CLR P20FF1434 JMP I02A1435 I02A1 LDAA P20FF1436 BEQ I02A21437 JMP I03PT1438 I02A2 STAA CHCT21439 STAA CHCT2+11440 STAA XMTRQ21441 STAA UT21442 LDX #01443 STX LGDPT21444 STAA OUFG21445 STAA EMPTY21446 LDAA #2

1447 STAA MSD021448 INCA1449 STAA FLBFG21450 LDAA MRFTA1451 ORAA #2

1452 ANDA #0DFH1453 STAA MRFTA1454 STAA LATCH31455 STAA P20FF1456 LDAA PA1AD1457 ANDA #0FDH1458 STAA PA1AD1459 STAA PIA1AD1460 LDX #SBUFF21461 STX INPT21462 STX OUTPT21463 LDAA SIGACQ1464 ANDA #0FDH1465 STAA SIGACQ1466 STAA LATCH11467 LDX TXPNTR1468 CPX #INPT21469 BNE I02A31470 CLR SOEN1471 I02A3 JMP I03PT1472 *********************

1473 *

1474 * INPUT SERVICE ROU

CHECK "I.R. " : FULL?

OUTPUT 9 CH. TO FIFO

CHECK "I.R. " : FULL?

OUTPUT 10 CH. TO FIFO

PORT #2 ON?

PORT IS OFF

RESET FIFO I/O #2

CLEAR "DATA RDY PORT #2"

CLR "SIGNAL ACQ. I/O #2'

***********************************************

94

1475 *

1476 I02LS LDAA #11477 STAA XFER21478 LDAA 102 OBTAIN CHAR1479 LDX INPT2 GET PUT PNTR1480 STAA 0,X PUT IT1481 INX INCR PUT PNTR1482 CPX OUTPT2 TEST OVERFLOW1483 BNE I02LSX BRANCH NO OVERFLOW1484 LDAA MRFTA **OVERFLOW**1485 ANDA #0DFH CLR "XMT ACK"1486 ORAA #2 RESET FIFO1487 STAA MRFTA1488 STAA LATCH31489 STAA OUFG2 SET OUFG FLAG1490 INS REMOVE RETURN1491 INS *

1492 JMP I03PT1493 I02LSX LDAA BPS16K1494 BEQ I02LSA1495 CPX #EBUFF4 16 KBPS1496 BNE I02LSB1497 LDX #SBUFF11498 BRA I02LSB1499 I02LSA CPX #EBUFF2 TEST END OF INPUT1500 BNE I02LSB NO1501 LDX #SBUFF2 GET INITIAL VALUE1502 I02LSB STX INPT21503 LDX CHCT2 GET CHAR COUNT1504 INX INCR COUNT1505 STX CHCT2 PUT BACK1506 RTS1507 **************+***************+**********•

1508 *

1509 *LOAD I/O #2 FIFO WITH 1 CHAR ROUTINE1510 *

1511 I02LF LDX OUTPT21512 LDAA RXINHB1513 BITA #2 IS THE EXTEND TRAN:

1514 BNE I02LF1 YES:RX NOT ALLOWED1515 LDAA 0,X1516 STAA 102+2 OUTPUT CH. TO I/O1517 I02LF1 INX ADJ. OUTPUT PNTR.1518 LDAB BPS16K1519 BEQ I02LFA1520 CPX #EBUFF4 16 KBPS1521 BNE I02LFB1522 LDX #SBUFF11523 BRA I02LFB1524 I02LFA CPX #EBUFF21525 BNE I02LFB1526 LDX #SBUFF21527 I02LFB STX OUTPT21528 LDAA #11529 STAA XFER21530 LDAA FMSD02 TEST MISSING DO1531 BEQ I02LFC

WBRWBRWBR

95

1532 LDX MDOCT21533 DEX1534 STX MDOCT21535 BNE I02LFC1536 LDAA SIGACQ1537 ANDA #0FDH1538 STAA SIGACQ1539 STAA LATCH11540 CLR FMSD021541 I02LFC LDX CHCT2 ADJUST CHAR COUNT1542 DEX1543 STX CHCT21544 BNE I02LFD1545 INS REMOVE RETURN1546 INS1547 JMP I02YE1 GO CHECK UNDERFLOW1548 I02LFD RTS1549 **********************************************************

1550 *

1551 * LOAD FIFO I/O #2 WITH 3 BUF. CH. ROUTINE1552 *

1553 LD2 LDX OUTPT21554 LDAA 0,X1555 STAA 102+21556 LDAA i,x1557 STAA 102+21558 LDAA 2,X1559 STAA 102+21560 INX1561 INX1562 INX1563 STX OUTPT21564 LDX CHCT21565 DEX1566 DEX1567 DEX1568 STX CHCT21569 RTS1570 ***********************************************************

1571 *

1572 ***** BEGIN SERVICING I/O PORT #2 *****

1573 *

1574 I02A LDAA PTONRX RX ONLY?1575 BITA #020H1576 BEQ I02AA1577 JMP I02Y1578 I02AA LDAA DATA11579 BITA #2

1580 BNE I02B1581 JMP I02Y1582 I02B ASLA1583 BPL I02C1584 LDAA XMTRQ21585 BNE I02C1586 LDAA EMPTY21587 BNE I02CA1588 LDX CHCT2 R/T SELECTED: CHECK RCV DON

96

1589 BEQ I02BB1590 I02BA JMP I02YD1591 I02BB LDAA DATA61592 BITA #4

1593 BNE I02BA1594 I02C LDAA XMTRQ21595 BNE I02D1596 LDAA EMPTY21597 BEQ I02E1598 I02CA CLR EMPTY21599 STAA XMTRQ21600 LDX #0

1601 STX LGDPT21602 LDAA MRFTA1603 ORAA #020H1604 STAA MRFTA1605 STAA LATCH31606 I02D LDAA OUFG21607 BNE I02DA1608 JMP I02H1609 I02DA STAA XFER21610 JMP I03PT1611 I02E LDAA DATA51612 ANDA #11613 BEQ I02F1614 JMP I03PT1615 I02F LDAA #1

1616 STAA XMTRQ21617 STAA GROUP

2

1618 STAA XFER21619 STAA FLBFG21620 LDAA SIGACQ1621 ORAA #020H1622 ANDA #0FDH1623 STAA SIGACQ1624 STAA LATCH

1

1625 LDAA MRFTA1626 ORAA #21627 STAA LATCH

3

1628 CLR 102+21629 ANDA #0FDH1630 ORAA #020H1631 STAA MRFTA1632 STAA LATCH31633 LDAA BPS16K1634 BEQ I02FA1635 LDX #SBUFFI1636 STX INPT21637 LDX #SBUFF11638 BRA I02FB1639 102 FA LDX #SBUFF21640 STX INPT21641 LDX #SBUFF21642 102 FB STX OUTPT21643 LDAA #0FFH1644 STAA 0,X1645 STAA 1,X

TEST: I/O FIFO UNDERFLOW

BRANCH: NO UNDERFLOW

GET HERE W/MULTPLETX REQ PER FRAME

SET "TX ACK'

CHECK TX INHIBIT

**INIT FOR PORT #2**

**DATA TRANSMISSION**

SELECT I/O INPUT MODECLR "SIG. ACQ. #2"

TOGGLE FIFO'S RESET

CLR PIA B-SIDE

SET "XMT ACK" I/O #2

+ 6

+ 6

16KBPS

STUFF 6 ELASTICBUFFER CHARACTERS (CC)

97

164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702

I02G

I02GAI02GB

I02H

I02HA

I02HB

102

1

I02K

I02M

I02N2

I02N3

I02N4

STAASTAASTAASTAALDXSTXJMPLDAABEQLDXBRALDXSTXSTXLDXSTXLDAAANDASTAASTAAJMPLDAAANDABEQJMPLDABBEQJMPLDAABITABNEJMPJSRLDAABITABNEJMPJSRLDAABITABNEJMPJSRLDAABITABNEJMPJSRLDAABNEJMPLDAABITABNEJMPJSRLDAA

2,X3,X4,X5,X#6

CHCT2I03PTBPS16K102GA#SBUFF1I02GB#SBUFF2INPT2OUTPT2#0

CHCT2SIGACQ#0FDHSIGACQLATCH1I03PTDATA5#1

I02HAI02YA1FLBFG2I02HB1020DATA6#4

102

1

I02XPI02LSDATA6#4

I02KI02XPI02LSDATA6#4

I02MI02XPI02LSDATA6#4

I02N2I02XPI02LSBPS16KI02N3I02XPDATA6#4

I02N4I02XPI02LSDATA6

16KBPS

CLR "SIGNAL ACQ. I/O #2

CHECK TX INHIBIT

TEST FIFO "O.R.

"

LOAD & STORE 1 CHAR

LOAD & STORE 2 CHAR

LOAD & STORE 3 CHAR

LOAD & STORE 4 CHAR

*16KBPS: ALLOW MORE**l/0 SERVICING*

LOAD & STORE 5 CHAR.

98

1703 BITA #4

1704 BNE I02N51705 JMP I02XP1706 I02N5 JSR I02LS1707 LDAA DATA61708 BITA #4

1709 BNE I02N61710 JMP I02XP1711 I02N6 JSR I02LS1712 LDAA DATA61713 BITA #4

1714 BNE I02N71715 JMP I02XP1716 I02N7 JSR I02LS1717 LDAA DATA61718 BITA #4

1719 BNE I02N81720 JMP I02XP1721 I02N8 JSR I02LS1722 LDAA DATA61723 BITA #4

1724 BNE I02N91725 JMP I02XP1726 I02N9 JSR I02LS1727 LDAA DATA61728 BITA #4

1729 BNE IO2N101730 JMP I02XP1731 IO2N10 JSR I02LS1732 JMP I02XP1733 1020 LDAA DATA61734 BITA #4

1735 BEQ I02XP1736 I02P CLR FLBFG21737 LDAA PA1AD1738 ORAA #2

1739 STAA PA1AD1740 STAA PIA1AD1741 JMP 102

1

1742 I02XP LDAA EMPTY21743 BPL I02XQ1744 LDX INPT21745 STX LGDPT21746 LDAA #11747 STAA EMPTY21748 I02XQ JMP I03PT1749 I02Y LDAA XMTRQ21750 BEQ I02YB1751 LDAA MRFTA1752 ANDA #0DFH1753 STAA MRFTA1754 STAA LATCH

3

1755 CLR XMTRQ21756 LDAA #0FFH1757 STAA EMPTY21758 LDAA PA1AD1759 ANDA #2

LOAD Sc STORE 6 CHAR.

LOAD & STORE 7 CHAR.

LOAD & STORE 8 CHAR.

LOAD & STORE 9 CHAR.

LOAD & STORE 10 CHAR.

LOAD & STORE 11 CHAR,

SET "DATA RDY PORT #2'

**TEST IF SETUP****LAST GOOD DATA PNTR**DO SETUP

CLR "TX ACK'

FIRST TIME THATTX REQ = FALSE

99

1760 BNE 102YA1761 STAA CHCT21762 STAA CHCT2+11763 STAA EMPTY21764 INCA1765 STAA FLBFG21766 LDAA MRFTA1767 ORAA #2

1768 STAA MRFTA1769 STAA LATCH31770 JMP I03PT1771 102YA JMP I02D1772 I02YB LDAA EMPTY21773 BNE I02YA1774 JMP I02YD177 5 102YA1 CLRA1776 STAA XMTRQ21777 STAA EMPTY21778 LDAA PA1AD1779 ANDA #0FDH1780 STAA PIA1AD1781 STAA PA1AD1782 LDAA MRFTA1783 ORAA #21784 ANDA #0DFH1785 STAA MRFTA1786 STAA LATCH31787 I02YC LDAA MRFTA1788 ORAA #2

1789 STAA MRFTA1790 STAA LATCH31791 LDAA SIGACQ1792 ANDA #0DFH1793 STAA SIGACQ1794 STAA LATCH

1

1795 I02YC1 CLR FMSD021796 LDAA #21797 STAA MSD021798 STAA FLBFG21799 JMP I02G1800 I02YD LDAA FLBFG21801 BEQ I02YF1802 STAA XFER21803 LDAA CHCT2+11804 CMPA #101805 BGE I02YE1806 JMP I03PT1807 I02YE CLR FLBFG21808 STAA UT21809 LDAA SIGACQ1810 ANDA #0DFH1811 STAA SIGACQ1812 STAA LATCH

1

1813 LDAA MRFTA1814 ANDA #0FDH1815 STAA MRFTA1816 STAA LATCH3

NO DATA: ABORT INPUT

CLEAR "DATA RDY PORT #2"

RESET I/O #2 FIFOCLR TX ACK I/O #2

**INI 7 I/O PORT****TO OUTPUT****RX BURST DATA**RESET I/O #2 FIFO

SELECT I/O OUTPUT MODE

RCV ELASTIC BUFFER FULL?

SET OUTPUT MODE

CLR REST ON I/O FIFO

100

1817 JSR LD21818 JSR LD21819 LDAA BPS16K1820 BEQ IO2YE01821 JSR LD21822 JSR LD21823 JSR LD21824 JSR LD21825 JSR LD21826 IO2YE0 JMP I03PT1827 I02YE1 LDAA #11828 STAA XFER21829 LDAA UT21830 BNE IO2YE01831 LDAA DATA61832 BITA #4

1833 BEQ I02YC11834 JMP I03PT1835 I02YF LDX CHCT21836 BEQ I02YE11837 LDAA DATA61838 LDAB UT21839 BNE I02YFA1840 BITA #41841 BEQ I02YC11842 I02YFA BITA #040H1843 BEQ I03PT1844 I02YG JSR I02LF1845 LDAA DATA61846 BITA #040H1847 BEQ I03PT1848 I02YH JSR I02LF1849 LDAA DATA61850 BITA #040H1851 BEQ I03PT1852 I02YI JSR I02LF1853 LDAA BPS16K1854 BEQ I03PT1855 I02YJ LDAA DATA61856 BITA #040H1857 BEQ I03PT1858 I02YK JSR I02LF1859 LDAA DATA61860 BITA #040H1861 BEQ I03PT1862 I02YL JSR I02LF1863 LDAA DATA61864 BITA #040H1865 BEQ I03PT1866 I02YM JSR I02LF1867 LDAA DATA61868 BITA #040H1869 BEQ I03PT1870 I02YN JSR I02LF1871 LDAA DATA61872 BITA #040H1873 BEQ I03PT

LOAD FIFO W/6 BUF . CH

.

16 KBPS SO:

LOAD FIFO W/21 BUF. CH.

CHECK FIFO UNDERFLOWBY TESTING FIFO "O.R."**UNDERFLOW**

CHECK FIFO "I.R.": FULL?

OUTPUT 1 CH. TO FIFO

CHECK "I.R.": FULL?

OUTPUT 2 CH. TO FIFO

CHECK "I.R. " : FULL?

OUTPUT 3 CH. TO FIFO

16 KBPS: SERVICE 10 CHARSCHECK "I .R. " : FULL?

OUTPUT 4 CH. TO FIFO

CHECK "I.R.": FULL?

OUTPUT 5 CH. TO FIFO

CHECK "I.R. " : FULL?

OUTPUT 6 CH. TO FIFO

CHECK "I.R." : FULL?

OUTPUT 7 CH. TO FIFO

CHECK "I.R.": FULL?

101

1874 I02YO JSR I02LF1875 LDAA DATA61876 BITA #040H1877 BEQ I03PT1878 I02YP JSR I02LF1879 LDAA DATA61880 BITA #040H1881 BEQ I03PT1882 I02YQ JSR I02LF1883 *********************

1884 *

1885 *

1886 *

1887 I03PT LDAA PTONRX1888 ANDA #4

1889 BEQ I03A11890 CLR P30FF1891 JMP I03A1892 I03A1 LDAA P30FF1893 BEQ I03A21894 JMP I04PT1895 I03A2 STAA CHCT31896 STAA CHCT3+11897 STAA XMTRQ31898 STAA UT31899 LDX #01900 STX LGDPT31901 STAA OUFG31902 STAA EMPTY31903 LDAA #2

1904 STAA MSD031905 INCA1906 STAA FLBFG31907 LDAA MRFTA1908 ORAA #4

1909 ANDA #0BFH1910 STAA MRFTA1911 STAA LATCH

3

1912 STAA P30FF1913 LDAA PA1AD1914 ANDA #0FBH1915 STAA PA1AD1916 STAA PIA1AD1917 LDX #SBUFF31918 STX INPT31919 STX OUTPT31920 LDAA SIGACQ1921 ANDA #0FBH1922 STAA SIGACQ1923 STAA LATCH

1

1924 LDX TXPNTR1925 CPX #INPT31926 BNE I03A31927 CLR SOEN1928 I03A3 JMP I04PT1929 *********************

1930 *

OUTPUT 8 CH. TO FIFO

CHECK "I.R. " : FULL?

OUTPUT 9 CH. TO FIFO

CHECK "I.R. " : FULL?

OUTPUT 10 CH. TO FIFO

PORT #3 ON?

PORT IS OFF

RESET FIFO I/O #3CLR XMT ACK I/O #3

CLEAR "DATA RDY PORT #3

CLR "SIGNAL ACQ. I/O #3'

***********************************************

102

193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987

INPUT SERVICE SUBROUTINE

OBTAIN CHARGET PUT PNTRPUT ITINCR PUT PNTRTEST OVERFLOWBRANCH NO OVERFLOW**OVERFLOW**CLR XMT ACK I/O #3

RESET FIFO I/O #3

SET OUFG FLAG*REMOVE RETURN*

I03LS LDAASTAALDAALDXSTAAINXCPXBNELDAAANDAORAASTAASTAASTAAINSINSJMP

103LSX LDAABEQCPXBNELDXBRA

I03LSA CPXBNELDX

I03LSB STXLDXINXSTXRTS

*

*LOAD I/O #3 FIFO WITH 1 CHAR. ROUTINE

#1

XFER3103

INPT30,X

OUTPT3I03LSXMRFTA#0BFH#4

MRFTALATCH

3

OUFG 3

I04PTBPS16KI03LSA#EBUFF4I03LSB#SBUFF1I03LSB#EBUFF3I03LSB#SBUFF3INPT3CHCT3

CHCT3

16 KBPS

TEST END OF INPUTNOGET INITIAL VALUE

GET CHAR. COUNTINCR COUNTPUT BACK

I03LF LDXLDAABITABNELDAASTAA

I03LF1 INXLDABBEQCPXBNELDXBRA

I03LFA CPXBNELDX

I03LFB STXLDAASTAALDAA

OUTPT3RXINHB#4I03LF10,X103+2

BPS16KI03LFA#EBUFF4I03LFB#SBUFF1I03LFB#EBUFF3I03LFB#SBUFF3OUTPT3#1XFER3FMSD03

IS THE EXTEND TRANSMIT FLAG SET?YES:RX NOT ALLOWED

OUTPUT CH. TO I/O #3 FIFOADJ. OUTPUT PNTR.

16KBPS

WBRWBRWBR

TEST MISSING DO

103

1988 BEQ I03LFC1989 LDX MDOCT31990 DEX1991 STX MDOCT31992 BNE I03LFC1993 LDAA SIGACQ1994 ANDA #0FBH1995 STAA SIGACQ1996 STAA LATCH1

1997 CLR FMSD031998 I03LFC LDX CHCT3 ADJ CHAR. COUNT1999 DEX2000 STX CHCT32001 BNE 103 LFD2002 INS REMOVE RETURN2003 INS2004 JMP I03YE1 GO CHECK UNDERFLOW2005 I03LFD RTS2006 *****************************************************

2007 *

2008 *load :FIFO I/O #3 WITH 3 BUF. CH. ROUTINE2009 *

2010 LD3 LDX OUTPT32011 LDAA 0,X2012 STAA 103 + 2

2013 LDAA i,x2014 STAA 103+22015 LDAA 2,X2016 STAA 103+22017 INX2018 INX2019 INX2020 STX 0UTPT32021 LDX CHCT32022 DEX2023 DEX2024 DEX2025 STX CHCT32026 RTS2027 ***********************************************************

2028 *

2029 ***** BEGIN SERVICING I/O PORT #3 *****

2030 *

2031 I03A LDAA PTONRX RX ONLY?2032 BITA #040H2033 BEQ I03AA2034 JMP I03Y2035 I03AA LDAA DATA12036 BITA #4

2037 BNE I03B2038 JMP I03Y2039 I03B ASIA2040 BPL I03C2041 LDAA XMTRQ32042 BNE I03C2043 LDAA EMPTY32044 BNE I03CA

104

2045 LDX CHCT32046 BEQ I03BB2047 I03BA JMP I03YD2048 I03BB LDAA DATA62049 BITA #2

2050 BNE I03BA2051 I03C LDAA XMTRQ32052 BNE I03D2053 LDAA EMPTY32054 BEQ I03E2055 I03CA CLR EMPTY32056 STAA XMTRQ32057 LDX #0

2058 STX LGDPT32059 LDAA MRFTA2060 ORAA #040H2061 STAA MRFTA2062 STAA LATCH32063 I03D LDAA OUFG32064 BNE I03DA2065 JMP I03H2066 I03DA STAA XFER32067 JMP I04PT2068 I03E LDAA DATA52069 ANDA #12070 BEQ I03F2071 JMP I04PT2072 I03F LDAA #12073 STAA XMTRQ32074 STAA GROUP

3

2075 STAA XFER32076 STAA FLBFG32077 LDAA SIGACQ2078 ORAA #040H2079 ANDA #0FBH2080 STAA SIGACQ2081 STAA LATCH12082 LDAA MRFTA2083 ORAA #4

2084 STAA LATCH

3

2085 CLR 103 + 2

2086 ANDA #0FBH2087 ORAA #040H2088 STAA MRFTA2089 STAA LATCH

3

2090 LDAA BPS16K2091 BEQ 103 FA2092 LDX #SBUFF12093 STX INPT32094 LDX #SBUFF12095 BRA I03FB2096 103 FA LDX #SBUFF32097 STX INPT32098 LDX #SBUFF32099 I03FB STX OUTPT32100 LDAA #0FFH2101 STAA 0,X

R/T SELECTED: CHECK RCV DON

TEST: I/O FIFO UNDERFLOW

BRANCH: NO UNDERFLOW

GET HERE W/MULTIPLETX REQ PER FRAME

SET "TX ACK"

CHECK TX INHIBIT

**INIT FOR PORT #3****DATA TRANSMISSION**

SET I/O INPUT MODECLR "SIG. ACQ. #3"

TOGGLE FIFO'S RESET

CLR PIA-B SIDE

SET XMT ACK I/O #3

+ 6 16KBPS

STUFF 6 ELASTICBUFFER CHARACTERS (CC)

105

210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158

I03G

I03GAI03GB

I03H

IQ3HA

I03HB

1031

I03K

I03M

I03N2

I03N3

IQ3N4

STAASTAASTAASTAASTAALDXSTXJMPLDAABEQLDXBRALDXSTXSTXLDXSTXLDAAANDASTAASTAAJMPLDAAANDABEQJMPLDABBEQJMPLDAABITABNEJMPJSRLDAABITABNEJMPJSRLDAABITABNEJMPJSRLDAABITABNEJMPJSRLDAABNEJMPLDAABITABNEJMPJSR

1,

2,

3,

4,

5,

#6CHCT3

'

I04PTBPS16K103GA#SBUFF1I03GB#SBUFF3INPT3OUTPT3#0CHCT3SIGACQ#0FBHSIGACQLATCH1I04PTDATA5#1I03HAI03YA1FLBFG3I03HB1030DATA6#2

1031I03XPI03LSDATA6#2I03KI03XPI03LSDATA6#2I03MI03XPI03LSDATA6#2I03N2I03XPI03LSBPS16KI03N3I03XPDATA6#2I03N4I03XPI03LS

16KBPS

CLR "SIGNAL ACQ. I/O #3"

CHECK TX INHIBIT

TEST FIFO "O.R.

LOAD Sc STORE 1 CHAR

LOAD & STORE 2 CHAR

LOAD & STORE 3 CHAR

LOAD & STORE 4 CHAR

*16KBPS: ALLOW MORE**I/0 SERVICING*

LOAD & STORE 5 CHAR.

106

2159 LDAA DATA62160 BITA #22161 BNE I03N52162 JMP I03XP2163 I03N5 JSR I03LS2164 LDAA DATA62165 BITA #2

2166 BNE I03N62167 JMP I03XP2168 I03N6 JSR I03LS2169 LDAA DATA62170 BITA #22171 BNE I03N72172 JMP I03XP2173 I03N7 JSR I03LS2174 LDAA DATA62175 BITA #22176 BNE I03N82177 JMP I03XP2178 I03N8 JSR I03LS2179 LDAA DATA62180 BITA #22181 BNE I03N92182 JMP I03XP2183 I03N9 JSR I03LS2184 LDAA DATA62185 BITA #22186 BNE IO3N102187 JMP I03XP2188 IO3N10 JSR I03LS2189 JMP I03XP2190 1030 LDAA DATA62191 BITA #22192 BEQ I03XP2193 I03P CLR FLBFG32194 LDAA PA1AD2195 ORAA #42196 STAA PA1AD2197 STAA PIA1AD2198 JMP 10312199 I03XP LDAA EMPTY32200 BPL I03XQ2201 LDX INPT32202 STX LGDPT32203 LDAA #12204 STAA EMPTY32205 I03XQ JMP I04PT2206 I03Y LDAA XMTRQ32207 BEQ I03YB2208 LDAA MRFTA2209 ANDA #0BFH2210 STAA MRFTA2211 STAA LATCH32212 CLR XMTRQ32213 LDAA #0FFH2214 STAA EMPTY32215 LDAA PA1AD

LOAD & STORE 6 CHAR.

LOD & STORE 7 CHAR.

LOAD & STORE 8 CHAR.

LOAD & STORE 9 CHAR.

LOAD & STORE 10 CHAR.

LOAD & STORE 11 CHAR,

SET "DATA RDY PORT #3"

**TEST IF SETUP****LAST GOOD DATA PNTR**DO SETUP

CLR "TX ACK"

FIRST TIME THATTX REQ = FALSE

107

2216 ANDA #42217 BNE I03YA2218 STAA CHCT32219 STAA CHCT3+12220 STAA EMPTY32221 INCA2222 STAA FLBFG32223 LDAA MRFTA2224 ORAA #4

2225 STAA MRFTA2226 STAA LATCH32227 JMP 104 PT2 22 8 I03YA JMP I03D2229 I03YB LDAA EMPTY32230 BNE I03YA2231 JMP I03YD2 2 32 103YA1 CLRA2233 STAA XMTRQ32234 STAA EMPTY32235 LDAA PA1AD2236 ANDA #0FBH2237 STAA PIA1AD2238 STAA PA1AD2239 LDAA MRFTA2240 ORAA #42241 ANDA #0BFH2242 STAA MRFTA2243 STAA LATCH32244 I03YC LDAA MRFTA2245 ORAA #4

2246 STAA MRFTA2247 STAA LATCH

3

2248 LDAA SIGACQ2249 ANDA #0BFH2250 STAA SIGACQ2251 STAA LATCH12252 I03YC1 CLR FMSD032253 LDAA #2

2254 STAA MSD032255 STAA FLBFG32256 JMP I03G2257 I03YD LDAA FLBFG32258 BEQ I03YF2259 STAA XFER32260 LDAA CHCT3+12261 CMPA #102262 BGE I03YE2263 JMP I04PT2264 I03YE CLR FLBFG32265 STAA UT32266 LDAA SIGACQ2267 ANDA #0BFH2268 STAA SIGACQ2269 STAA LATCH12270 LDAA MRFTA2271 ANDA #0FBH2272 STAA MRFTA

NO DATA: ABORT INPUT

CLEAR "DATA RDY PORT #3

RESET I/O #1 FIFOCLR TX ACK I/O #1

**INIT I/O PORT****TO OUTPUT****RX BURST DATA**RESET I/O #3 FIFO

SELECT I/O OUTPUT MODE

RCV ELASTIC BUFFER FULL?

SET OUTPUT MODE

CLR RESET ON I/O FIFO

108

2273 STAA LATCH32274 JSR LD32275 JSR LD32276 LDAA BPS16K2277 BEQ IO3YE02278 JSR LD32279 JSR LD32280 JSR LD32281 JSR LD32282 JSR LD32283 IO3YE0 JMP 104 PT2284 I03YE1 LDAA #12285 STAA XFER32286 LDAA UT32287 BNE IO3YE02288 LDAA DATA62289 BITA #22290 BEQ I03YC12291 JMP I04PT2292 I03YF LDX CHCT32293 BEQ I03YE12294 LDAA DATA62295 LDAB UT32296 BNE I03YFA2297 BITA #22298 BEQ I03YC12299 I03YFA BITA #020H2300 BEQ I04PT2301 I03YG JSR I03LF2302 LDAA DATA62303 BITA #020H2304 BEQ I04PT2305 I03YH JSR I03LF2306 LDAA DATA62307 BITA #020H2308 BEQ I04PT2309 I03YI JSR I03LF2310 LDAA BPS16K2311 BEQ 104PT2312 I03YJ LDAA DATA62313 BITA #020H2314 BEQ 104 PT2315 I03YK JSR I03LF2316 LDAA DATA62317 BITA #020H2318 BEQ I04PT2319 I03YL JSR I03LF2320 LDAA DATA62321 BITA #020H2322 BEQ I04PT2323 I03YM JSR I03LF2324 LDAA DATA62325 BITA #020H2326 BEQ I04PT2327 I03YN JSR I03LF2328 LDAA DATA62329 BITA #020H

LOAD FIFO W/6 BUF . CH

.

LOAD FIFO W/21 BUF. CH

.

CHECK FIFO UNDERFLOWBY TESTING FIFO "O.R."**UNDERFLOW**

CHECK " I . R .

" : FULL?

OUTPUT 1 CH. TO FIFO

CHECK "I.R. " : FULL?

OUTPUT 2 CH. TO FIFO

CHECK " I . R .

" : FULL?

OUTPUT 3 CH. TO FIFO

16 KBPS : SERVICE 10 CHARSCHECK "I .R. " : FULL?

OUTPUT 4 CH. TO FIFO

CHECK "I .R. " : FULL?

OUTPUT 5 CH. TO FIFO

CHECK "I.R. " : FULL?

OUTPUT 6 CH. TO FIFO

CHECK "I.R.": FULL?

OUTPUT 7 CH. TO FIFO

CHECK "I.R.": FULL?

109

233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386

I03YO

I03YP

I03YQ******

I04PT

BEQ I04PTJSR I03LFLDAA DATA6BITA #020HBEQ I04PTJSR I03LFLDAA DATA6BITA #020HBEQ I04PTJSR I03LF*****************************************************

OUTPUT 8 CH. TO FIFO

CHECK "I.R.": FULL?

OUTPUT 9 CH. TO FIFO

CHECK "I.R. " : FULL?

OUTPUT 10 CH. TO FIFO

I04A1

I04A2

I04A3

LDAA PTONRXANDA #8BEQ I04A1CLR P40FFJMP I04ALDAA P40FFBEQ I04A2JMP BSERVSTAA CHCT4STAA CHCT4+1STAA XMTRQ4STAA UT4LDX #0STX LGDPT4STAA OUFG4STAA EMPTY4LDAA #2STAA MSD04INCASTAA FLBFG4LDAA MRFTAORAA #8ANDA #07FHSTAA MRFTASTAA LATCH3STAA P40FFLDAA PA1ADANDA #0F7HSTAA PA1ADSTAA PIA1ADLDX #SBUFF4STX INPT4STX OUTPT4LDAA SIGACQANDA #0F7HSTAA SIGACQSTAA LATCH1LDX TXPNTRCPX #INPT4BNE I04A3CLR SOENJMP BSERV

PORT #4 ON?

PORT IS OFF

RESET FIFO I/O #4CLR XMT ACK

CLEAR "DATA RDY PORT #4

CLR "SIGNAL ACQ. I/O #4"

***********************************************************

10

2387 *

2388 * INPUT SERVICE SUBROUTINE2389 *

2390 I04LS LDAA #12391 STAA XFER42392 LDAA 104 OBTAIN CHAR2393 LDX INPT4 GET PUT PNTR2394 STAA 0,X PUT IT2395 INX INCR PUT PNTR2396 CPX OUTPT4 TEST OVERFLOW2397 BNE I04LSX BRANCH NO OVERFLOW2398 LDAA MRFTA **OVERFLOW**2399 ANDA #07FH CLR XMT ACK2400 ORAA #8 RESET FIFO2401 STAA MRFTA2402 STAA LATCH32403 STAA OUFG4 SET OUFG FLAG2404 INS *REMOVE RETURN2405 INS *

2406 JMP BSERV2407 I04LSX LDAA BPS16K2408 BEQ I04LSA2409 CPX #EBUFF4 16 KBPS2410 BNE I04LSB2411 LDX #SBUFF12412 BRA I04LSB2413 I04LSA CPX #EBUFF4 TEST END OF INPUT2414 BNE I04LSB NO2415 LDX #SBUFF4 GET INITIAL VALUE2416 I04LSB STX INPT42417 LDX CHCT4 GET CHAR COUNT2418 INX INCR COUNT2419 STX CHCT4 PUT BACK2420 RTS2421 ******************************************

2422 *

2423 *LOAD I/O #4 FIFO WITH 1 CHAR. ROUTINE2424 •

2425 I04LF LDX 0UTPT42426 LDAA RXINHB2427 BITA #8 IS THE EXTEND TRAN!

2428 BNE I04LF1 YES : RX NOT ALLOWED2429 LDAA 0,X2430 STAA 104 + 2 OUTPUT CH. TO I/O •

2431 I04LF1 INX ADJ. OUTPUT PNTR.2432 LDAB BPS16K2433 BEQ I04LFA2434 CPX #EBUFF4 16KBPS2435 BNE I04LFB2436 LDX #SBUFF12437 BRA I04LFB2438 I04LFA CPX #EBUFF42439 BNE I04LFB2440 LDX #SBUFF42441 I04LFB STX OUTPT42442 LDAA #1

2443 STAA XFER4

WBRWBRWBR

111

2444 LDAA FMSD04 TEST MISSING DO2445 BEQ I04LFC2446 LDX MDOCT42447 DEX2448 STX MDOCT42449 BNE I04LFC2450 LDAA SIGACQ2451 ANDA #0F7H2452 STAA SIGACQ2453 STAA LATCH

1

2454 CLR FMSD042455 I04LFC LDX CHCT4 ADJUST CHR COUNT2456 DEX2457 STX CHCT42458 BNE I04LFD2459 INS REMOVE RETURN2460 INS2461 JMP 104YE1 GO CHECK UNDERFLOW2462 I04LFD RTS2463 ***********************************************************

2464 *

2465 *load :FIFO I/O #4 WITH 3 BUF. CH. ROUTINE2466 *

2467 LD4 LDX OUTPT42468 LDAA 0,X2469 STAA 104 + 2

2470 LDAA 1,X2471 STAA 104 + 2

2472 LDAA 2,X2473 STAA 104 + 2

2474 INX2475 INX2476 INX2477 STX OUTPT42478 LDX CHCT42479 DEX2480 DEX2481 DEX2482 STX CHCT42483 RTS2484 ********************************************************

2485 *

2486 ***** BEGIN SERVICING I/O PORT #4 *****

2487 *

2488 I04A LDAA PTONRX RX ONLY?2489 BITA #080H2490 BEQ I04AA2491 JMP I04Y2492 I04AA LDAA DATA12493 BITA #82494 BNE I04B2495 JMP I04Y2496 I04B ASLA2497 BPL I04C2498 LDAA XMTRQ42499 BNE I04C2500 LDAA EMPTY4

112

250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557

I04BAI04BB

I04C

I04CA

I04D

104DA

I04E

I04F

104 FA

I04FB

BNELDXBEQJMPLDAABITABNELDAABNELDAABEQCLRSTAALDXSTXLDAAORAASTAASTAALDAABNEJMPSTAAJMPLDAAANDABEQJMPLDAASTAASTAASTAASTAALDAAORAAANDASTAASTAALDAAORAASTAACLRANDAORAASTAASTAALDAABEQLDXSTXLDXBRALDXSTXLDXSTXLDAA

104CACHCT4I04BB104YDDATA6#1

I04BAXMTRQ4I04DEMPTY4I04EEMPTY4XMTRQ4#0

LGDPT4MRFTA#080HMRFTALATCH

3

OUFG4104DAI04HXFER4BSERVDATA5#1I04FBSERV#1XMTRQ4GROUP4XFER4FLBFG4SIGACQ#080H#0F7HSIGACQLATCH1MRFTA#8LATCH3104 + 2#0F7H#080HMRFTALATCH

3

BPS16K104 FA#SBUFFl+6INPT4#SBUFF1104 FB#SBUFF4+6INPT4#SBUFF4OUTPT4#0FFH

R/T SELECTED: CHECK RCV DON

TEST: I/O FIFO UNDERFLOW

BRANCH: NO UNDERFLOW

GET HERE W/MULTIPLETX REQ PER FRAME

SET "TX ACK"

CHECK TX INHIBIT

**INIT FOR PORT #4****DATA TRANSMISSION**

SELECT I/O INPUT MODECLR "SIG. ACQ. #4"

TOGGLE FIFO'S RESET

CLR PIA-B SIDE

SET XMT ACK I/O #4

16KBPS

STUFF 6 ELASTIC

113

255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614

I04G

I04GAI04GB

I04H

I04HA

I04HB

104

1

I04K

I04M

I04N2

I04N3

STAASTAASTAASTAASTAASTAALDXSTXJMPLDAABEQLDXBRALDXSTXSTXLDXSTXLDAAANDASTAASTAAJMPLDAAANDABEQJMPLDABBEQJMPLDAABITABNEJMPJSRLDAABITABNEJMPJSRLDAABITABNEJMPJSRLDAABITABNEJMPJSRLDAABNEJMPLDAABITABNEJMP

0,

1,

2,

3,

4,

5,

#6CHCT4BSERVBPS16KI04GA#SBUFF1I04GB#SBUFF4INPT4OUTPT4#0CHCT4SIGACQ#0F7HSIGACQLATCH

1

BSERVDATA5#1I04HAI04YA1FLBFG4I04HB1040DATA6#1104

1

I04XPI04LSDATA6#1I04KI04XPI04LSDATA6#1I04MI04XPI04LSDATA6#1I04N2I04XPI04LSBPS16KI04N3I04XPDATA6#1I04N4I04XP

BUFFER CHARACTERS (CC)

16 KBPS

CLR "SIGNAL ACQ. I/O #4"

CHECK TX INHIBIT

TEST FIFO "O.R.

LOAD & STORE 1 CHAR

LOAD & STORE 2 CHAR

LOAD $ STORE 3 CHAR.

LOAD & STORE 4 CHAR

*16 KBPS: ALLOW MORE**I/0 SERVICING*

14

2615 I04N4 JSR I04LS2616 LDAA DATA62617 BITA #1

2618 BNE I04N52619 JMP I04XP2620 I04N5 JSR I04LS2621 LDAA DATA62622 BITA #1

2623 BNE I04N62624 JMP I04XP2625 I04N6 JSR I04LS2626 LDAA DATA62627 BITA #1

2628 BNE I04N72629 JMP I04XP2630 I04N7 JSR I04LS2631 LDAA DATA62632 BITA #1

2633 BNE I04N82634 JMP I04XP2635 I04N8 JSR I04LS2636 LDAA DATA62637 BITA #12638 BNE I04N92639 JMP I04XP2640 I04N9 JSR I04LS2641 LDAA DATA62642 BITA #12643 BNE IO4N102644 JMP I04XP2645 IO4N10 JSR I04LS2646 JMP I04XP2647 1040 LDAA DATA62648 BITA #12649 BEQ I04XP2650 I04P CLR FLBFG42651 LDAA PA1AD2652 ORAA #82653 STAA PA1AD2654 STAA PIA1AD2655 JMP 10412656 I04XP LDAA EMPTY42657 BPL I04XQ2658 LDX INPT42659 STX LGDPT42660 LDAA #12661 STAA EMPTY42662 I04XQ JMP BSERV2663 I04Y LDAA XMTRQ42664 BEQ I04YB2665 LDAA MRFTA2666 ANDA #0 7FH2667 STAA MRFTA2668 STAA LATCH32669 CLR XMTRQ42670 LDAA #0FFH2671 STAA EMPTY4

LOAD & STORE 5 CHAR.

LOAD & STORE 6 CHAR.

LOAD & STORE 7 CHAR.

LOAD & STORE 8 CHAR.

LOAD & STORE 9 CHAR.

LOAD & STORE 10 CHAR.

LOAD Sc STORE 11 CHAR.

SET "DATA RDY PORT #4

**TEST IF SETUP****LAST GOOD DATA PNTR**DO SETUP

CLR "TX ACK'

FIRST TIME THATTX REQ = FALSE

115

267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272^28

I04YA104YB

104YA1

I04YC

I04YC1

104YD

104YE

LDAAANDABNESTAASTAASTAAINCASTAALDAAORAASTAASTAAJMPJMPLDAABNEJMPCLRASTAASTAALDAAANDASTAASTAALDAAORAAANDASTAASTAALDAAORAASTAASTAALDAAANDASTAASTAACLRLDAASTAASTAAJMPLDAABEQSTAALDAACMPABGEJMPCLRSTAALDAAANDASTAASTAALDAAANDA

PA1AD#8104YACHCT4CHCT4+1EMPTY4

FLBFG4MRFTA#8

MRFTALATCH3BSERVI04DEMPTY4I04YA104YD

XMTRQ4EMPTY4PA1AD#0F7HPIA1ADPA1ADMRFTA#8

#07FHMRFTALATCH3MRFTA#8MRFTALATCH3SIGACQ#07FHSIGACQLATCH1FMSD04#2MSD04FLBFG4I04GFLBFG4104YFXFER4CHCT4+1#10I04YEBSERVFLBFG4UT4SIGACQ#07FHSIGACQLATCH

1

MRFTA#0F7H

NO DATA: ABORT INPUT

CLEAR "DATA RDY PORT #4"

RESET I/O #4 FIFOCLR TX ACK I/O #4

**INIT I/O PORT****TO OUTPUT****RX BURST DATA**RESET I/O #4 FIFO

SELECT I/O OUTPUT MODE

RCV ELASTIC BUFFER FULL?

SET OUTPUT MODE

RESET ON I/O FIFO

272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785

IO4YE0104YE1

I04YF

104YFA

I04YG

104YH

I04YI

I04YJ

104YK

104YL

I04YM

I04YN

STAASTAAJSRJSRLDAABEQJSRJSRJSRJSRJSRJMPLDAASTAALDAABNELDAABITABEQJMPLDXBEQLDAALDABBNEBITABEQBITABEQJSRLDAABITABEQJSRLDAABITABEQJSRLDAABEQLDAABITABEQJSRLDAABITABEQJSRLDAABITABEQJSRLDAABITABEQJSRLDAA

MRFTALATCH3LD4LD4BPS16K104YEOLD4 •

LD4LD4LD4LD4BSERV#1XFER4UT4104YEODATA6#1I04YC1BSERVCHCT4104YE1DATA6UT4104YFA#1I04YC1#010HBSERVI04LFDATA6#010HBSERVI04LFDATA6#010HBSERVI04LFBPS16KBSERVDATA6#010HBSERVI04LFDATA6#010HBSERVI04LFDATA6#010HBSERVI04LFDATA6#010HBSERVI04LFDATA6

LOAD FIFO W/6 BUF. CH

.

16 KBPS SO:

LOAD FIFO W/21 BUF. CH

.

CHECK FIFO UNDERFLOWBY TESTING FIFO "O.R."**UNDERFLOW**

CHECK "I.R. " : FULL?

OUTPUT 1 CHAN. TO FIFO

CHECK "I.R." : FULL?

OUTPUT 2 CH. TO FIFO

CHECK "I.R." : FULL?

OUTPUT 3 CH. TO FIFO

16KBPS: SERVICE 10 CHAR.CHECK "I.R. " : FULL?

OUTPUT 4 CH. TO FIFO

CHECK "I.R.": FULL?

OUTPUT 5 CH. TO FIFO

CHECK "I.R. " : FULL?

OUTPUT 6 CH. TO FIFO

CHECK "I.R.": FULL?

OUTPUT 7 CH. TO FIFO

117

278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842

BITABEQ

I04YO JSRLDAABITABEQ

I04YP JSRLDAABITA

I04YQ JSR

#010HBSERVI04LFDATA6#010HBSERVI04LFDATA6#010HI04LF

CHECK "I.R.": FULL?

OUTPUT 8 CH. TO FIFO

CHECK "I.R. " : FULL?

OUTPUT 9 CH. TO FIFO

CHECK "I.R.": FULL?OUTPUT 10 CH. TO FIFO

***********************************************************

BITE SERVICE ROUTINE

BSERV

BSERVA

LDAABITABEQCLRCLRBITABEQLDAABRA

BSERVB

BSERVC

BSERVDBSERVEBSERVF

SERVF1

LDAAASLACOMAANDASTAASTAALDABLDAABEQBITBBNECLRJMPBITBBEQINCLDABLDXBEQLDAABEQCLR

DATA5#8BSERVAIRSBITBITELT#04HBSERVB#0FFHBSERVC

RXINHB

BITELTBITELTLATCH2DATA5TIMEFGBSERVF#010HBSERVETIMEFGSOF#010HBSERVETIMEFGBITELTCHCT1SERVF3XFER1SERVF2XFER1

TEST: SYSTEM BITE RESET

TEST: LAMP TEST

TURN ALL BITE LITES ON

WHEN THE EXTEND TIMER IS SET,IT IS NOT AN ERROR FOR THE PORTOUTPUT TO BE DIFFERENT FROM THEFRAME INPUT, BECAUSE WE AREDISABLING RECEIVE CAPABILITIES

.

THEREFORE WE MUST MASK OUT THEERROR ONLY ON THE PORTS WITHTHE EXTEND TIMER SET. BITS 0-3

IN RXINHB COORESPOND TO PORTS l-<

AND BITS 1-4 COORESPOND TO PORTS1-4 IN LATCH2

.

NO ERROR FOR PORT WITHEXTEND TIMER SET

OUTPUT ALL OTHER ERRORS PRESENT

WBRWBRWBRWBRWBRWBRWBRWBRWBRWBRWBRWBRWBRWBRWBRWBRWBRWBR

TEST 75/16 HZ CLOCK

TEST 75/16 HZ CLOCK

118

2843 BRA BSERVG2844 SERVF2 ORAB #2

2845 BRA BSERVG2846 SERVF3 LDAA XMTRQ12847 BNE SERVF12848 BSERVG LDX CHCT22849 BEQ SERVG32850 SERVG1 LDAA XFER22851 BEQ SERVG22852 CLR XFER22853 BRA BSERVH2854 SERVG2 ORAB #4

2855 BRA BSERVH2856 SERVG3 LDAA XMTRQ22857 BNE SERVG12858 BSERVH LDX CHCT32859 BEQ SERVH32860 SERVH1 LDAA XFER32861 BEQ SERVH22862 CLR XFER32863 BRA BSERVI2864 SERVH2 ORAB #8

2865 BRA BSERVI2866 SERVH3 LDAA XMTRQ32867 BNE SERVH12868 BSERVI LDX CHCT42869 BEQ SERVI32870 SERVI1 LDAA XFER42871 BEQ SERVI22872 CLR XFER42873 BRA BSERVK2874 SERVI2 ORAB #010H2875 BRA BSERVK2876 SERVI3 LDAA XMTRQ42877 BNE SERVI12878 BSERVK STAB BITELT2879 it*******************:

2880 *

2881 * BEGIN SERVICII2882 *

2883 SOF LDAA SOEN2884 BEQ SOF12885 BSR SOFA2886 SOF1 JMP SIF2887 *

2888 SOF2 LDX OUTCHC2889 LDAB #162890 SOF3 LDAA DATA52891 BMI SOF52892 LDAA #033H2893 STAA PIA1BD2894 DEX2895 BNE SOF42896 CLRA2897 STAA SOEN2898 STAA SELFTT2899 STX OUTCHC

I/O #1 BITE ERROR

NO DATA AFTER TX REQ?

I/O #2 BITE ERROR

NO DATA AFTER TX REQ?

I/O #3 BITE ERROR

NO DATA AFTER TX REQ?

I/O #4 BITE ERROR

NO DATA AFTER TX REQ?

**•*•********•******•••*********•-*•*•*•***********

*TX SELF TEST ROUTINE*

FIFO RDY?

OUTPUT TEST CHAR.

DONE SELF TEST TX

119

2900 RTS2901 SOF4 DECB2902 BNE SOF32903 SOF5 STX OUTCHC2904 RTS2905 *

2906 SOFA LDAA SELFTT2907 BNE SOF22908 LDX TXPNTR2909 LDAA DATA52910 BITA #1

2911 BEQ SOFAA2912 CLR SOEN2913 RTS2914 SOFAA LDX 2,X2915 STX TBPNTR2916 LDX TXPNTR2917 LDX 4,X2918 STX TXCHCT2919 LDX TXPNTR2920 LDX 14, X

2921 STX TXLGDP2922 LDAA GRP1FG2923 BNE SOFB2924 JMP SOFY2925 SOFB LDX FILLCT2926 LDAB #0FFH2927 LDAA DATA52928 BPL SOFBA2929 STX FILLCT2930 RTS2931 SOFBA STAB PIA1BD2932 DEX2933 BNE SOFBB2934 CLR GRP1FG2935 JMP SOFD+22936 SOFBB LDAA DATA52937 BPL SOFBC2938 STX FILLCT2939 RTS2940 SOFBC STAB PIA1BD2941 DEX2942 BNE SOFBD2943 CLR GRP1FG2944 JMP SOFE+22945 SOFBD LDAA DATA52946 BPL SOFBE2947 STX FILLCT2948 RTS2949 SOFBE STAB PIA1BD2950 DEX2951 BNE SOFBF2952 CLR GRP1FG2953 JMP SOFF+22954 SOFBF LDAA DATA52955 BPL SOFBG2956 STX FILLCT

TX SELF TEST?

CHECK TX INHIBIT

TX INHIBIT: ABORT

SETUP L.G.D. PNTR FORTX BURST SERVICE

FILL PATTERN BEFORE DATAFIFO RDY? (DATA5-H=LOW)

OUTPUT FILL CHAR #1

FIFO READY?

OUTPUT FILL CHAR #2

FIFO READY?

OUTPUT FILL CHAR #3

FIFO READY?

120

2957 RTS2958 SOFBG STAB PIA1BD2959 DEX2960 BNE SOFBH2961 CLR GRP1FG2962 JMP SOFG+22963 SOFBH LDAA DATA52964 BPL SOFBI2965 STX FILLCT2966 RTS2967 SOFBI STAB PIA1BD2968 DEX2969 BNE SOFBJ2970 CLR GRP1FG2971 JMP SOFH+22972 SOFBJ LDAA DATA52973 BPL SOFBK2974 STX FILLCT2975 RTS2976 SOFBK STAB PIA1BD2977 DEX2978 BNE SOFBL2979 CLR GRP1FG2980 JMP SOFI+22981 SOFBL LDAA DATA52982 BPL SOFBM2983 STX FILLCT2984 RTS2985 SOFBM STAB PIA1BD2986 DEX2987 BNE SOFBN2988 CLR GRP1FG2989 JMP SOFJ+22990 SOFBN LDAA DATA52991 BPL SOFBO2992 STX FILLCT2993 RTS2994 SOFBO STAB PIA1BD2995 DEX2996 BNE SOFBP2997 CLR GRP1FG2998 JMP SOFK+22999 SOFBP LDAA DATA53000 BPL SOFBQ3001 STX FILLCT3002 RTS3003 SOFBQ STAB PIA1BD3004 DEX3005 BNE SOFBR3006 CLR GRP1FG3007 JMP SOFL+23008 SOFBR LDAA DATA53009 BPL SOFBS3010 STX FILLCT3011 RTS3012 SOFBS STAB PIA1BD3013 DEX

OUTPUT FILL CHAR #4

FIFO READY?

OUTPUT FILL CHAR #5

FIFO READY?

OUTPUT FILL CHAR #6

FIFO READY?

OUTPUT FILL CHAR #7

FIFO READY?

OUTPUT FILL CHAR #8

FIFO READY?

OUTPUT FILL CHAR #9

FIFO READY?

OUTPUT FILL CHAR #10

121

3014 BNE SOFBT3015 CLR GRP1FG3016 JMP SOFM+23017 SOFBT LDAA DATA53018 BPL SOFBU3019 STX FILLCT3020 RTS3021 SOFBU STAB PIA1BD3022 DEX3023 BNE SOFBV3024 CLR GRP1FG3025 JMP SOFN+23026 SOFBV LDAA DATA53027 BPL SOFBW3028 STX FILLCT3029 RTS3030 SOFBW STAB PIA1BD3031 DEX3032 BNE SOFBX3033 CLR GRP1FG3034 JMP SOFO+23035 SOFBX LDAA DATA53036 BPL SOFBY3037 STX FILLCT3038 RTS3039 SOFBY STAB PIA1BD3040 DEX3041 BNE SOFBZ3042 CLR GRP1FG3043 JMP SOFP+23044 SOFBZ LDAA DATA53045 BPL SOFB13046 STX FILLCT3047 RTS3048 SOFB1 STAB PIA1BD3049 DEX3050 BNE SOFB23051 CLR GRP1FG3052 JMP SOFQ+23053 SOFB2 LDAA DATA53054 BPL SOFB33055 STX FILLCT3056 RTS3057 SOFB3 STAB PIA1BD3058 DEX3059 BNE SOFB43060 CLR GRP1FG3061 JMP SOFR+23062 SOFB4 LDAA DATA53063 BPL SOFB53064 STX FILLCT3065 RTS3066 SOFB5 STAB PIA1BD3067 DEX3068 BNE SOFB63069 CLR GRP1FG3070 SOFB6 STX FILLCT

FIFO READY?

OUTPUT FILL CHAR #11

FIFO READY?

OUTPUT FILL CHAR #12

FIFO READY?

OUTPUT FILL CHAR #13

FIFO READY?

OUTPUT FILL CHAR #14

FIFO READY?

OUTPUT FILL CHAR #15

FIFO READY?

OUTPUT FILL CHAR #16

122

3071 RTS3072 SOFC LDAA DATA5 FIFO READY?3073 BPL SOFCA3074 JMP SOFS3075 SOFCA LDX TXCHCT3076 BNE SOFCB3077 LDAA #0FFH GET STUFF CHAR3078 STAA TXEND3079 LDX TXPNTR3080 STAA 13,

X

SET PORT'S OUFG3081 BRA SOFCD3082 SOFCB DEX3083 STX TXCHCT3084 LDX TBPNTR3085 LDAA 0,X GET BUFF CHAR3086 INX3087 CPX TXUVAL ADJ BUFF PNTRS3088 BNE SOFCC3089 LDX TXLVAL3090 SOFCC STX TBPNTR3091 CPX TXLGDP LAST GOOD DATA?3092 BNE SOFCD3093 LDX #0 YES3094 STX TXLGDP3095 STAB TXDONE3096 SOFCD STAA PIA1BD OUTPUT CHAR #13097 LDX OUTCHC3098 DEX3099 BNE SOFD3100 JMP SOFT3101 SOFD STX OUTCHC3102 LDAA DATA5 FIFO READY?3103 BPL SOFDA3104 JMP SOFS3105 SOFDA LDX TXCHCT3106 BNE SOFDB3107 LDAA #0FFH GET STUFF CHAR3108 STAA TXEND3109 LDX TXPNTR3110 STAA 13,

X

3111 BRA SOFDD3112 SOFDB DEX3113 STX TXCHCT3114 LDX TBPNTR3115 LDAA 0,X GET BUFF CHAR3116 INX3117 CPX TXUVAL ADJ BUFF PNTRS3118 BNE SOFDC3119 LDX TXLVAL3120 SOFDC STX TBPNTR3121 CPX TXLGDP LAST GOOD DATA?3122 BNE SOFDD3123 LDX #0 YES3124 STX TXLGDP3125 STAB TXDONE3126 SOFDD STAA PIA1BD OUTPUT CHAR #23127 LDX OUTCHC

123

3128 DEX3129 BNE SOFE3130 JMP SOFT3131 SOFE STX OUTCHC3132 LDAA DATA5 FIFO READY?3133 BPL SOFEA3134 JMP SOFS3135 SOFEA LDX TXCHCT3136 BNE SOFEB3137 LDAA #0FFH GET STUFF CHAR3138 STAA TXEND3139 LDX TXPNTR3140 STAA 13,

X

SET PORT ' S UOFG3141 BRA SOFED3142 SOFEB DEX3143 STX TXCHCT3144 LDX TBPNTR3145 LDAA 0,X GET BUFF CHAR3146 INX3147 CPX TXUVAL ADJ BUFF PNTRS3148 BNE SOFEC3149 LDX TXLVAL3150 SOFEC STX TBPNTR3151 CPX TXLGDP LAST GOOD DATA?3152 BNE SOFED3153 LDX #0 YES3154 STX TXLGDP3155 STAB TXDONE3156 SOFED STAA PIA1BD OUTPUT CHAR #33157 LDX OUTCHC3158 DEX3159 BNE SOFF3160 JMP SOFT3161 SOFF STX OUTCHC3162 LDAA DATA5 FIFO READY?3163 BPL SOFFA3164 JMP SOFS3165 SOFFA LDX TXCHCT3166 BNE SOFFB3167 LDAA #0FFH GET STUFF CHAR3168 STAA TXEND3169 LDX TXPNTR3170 STAA 13,

X

SET PORT'S OUFG3171 BRA SOFFD3172 SOFFB DEX3173 STX TXCHCT3174 LDX TBPNTR3175 LDAA 0,X GET BUFF CHAR3176 INX3177 CPX TXUVAL ADJ BUFF PNTRS3178 BNE SOFFC3179 LDX TXLVAL3180 SOFFC STX TBPNTR3181 CPX TXLGDP LAST GOOD DATA?3182 BNE SOFFD3183 LDX #0 YES3184 STX TXLGDP

124

318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241

SOFFD

SOFG

SOFGA

SOFGB

SOFGC

SOFGD

SOFH

SOFHA

SOFHB

SOFHC

STABSTAALDXDEXBNEJMPSTXLDAABPLJMPLDXBNELDAASTAALDXSTAABRADEXSTXLDXLDAAINXCPXBNELDXSTXCPXBNELDXSTXSTABSTAALDXDEXBNEJMPSTXLDAABPLJMPLDXBNELDAASTAALDXSTAABRADEXSTXLDXLDAAINXCPXBNELDXSTXCPX

TXDONEPIA1BDOUTCHC

SOFGSOFTOUTCHCDATA5SOFGASOFSTXCHCTSOFGB#0FFHTXENDTXPNTR13,XSOFGD

TXCHCTTBPNTR0,X

TXUVALSOFGCTXLVALTBPNTRTXLGDPSOFGD#0TXLGDPTXDONEPIA1BDOUTCHC

SOFHSOFTOUTCHCDATA5SOFHASOFSTXCHCTSOFHB#0FFHTXENDTXPNTR13,

X

SOFHD

TXCHCTTBPNTR0,X

TXUVALSOFHCTXLVALTBPNTRTXLGDP

OUTPUT CHAR #4

FIFO READY?

GET STUFF CHAR

SET PORT ' S OUFG

GET BUFF CHAR

ADJ BUFF PNTRS

LAST GOOD DATA?

YES

OUTPUT CHAR #5

FIFO READY?

GET STUFF CHAR

SET PORT'S OUFG

GET BUFF CHAR

ADJ BUFF PNTRS

LAST GOOD DATA?

125

3242 BNE SOFHD3243 LDX #0 YES3244 STX TXLGDP3245 STAB TXDONE3246 SOFHD STAA PIA1BD OUTPUT CHAR #63247 LDX OUTCHC3248 DEX3249 BNE SOFI3250 JMP SOFT3251 SOFI STX OUTCHC3252 LDAA DATA5 FIFO READY?3253 BPL SOFIA3254 JMP SOFS3255 SOFIA LDX TXCHCT3256 BNE SOFIB3257 LDAA #0FFH GET STUFF CHAR3258 STAA TXEND3259 LDX TXPNTR3260 STAA 13,

X

SET PORT ' S OUFG3261 BRA SOFID3262 SOFIB DEX3263 STX TXCHCT3264 LDX TBPNTR3265 LDAA 0,X GET BUFF CHAR3266 INX3267 CPX TXUVAL ADJ BUFF PNTRS3268 BNE SOFIC3269 LDX TXLVAL3270 SOFIC STX TBPNTR3271 CPX TXLGDP LAST GOOD DATA?3272 BNE SOFID3273 LDX #0 YES3274 STX TXLGDP3275 STAB TXDONE3276 SOFID STAA PIA1BD OUTPUT CHAR #73277 LDX OUTCHC3278 DEX3279 BNE SOFJ3280 JMP SOFT3281 SOFJ STX OUTCHC3282 LDAA DATA5 FIFO READY?3283 BPL SOFJA3284 JMP SOFS3285 SOFJA LDX TXCHCT3286 BNE SOFJB3287 LDAA #0FFH GET STUFF CHAR3288 STAA TXEND3289 LDX TXPNTR3290 STAA 13,

X

SET PORT'S OUFG3291 BRA SOFJD3292 SOFJB DEX3293 STX TXCHCT3294 LDX TBPNTR3295 LDAA 0,X GET BUFF CHAR3296 INX3297 CPX TXUVAL ADJ BUFF PNTRS3298 BNE SOFJC

126

3299 LDX TXLVAL3300 SOFJC STX TBPNTR3301 CPX TXLGDP LAST GOOD DATA?3302 BNE SOFJD3303 LDX #0 YES3304 STX TXLGDP3305 STAB TXDONE3306 SOFJD STAA PIA1BD OUTPUT CHAR #8

3307 LDX OUTCHC3308 DEX3309 BNE SOFK3310 JMP SOFT3311 SOFK STX OUTCHC3312 LDAA DATA5 FIFO READY?3313 BPL SOFKA3314 JMP SOFS3315 SOFKA LDX TXCHCT3316 BNE SOFKB3317 LDAA #0FFH GET STUFF CHAR3318 STAA TXEND3319 LDX TXPNTR3320 STAA 13,

X

SET PORT'S OUFG3321 BRA SOFKD3322 SOFKB DEX3323 STX TXCHCT3324 LDX TBPNTR3325 LDAA 0,X GET BUFF CHAR3326 INX3327 CPX TXUVAL ADJ BUFF PNTRS3328 BNE SOFKC3329 LDX TXLVAL3330 SOFKC STX TBPNTR3331 CPX TXLGDP LAST GOOD DATA?3332 BNE SOFKD3333 LDX #0 YES3334 STX TXLGDP3335 STAB TXDONE3336 SOFKD STAA PIA1BD OUTPUT CHAR #93337 LDX OUTCHC3338 DEX3339 BNE SOFL3340 JMP SOFT3341 SOFL STX OUTCHC3342 LDAA DATA5 FIFO READY?3343 BPL SOFLA3344 JMP SOFS3345 SOFLA LDX TXCHCT3346 BNE SOFLB3347 LDAA #0FFH GET STUFF CHAR3348 STAA TXEND3349 LDX TXPNTR3350 STAA 13,

X

SET PORT ' S OUFG3351 BRA SOFLD3352 SOFLB DEX3353 STX TXCHCT3354 LDX TBPNTR3355 LDAA 0,X GET BUFF CHAR

127

3356 INX3357 CPX TXUVAL ADJ BUFF PNTRS3358 BNE SOFLC3359 LDX TXLVAL3360 SOFLC STX TBPNTR3361 CPX TXLGDP LAST GOOD DATA?3362 BNE SOFLD3363 LDX #0 YES3364 STX TXLGDP3365 STAB TXDONE3366 SOFLD STAA PIA1BD OUTPUT CHAR #103367 LDX OUTCHC3368 DEX3369 BNE SOFM3370 JMP SOFT3371 SOFM STX OUTCHC3372 LDAA DATA5 FIFO READY?3373 BPL SOFMA3374 JMP SOFS3375 SOFMA LDX TXCHCT3376 BNE SOFMB3377 LDAA #0FFH GET STUFF CHAR3378 STAA TXEND3379 LDX TXPNTR3380 STAA 13,

X

SET PORT ' S OUFG3381 BRA SOFMD3382 SOFMB DEX3383 STX TXCHCT3384 LDX TBPNTR3385 LDAA 0,X GET BUFF CHAR3386 INX3387 CPX TXUVAL ADJ BUFF PNTRS3388 BNE SOFMC3389 LDX TXLVAL3390 SOFMC STX TBPNTR3391 CPX TXLGDP LAST GOOD DATA?3392 BNE SOFMD3393 LDX #0 YES3394 STX TXLGDP3395 STAB TXDONE3396 SOFMD STAA PIA1BD OUTPUT CHAR #113397 LDX OUTCHC3398 DEX3399 BNE SOFN3400 JMP SOFT3401 SOFN STX OUTCHC3402 LDAA DATA5 FIFO READY?3403 BPL SOFNA3404 JMP SOFS3405 SOFNA LDX TXCHCT3406 BNE SOFNB3407 LDAA #0FFH GET STUFF CHAR3408 STAA TXEND3409 LDX TXPNTR3410 STAA 13,

X

SET PORT' OUFG3411 BRA SOFND3412 SOFNB DEX

128

3413 STX TXCHCT3414 LDX TBPNTR3415 LDAA 0,X GET BUFF CHAR3416 INX3417 CPX TXUVAL AND BUFF PNTRS3418 BNE SOFNC3419 LDX TXLVAL3420 SOFNC STX TBPNTR3421 CPX TXLGDP LAST GOOD DATA?3422 BNE SOFND3423 LDX #0 YES3424 STX TXLGDP3425 STAB TXDONE3426 SOFND STAA PIA1BD OUTPUT CHAR #123427 LDX OUTCHC3428 DEX3429 BNE SOFO3430 JMP SOFT3431 SOFO STX OUTCHC3432 LDAA DATA5 FIFO READY?3433 BPL SOFOA3434 JMP SOFS3435 SOFOA LDX TXCHCT3436 BNE SOFOB3437 LDAA #0FFH GET STUFF CHAR3438 STAA TXEND3439 LDX TXPNTR3440 STAA 13,

X

SET PORT ' S OUFG3441 BRA SOFOD3442 SOFOB DEX3443 STX TXCHCT3444 LDX TBPNTR3445 LDAA 0,X GET BUFF CHAR3446 INX3447 CPX TXUVAL ADJ BUFF PNTRS3448 BNE SOFOC3449 LDX TXLVAL3450 SOFOC STX TBPNTR3451 CPX TXLGDP LAST GOOD DATA?3452 BNE SOFOD3453 LDX #0 YES3454 STX TXLGDP3455 STAB TXDONE3456 SOFOD STAA PIA1BD OUTPUT CHAR #133457 LDX OUTCHC3458 DEX3459 BNE SOFP3460 JMP SOFT3461 SOFP STX OUTCHC3462 LDAA DATA5 FIFO READY?3463 BPL SOFPA3464 JMP SOFS3465 SOFPA LDX TXCHCT3466 BNE SOFPB3467 LDAA #0FFH GET BUFF CHAR3468 STAA TXEND3469 LDX TXPNTR

129

3470 STAA 13,

X

SET PORT'S OUFG3471 BRA SOFPD3472 SOFPB DEX3473 STX TXCHCT3474 LDX TBPNTR3475 LDAA 0,X GET BUF CHAR3476 INX3477 CPX TXUVAL ADJ BUFF PNTRS3478 BNE SOFPC3479 LDX TXLVAL3480 SOFPC STX TBPNTR3481 CPX TXLGDP LAST GOOD DATA?3482 BNE SOFPD3483 LDX #0 YES3484 STX TXLGDP3485 STAB TXDONE3486 SOFPD STAA PIA1BD OUTPUT CHAR #143487 LDX OUTCHC3488 DEX3489 BNE SOFQ3490 JMP SOFT3491 SOFQ STX OUTCHC3492 LDAA DATA5 FIFO READY?3493 BPL SOFQA3494 JMP SOFS3495 SOFQA LDX TXCHCT3496 BNE SOFQB3497 LDAA #0FFH GET STUFF CHAR3498 STAA TXEND3499 LDX TXPNTR3500 STAA 13,

X

SET PORT ' S OUFG3501 BRA SOFQD3502 SOFQB DEX3503 STX TXCHCT3504 LDX TBPNTR3505 LDAA 0,X GET BUFF CHAR3506 INX3507 CPX TXUVAL ADJ BUFF PNTRS3508 BNE SOFQC3509 LDX TXLVAL3510 SOFQC STX TBPNTR3511 CPX TXLGDP LAST GOOD DATA?3512 BNE SOFQD3513 LDX #0 YES3514 STX TXLGDP3515 STAB TXDONE3516 SOFQD STAA PIA1BD OUTPUT CHAR #153517 LDX OUTCHC3518 DEX3519 BEQ SOFT3520 SOFR STX OUTCHC3521 LDAA DATA5 FIFO READY?3522 BPL SOFRA3523 JMP SOFS3524 SOFRA LDX TXCHCT3525 BNE SOFRB3526 LDAA #0FFH GET STUFF CHAR

130

35273528352935303531 SOFRB35323533353435353536353735383 53 9 SOFRC354035413542354335443 54 5 SOFRD35463547354835493550 SOFS35513552355335543555355635573558355935603561356235633564 SOFT35653 566 SOFTA35673568356935703571357235733574357535763577357835793580358135823583

STAALDXSTAABRADEXSTXLDXLDAAINXCPXBNELDXSTXCPXBNELDXSTXSTABSTAALDXDEXBEQSTXLDXLDAALDABSTAASTABLDAALDABSTAASTABLDAALDABSTAASTABRTSLDAABEQCLRBSTABSTABSTABSTABLDAAANDASTAASTAALDXSTABSTABSTABSTABSTABLDABSTABLDAA

TXENDTXPNTR13,

X

SOFRD

TXCHCTTBPNTR0,X

TXUVALSOFRCTXLVALTBPNTRTXLGDPSOFRD#0TXLGDPTXDONEPIA1BDOUTCHC

SOFTOUTCHCTXPNTRTXCHCTTXCHCT+14,X5,XTBPNTRTBPNTR+12,X3,XTXLGDPTXLGDP+114,

X

15,

X

TXENDSOFTB

TXENDTXDONETXCHCTTXCHCT+1XMASKPA1ADPA1ADPIA1ADTXPNTR8,X13,

X

6,X4,X5,X#3

7,XMASKR

SET PORT'S OUFG

GET BUFF CHAR

ADJ BUFF PNTRS

LAST GOOD DATA?

YES

OUTPUT CHAR #16

STORE BUFF PNTRS

RESTORE BUFF CHAR COUNT

RESTORE BUFF OUTPUT PNTR

RESTORE L.G.D. PNTR

CLR "DATA RDY PORT-

CLR TX REQ FLAGCLR OUFGCLR EMPTYCLR CHCT

SET FLBFGTX ACK OF I/O PORT

131

358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640

SOFTB

SOFU

SOFY

SOFYXXSOFYA

SOFYA1

SOFYB

SOFYB1

SOFYC

SOFYC1

SOFYD

SOFYD1

ANDALDABCOMBSTABORAASTAASTAABRALDAABEQLDAACOMAANDABEQCLRASTAABRALDABLDAABNELDAABEQLDAACOMAANDABEQCLRASTAAJMPLDXLDAABPLRTSSTABDEXBEQLDAABPLSTXRTSSTABDEXBEQLDAABPLSTXRTSSTABDEXBNEJMPLDAABPLSTXRTSSTABDEX

MRFTAXMASK

XMASKXMASKMRFTALATCH3SOFUTXDONESOFUXMASK

DATA1SOFTA

SOENSOFS#0FFHTXENDSOFYATXDONESOFYXXXMASK

DATA1SOFYXX

TXDONESOFCOUTCHCDATA5SOFYA1

AND SET FIFO'S MR

SOFTADATA5SOFYB1OUTCHC

SOFTADATA5SOFYC1OUTCHC

TEST PORT'S TX REQ INPUT

TEST PORT'S TX REQ INPUT

BRANCH IF TX REQ =

GET HERE WITH MULTIPLETX REQS. PER FRAME

FIFO RDY?

PIA1BD OUTPUT FILL CHAR #1

FIFO RDY?

PIA1BD OUTPUT FILL CHAR #2

FIFO RDY?

PIA1BD OUTPUT FILL CHAR #3

SOFYDSOFTADATA5SOFYD1OUTCHC

FIFO RDY?

PIA1BD OUTPUT FILL CHAR #4

132

3641 BNE3642 JMP364 3 SOFYE LDAA3644 BPL3645 STX3646 RTS3 64 7 SOFYE

1

STAB3648 DEX3649 BNE3650 JMP3651 SOFYF LDAA3652 BPL3653 STX3654 RTS3 655 SOFYF1 STAB3656 DEX3657 BNE3658 JMP3659 SOFYG LDAA3660 BPL3661 STX3662 RTS3663 SOFYG1 STAB3664 DEX3665 BNE3666 JMP366 7 SOFYH LDAA3668 BPL3669 STX3670 RTS3671 SOFYH1 STAB3672 DEX3673 BNE3674 JMP3675 SOFYI LDAA3676 BPL3677 STX3678 RTS367 9 SOFYI

1

STAB3680 DEX

SOFYESOFTADATA5SOFYE1OUTCHC

FIFO RDY?

PIA1BD OUTPUT FILL CHAR #5

SOFYFSOFTADATA5SOFYF1OUTCHC

PIA1BD

SOFYGSOFTADATA5SOFYG1OUTCHC

FIFO RDY?

OUTPUT FILL CHAR #6

FIFO RDY?

PIA1BD OUTPUT FILL CHAR #7

SOFYHSOFTADATA5SOFYH1OUTCHC

PIA1BD

SOFYISOFTADATA5SOFYHOUTCHC

FIFO RDY?

OUTPUT FILL CHAR #8

FIFO RDY?

PIA1BD OUTPUT FILL CHAR #9

3681 BNE SOFYJ3682 JMP SOFTA3683 SOFYJ LDAA DATA5 FIFO RDY?3684 BPL SOFYJ13685 STX OUTCHC3686 RTS3687 SOFYJ1 STAB PIA1BD OUTPUT FI3688 DEX3689 BNE SOFYK3690 JMP SOFTA3691 SOFYK LDAA DATA5 FIFO RDY?3692 BPL SOFYK13693 STX OUTCHC3694 RTS3695 SOFYK1 STAB PIA1BD OUTPUT FI3696 DEX3697 BNE SOFYL

3698369937003701370237033704370537063" 7

3'3

3709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754

SOFYL

SOFYL1

SOFYM

SOFYM1

SOFYN

SOFYN1

SOFYO

SOFYOl

SOFYP

SOFYP1

JMPLDAABPLSTXRTSSTABDEXBNEJMPLDAABPLSTXRTSSTABDEXBNEJMPLDAABPLSTXRTSSTABDEXBNEJMPLDAABPLSTXRTSSTABDEXBNEJMPLDAABPLSTXRTSSTABDEXBNEJMP

SOFTADATA5SOFYL1OUTCHC

FIFO RDY?

PIA1BD OUTPUT FILL CHAR #12

SOFYMSOFTADATA5SOFYM1OUTCHC

PIA1BD

SOFYNSOFTADATA5SOFYN1OUTCHC

SOFYOSOFTADATA5SOFYOlOUTCHC

PIA1BD

SOFYPSOFTADATA 5

SOFYP1OUTCHC

PIA1BD

SOFYQSOFTA

FIFO RDY?

OUTPUT FILL CHAR #13

FIFO RDY?

PIA1BD OUTPUT FILL CHAR #14

FIFO RDY?

OUTPUT FILL CHAR #15

FIFO RDY?

OUTPUT FILL CHAR #16

SOFYQ STX OUTCHCRTS

***************************** + ** + *************••**********•**

* BEGIN SERVICING SYSTEM INPUT FIFO*

*

SIF LDAA SIENBNE SIFAJMP TDMA

INCHCSIF1 LDXLDAB #16

SIF2 LDAA DATA1BPL SIF6LDAA DATA2

*RX SELF iiST ROUTINE*

CHAR IN RX FIFO?

LOAD CHAR

134

3755 CMPA #033H3756 BEQ SIF33757 STAB STERR3758 SIF3 DEX3759 BNE SIF53760 CLRA3761 STAA SIEN3762 STAA SELFTR3763 STX INCHC3764 LDAA PA1AD3765 LDAB STERR3766 BNE SIF3A3767 ANDA #0 7FH3768 BRA SIF43769 SIF3A ORAA #080H3770 SIF4 STAA PA1AD3771 STAA PIA1AD3772 ANDA #080H3773 ORAA BITELT3774 STAA BITELT3775 STAA LATCH23776 CLR STERR3777 JMP TDMA3778 SIF5 DECB3779 BNE SIF23780 SIF6 STX INCHC3781 JMP TDMA3782 *

3783 SIFA LDAA SELFTR3784 BNE SIF13785 LDAA INPTRC3786 BEQ SIFA1A3787 LDX RCRXPT3788 SIFR LDAA DATA13789 BMI SIFRA3790 SIFR1 STX RCRXPT3791 JMP TDMA3792 SIFRA LDAA DATA23793 STAA

; X3794 INX3795 CPX #ERCRX3796 BNE SIFR3797 SEI3798 LDX #SRCRX3799 LDAA o,x3800 STAA ACIAD3801 INX3802 LDAA #0BDH3803 STAA AC IACS3804 STAA TXIRFG3805 STX RCRXPT3806 CLR SIEN3807 CLI3808 JMP TDMA3809 ********************

3810 *

3811 *FILL MISSING RX BUR:

CORRECT CHARACTER?

CLR DBP SELF TEST FAIL

SET DBP SELF TEST FAIL

ADJUST SELF TESTFAIL BITE LITE

RX SELF TEST?

CHAR IN INPUT FIFO?

LOAD & STORE FIFO CHAR

BUFFER FULL?

LOAD ACIA WITH 1

R/CCOW RX CHARS

.

135

381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868

SIFRBSIFRC

SIFRD

SIFRE

SIFA1A

SIFA1C

SIFA1B

SIFA1

SIFA2

LDABLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNECLRJMPSTXDECBBNEJMP

LDXLDAABNELDAAANDABNECLRCLRJMPLDXSTXLDXLDXSTXLDAABNELDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNE

#16#0FFHRBPNTR0,X

RXUVALSIFRDRXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFREFILLFGSIFQINCHC

SIFRCSIFP

RXPNTR8,XSIFA1CPTONRXMASKIOSIFA1BSIENFILLFGTDMA0,XRBPNTRRXPNTR4,XRBCHCTFILLFGSIFRBDATA1SIFA1TDMADATA2RBPNTR0,X

RXUVALSIFA2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFB

INIT STORE COUNTER

ADJ PNTRS

TEST FIFO CH CNT

DEC STORE COUNTER

SETUP RCV PNTRSTEST PORT'S TX REQ FLAG

TEST IF PORT IS ON

*ABORT RX BURST: TX REQ**OR PORT IS OFF*

FILL BURST WITH "FF"?

LOAD Sc STORE CHAR #1

ADJ PNTRS

TEST FIFO CH CNT

136

386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925

SIFB

SIFB1

SIFB2

SIFC

SIFC1

SIFC2

SIFD

SIFD1

SIFD2

JMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNEJMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNEJMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNE

SIFQINCHCDATA1SIFB1SIFPDATA2RBPNTR0,X

RXUVALSIFB2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFCSIFQINCHCDATA1SIFC1SIFPDATA2RBPNTR0,X

RXUVALSIFC2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFDSIFQINCHCDATA1SIFD1SIFPDATA2RBPNTR0,X

RXUVALSIFD2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFE

LOAD & STORE FIFO CHAR #2

ADJ PNTRS

TEST FIFO CHAR COUNT

LOAD & STORE FIFO CHAR #3

ADJ PNTRS

TEST FIFO CHAR COUNT

LOAD Sc STORE FIFO CHAR #4

ADJ PNTRS

TEST FIFO CHAR COUNT

137

392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982

SIFE

SIFE1

SIFE2

SIFF

SIFF1

SIFF2

SIFG

SIFG1

SIFG2

JMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNEJMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNEJMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNE

SIFQINCHCDAT£ 1

SIF1 1

SIFPDATA2RBPNTR0,X

RXUVALSIFE2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFFSIFQINCHCDATA1SIFF1SIFPDATA2RBPNTR0,X

RXUVALSIFF2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFGSIFQINCHCDATA1SIFG1SIFPDATA2RBPNTR0,X

RXUVALSIFG2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFH

LOAD & STORE FIFO CHAR #5

ADJ PNTRS

TEST FIFO CHAR COUNT

LOAD & STORE FIFO CHAR #6

ADJ PNTRS

TEST FIFO CHAR COUNT

LOAD Sc STORE FIFO CHAR #7

ADJ PNTRS

TEST FIFO CHAR COUNT

138

398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039

SIFH

SIFH1

SIFH2

SIFI

SIFI1

SIFI2

SIFX

SIFX1

SIFX2

JMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNEJMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNEJMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNE

SIFQINCHCDATA1SIFH1SIFPDATA2RBPNTR0,X

RXUVALSIFH2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFISIFQINCHCDATA1SIFI1SIFPDATA2RBPNTR0,X

RXUVALSIFI2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFXSIFQINCHCDATA1SIFX1SIFPDATA2RBPNTR0,X

RXUVALSIFX2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFJ

LOAD & STORE FIFO CHAR #8

ADJ PNTRS

TEST FIFO CHAR COUNT

LOAD Sc STORE FIFO CHAR #9

ADJ PNTRS

TEST FIFO CHAR COUNT

LOAD Sc STORE FIFO CHAR #10

ADJ PNTRS

TEST FIFO CHAR COUNT

139

404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096

SIFJ

SIFJ1

SIFJ2

SIFK

SIFK1

SIFK2

SIFL

SIFL1

SIFL2

JMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNEJMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNEJMPSTXLDAABMIJMPLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBNE

SIFQINCHCDATA1SIFJ1SIFPDATA2RBPNTR0,X

RXUVALSIFJ2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFKSIFQINCHCDATA1SIFK1SIFPDATA2RBPNTR0,X

RXUVALSIFK2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFLSIFQINCHCDATA1SIFL1SIFPDATA2RBPNTR0,X

RXUVALSIFL2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFM

LOAD & STORE FIFO CHAR #11

ADJ PNTRS

TEST FIFO CHAR COUNT

LOAD Sc STORE FIFO CHAR #12

ADJ PNTRS

TEST FIFO CHAR COUNT

LOAD & STORE FIFO CHAR #13

ADJ PNTRS

TEST FIFO CHAR COUNT

140

409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153

SIFM

SIFM1

SIFM2

SIFN

SIFN1

SIFN2

SIFO

SIFOl

SIF02

SIFP

JMPSTXLDAABPLLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBEQSTXLDAABPLLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBEQSTXLDAABPLLDAALDXSTAAINXCPXBNELDXSTXLDXINXSTXLDXDEXBEQSTXLDXLDAALDABSTAA

SIFQINCHCDATA1SIFPDATA2RBPNTR0,X

RXUVALSIFM2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFQINCHCDATA1SIFPDATA2RBPNTR0,X

RXUVALSIFN2RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFQINCHCDATA1SIFPDATA2RBPNTR0,X

RXUVALSIF02RXLVALRBPNTRRBCHCT

RBCHCTINCHC

SIFQINCHCRXPNTRRBCHCTRBCHCT+14,X

LOAD Sc STORE FIFO CHAR #14

ADJ PNTRS

TEST FIFO CHAR COUNT

LOAD & STORE FIFO CHAR #15

ADJ PNTRS

TEST FIFO CHAR COUNT

LOAD & STORE FIFO CHAR #16

ADJ PNTRS

TEST FIFO CHAR COUNT

UPDATE PORT ' S BUFF PNTRS

141

415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210

SIFQ

STAB 5,XLDAA RBPNTRLDAB RBPNTR+1STAA 0,XSTAB 1,XJMP TDMACLRASTAA SIENBRA SIFP

*************************************************************

INTERRUPT REQUEST SERVICE ROUTINE

IRS

IRSA

IRSB

IRSC

IRSD

IRSE

IRSF

LDABLDAABEQBITBBEQLDXLDAASTAAINXSTXCPXBNELDAASTAACLRBITBBNERTIBITBBNELDAASTAARTIBITBBEQLDAASTAALDAALDABBEQDECBBEQDECBBNELDXSTAAINXSTXCPXBNELDAASTAABRA

AC IACSTXIRFGIRSC#2

IRSCRCRXPTo,xACIAD

RCRXPT#ERCRXIRSB#0 9DHAC IACSTXIRFG#1IRSE

#1

IRSE#1IRSBIT

#070HIRSF#1IRSBITACIADRCFGIRSJ

IRSG

IRSNRTXPT0,X

RTXPT#ERTXBIRSI#1RDRDYIRSH

TDR EMPTY?

OUTPUT CHAR TO AC I

A

CLR TX IRQ ENABLE

RDR FULL?

RCCOW/CCOW BITE ERROR:IRQ ERROR OR SCU FORMAT ERR

AC IA RX ERRORS?

LOAD AC IA RX CHAR

STORE CHAR IN RCCOW BUFFER

SET FOR RCCOW DATA READY

142

4211 IRSG LDX CTXPT4212 STAA 0,X4213 INX4214 STX CTXPT4215 CPX #ECTXB4216 BNE IRSI4217 LDAA #2

4218 STAA CDRDY4219 IRSH CLR RCFG4220 IRSI RTI4221 IRSJ CMPA #0A3H4222 BNE IRSL4223 LDX #SCTXB4224 STX CTXPT4225 LDAB #1

4226 IRSK STAB RCFG4227 RTI4228 IRSL CMPA #0A4H4229 BNE IRSM4230 LDX #SRTXB4231 STX RTXPT4232 LDAB #2

4233 BRA IRSK4234 IRSM CMPA #0A9H4235 BEQ IRSMA4236 CMPA #0ABH4237 BEQ IRSMA4238 BRA IRSD4239 IRSMA TAB4240 ANDB #02H4241 STAB RXINHB4242 LDAB #3

4243 STAB RC3FG4244 BRA IRSK4245 IRSN LDAB RC3FG4246 CMPB #3

4247 BEQ IRSQ4248 CMPB #2

4249 BEQ IRSO4250 TAB4251 RORB4252 RORB4253 RORB4254 RORB4255 ANDB #0CH4256 ORAB RXINHB4257 STAB RXINHB4258 ANDA #03FH4259 STAA BRATE24260 TAB4261 ANDB #7

4262 ANDA #038H4263 ASLB4264 ASLB4265 ASLB4266 STAB CHRAT34267 STAA CHRAT4

STORE CHAR IN CCOW BUFFER

SET FOR CCOW DATA RDY

GET RXINHB BIT 2 FROM A9/A11 BIT 2

WBRWBRWBRWBRWBRWBR

GET RXINHB BITS 4,3 FROM BITS 7,6

REMOVE RXINHB BITS BEFORE USINGPORT BIT RATES (3 & 4)

WBRWBRWBRWBRWBRWBRWBRSEFWBR

143

426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324

IRSO

IRSP

IRSQ

CLRCLRRTITABROLBROLBROLBANDBORABSTABANDASTAATABANDBSTABTABANDBANDAASLBASLBASLBSTABSTAADECRTISTAABRA

RCFGRC3FG

GET RXINHB BIT FROM BIT 6

#01HRXINHBRXINHB#0BFHBRATE1

#080HBPS16K

#7#038H

CHRAT1CHRAT2RC3FG

PTONRXIRSP

REMOVE RXINHB BIT BEFORE USINGPORT BIT RATES (1 & 2)

WBRWBRWBRWBRWBRWBRSEFWBR

WBR

PORT ON & RX ONLY INFO

************************************************************

* LOAD RX ELASTIC BUFFER FOR 16 KBPS*

STUFF LDX #SBUFF1CLRB

STUFA STAA 0,XINXINCBBNE STUFARTS

********************************************************

INSERR BRA INSERR BAD INTERRUPT- CRASH*

************************************************************

* PROGRAM VERSION, ROM CHECKSUM VALUES, AND INTERRUPT VECTORS*

***********************************************************

ORGPGMVRS FCBCKSMB RMBCKSMA RMB

FDBFDBFDBFDB

*

END

0FFF5H4

1

1

IRSINSERRINSERRPWRON

PWRON

** PROGRAM VERSION**MSB OF CHECKSUM - BD . PROGRAMMER SUPPLIES VALUELSB OF CHECKSUM - SEE 98-P082 93T FOR DETAILS.IRQ VECTORSWI ERRORNMI ERRORRESTART VECTOR

144

APPENDIX E

DATA BUFFER PROCESSOR LABEL CROSS REFERENCE

Label NameDefined

On Referenced OnBITRAT 642 637 943

BSERV 2801 2351 2385 2406 2524 2528 2566 2580 2662

2684 2720 2740 2748 2757 2761 2765 2768

2771 2775 2779 2783 2787 2791

BSERVA 2806 2803

BSERVB 2821 2807

BSERVC 2826 2809

BSERVD 2832

BSERVE 2833 2831 2835

BSERVF 2834 2829

BSERVG 2848 2843 2845

BSERVH 2858 2853 2855

BSERVI 2868 2863 2865

BSERVK 2878 2873 2875

CKSMA 4318

CKSMB 4317

CLEAR 116 29 126

CLEARA 118 120

INIT 68 11 175

INSERR 4308 4308

IOIA 1128 988

I01A1 989 986

I01A2 992 990

I01A3 1025 1023

IOIAA 1132 1130

IOIB 1136 1134

IOIBA 1144 1147

IOIBB 1145 1143

IOIC 1148 1137 1139

IOICA 1152 1141

IOID 1160 1149 1314

IOIE 1164 1151

IOIF 1168 1166

IOIG 1200 1342

IOIH 1210 1161

101 HA 1214 1212

I01HB 1217 1215

ion 1221 1219 1284

IOIK 1226 1224

145

Label NameDefined

On Referenced OnI01LF 1065 1387 1391 1395 1401 1405 1409 1413 1417

1421 1425

I01LF1 1071 1068

IOILFA 1078 1073

IOILFB 1081 1075 1077 1079

IOILFC 1095 1085 1089

IOILFD 1102 1098

IOILS 1030 1221

1264

1226

1269

1231 1236 1244 1249

1274

1254 1259

IOILSA 1053 1048

IOILSB 1056 1050 1052 1054

IOILSX 1047 1037

IOIM 1231 1229

IO1N10 1274 1272

I01N2 1236 1234

I01N3 1240 1238

I01N4 1244 1242

I01N5 1249 1247

I01N6 1254 1252

I01N7 1259 1257

I01N8 1264 1262

I01N9 1269 1267

IOIO 1276 1216

I01P 1279

IOIPT 984 712

976

729 739 778 816 854 927 932

IOIXP 1285 1220

1258

1225

1263

1230 1235 1239 1243

1268 1273 1275 1278

1248 1253

I01XQ 1291 1286

I01Y 1292 1131 1135

I01YA 1314 1303 1316

I01YA1 1318 1213

I01YB 1315 1293

IOIYC 1330

I01YC1 1338 1376 1384

I01YD 1343 1144 1317

IOIYE 1350 1348

I01YEO 1369 1363 1373

I01YE1 1370 1101 1379

I01YF 1378 1344

I01YFA 1385 1382

IOIYG 1387

I01YH 1391

I01YI 1395

101YJ 1398

146

Label NameDefined

On Referenced OnI01YK 1401

IOIYL 1405

101YM 1409

I01YN 1413

I01Y0 1417

I01YP 1421

I01YQ 1425

I02A 1574 1434

102A

1

1435 1432

I02A2 1438 1436

I02A3 1471 1469

I02AA 1578 1576

I02B 1582 1580

I02BA 1590 1593

I02BB 1591 1589

I02C 1594 1583 1585

I02CA 1598 1587

I02D 1606 1595 1771

I02DA 1609 1607

I02E 1611 1597

I02F 1615 1613

I02FA 1639 1634

I02FB 1642 1638

I02G 1653 1799

I02GA 1657 1654

I02GB 1658 1656

I02H 1667 1608

I02HA 1671 1669

I02HB 1674 1672

1021 1678 1676 1741

I02K 1683 1681

I02LF 1511 1844

1878

1848 1852 1858 1862 1866 1870 1874

1882

I02LF1 1517 1514

I02LFA 1524 1519

I02LFB 1527 1521 1523 1525

I02LFC 1541 1531 1535

I02LFD 1548 1544

I02LS 1476 1678

1721

1683 1688 1693 1701 1706 1711 1716

1726 1731

I02LSA 1499 1494

I02LSB 1502 1496 1498 1500

I02LSX 1493 1483

I02M 1688 1686

IO2N10 1731 1729

I02N2 1693 1691

147

Label NameDefined

On Referenced OnI02N3 1697 1695

I02N4 1701 1699

102N5 1706 1704

I02N6 1711 1709

I02N7 1716 1714

I02N8 1721 1719

I02N9 1726 1724

1020 1733 1673

I02P 1736

102PT 1430 991

1313

1400

1025

1349

1404

1046

1369

1408

1163 1167 1199

1377 1386 1390

1412 1416 1420

1209 1291

1394 1397

1424

I02XP 1742 1677

1715

1682

1720

1687

1725

1692 1696 1700

1730 1732 1735

1705 1710

I02XQ 1748 1743

I02Y 1749 1577 1581

I02YA 1771 1760 1773

102YA1 1775 1670

I02YB 1772 1750

I02YC 1787

I02YC1 1795 1833 1841

102YD 1800 1590 1774

I02YE 1807 1805

IO2YE0 1826 1820 1830

I02YE1 1827 1547 1836

I02YF 1835 1801

I02YFA 1842 1839

I02YG 1844

I02YH 1848

I02YI 1852

I02YJ 1855

I02YK 1858

I02YL 1862

I02YM 1866

I02YN 1870

I02Y0 1874

I02YP 1878

I02YQ 1882

I03A 2031 1891

I03A1 1892 1889

I03A2 1895 1893

I03A3 1928 1926

I03AA 2035 2033

I03B 2039 2037

I03BA 2047 2050

I03BB 2048 2046

148

Label NameDefined

On Referenced OnI03C 2051 2040 2042

I03CA 2055 2044

I03D 2063 2052 2228

103DA 2066 2064

I03E 2068 2054

103 F 2072 2070

103FA 2096 2091

I03FB 2099 2095

I03G 2110 2256

I03GA 2114 2111

I03GB 2115 2113

I03H 2124 2065

I03HA 2128 2126

I03HB 2131 2129

1031 2135 2133 2198

I03K 2140 2138

I03LF 1968 2301

2335

2305

2339

2309 2315 2319 2323 2327 2331

I03LF1 1974 1971

I03LFA 1981 1976

I03LFB 1984 1978 1980 1982

I03LFC 1998 1988 1992

I03LFD 2005 2001

I03LS 1933 2135

2178

2140

2183

2145

2188

2150 2158 2163 2168 2173

I03LSA 1956 1951

I03LSB 1959 1953 1955 1957

I03LSX 1950 1940

I03M 2145 2143

IO3N10 2188 2186

I03N2 2150 2148

I03N3 2154 2152

I03N4 2158 2156

I03N5 2163 2161

I03N6 2168 2166

I03N7 2173 2171

I03N8 2178 2176

I03N9 2183 2181

1030 2190 2130

I03P 2193

103PT 1887 1437

1770

1857

1471

1806

1861

1492

1826

1865

1610 1614

1834 1843

1869 1873

1652 1666 1748

1847 1851 1854

1877 1881

I03XP 2199 2134

2172

2139

2177

2144

2182

2149 2153

2187 2189

2157 2162 2167

2192

I03XQ 2205 2200

149

Label NameDefined

On Referenced OnI03Y 2206 2034 2038

I03YA 2228 2217 2230

103YA1 2232 2127

I03YB 2229 2207

I03YC 2244

I03YC1 2252 2290 2298

I03YD 2257 2047 2231

I03YE 2264 2262

IO3YE0 2283 2277 2287

103YE 1 2284 2004 2293

I03YF 2292 2258

I03YFA 2299 2296

I03YG 2301

I03YH 2305

I03YI 2309

I03YJ 2312

I03YK 2315

I03YL 2319

I03YM 2323

I03YN 2327

I03Y0 2331

I03YP 2335

I03YQ 2339

I04A 2488 2348

I04A1 2349 2346

I04A2 2352 2350

I04A3 2385 2383

I04AA 2492 2490

I04B 2496 2494

I04BA 2504 2507

I04BB 2505 2503

I04C 2508 2497 2499

I04CA 2512 2501

I04D 2520 2509 2685

I04DA 2523 2521

I04E 2525 2511

I04F 2529 2527

I04FA 2553 2548

I04FB 2556 2552

I04G 2567 2713

I04GA 2571 2568

I04GB 2572 2570

I04H 2581 2522

I04HA 2585 2583

I04HB 2588 2586

1041 2592 2590 2655

150

Label NameDefined

On Referenced OnI04K 2597 2595

I04LF 2425 2758

2792

2762

2795

2766 2772 2776 2780 2784 2788

I04LF1 2431 2428

I04LFA 2438 2433

I04LFB 2441 2435 2437 2439

I04LFC 2455 2445 2449

I04LFD 2462 2458

I04LS 2390 2592

2635

2597

2640

2602

2645

2607 2615 2620 2625 2630

I04LSA 2413 2408

I04LSB 2416 2410 2412 2414

I04LSX 2407 2397

I04M 2602 2600

IO4N10 2645 2643

I04N2 2607 2605

I04N3 2611 2609

I04N4 2615 2613

I04N5 2620 2618

I04N6 2625 2623

I04N7 2630 2628

I04N8 2635

2640

2633

2638I04N9

1040 2647 2587

I04P 2650

I04PT 2344 1894

2227

2314

1928

2263

2318

1949

2283

2322

2067 2071

2291 2300

2326 2330

2109

2304

2334

2123

2308

2338

2205

2311

I04XP 2656 2591

2629

2596

2634

2601

2639

2606 2610

2644 2646

2614

2649

2619 2624

I04XQ 2662 2657

I04Y 2663 2491 2495

I04YA 2685 2674 2687

104YA1 2689 2584

104YB 2686 2664

I04YC 2701

104YC1 2709 2747 2755

I04YD 2714 2504 2688

104YE 2721 2719

IO4YE0 2740 2734 2744

104YE

1

2741 2461 2750

I04YF 2749 2715

104YFA 2756 2753

I04YG 2758

104YH 2762

I04YI 2766

151

Label NameDefined

On Referenced OnI04YJ 2769

I04YK 2772

I04YL 2776

104YM 2780

104YN 2784

I04Y0 2788

I04YP 2792

I04YQ 2795

IRS 4168

IRSA 4174

IRSB 4183 4179

IRSC 4186 4170 4172

IRSD 4188 4238

IRSE 4191 4184 4187

IRSF 4195 4192

IRSG 4211 4199

IRSH 4219 4210

IRSI 4220 4207 4216

IRSJ 4221 4197

IRSK 4226 4233 4244

IRSL 4228 4222

IRSM 4234 4229

IRSMA 4239 4235 4237

IRSN 4245 4201

IRSO 4271 4249

IRSP 4291 4294

IRSQ 4293 4247

LD1 1107 1360 1361 1364 1365 1366 1367 1368

LD2 1553 1817 1818 1821 1822 1823 1824 1825

LD3 2010 2274 2275 2278 2279 2280 2281 2282

LD4 2467 2731 2732 2735 2736 2737 2738 2739

PGMVRS 4316

PWRON 6

PWR0N1 58 30

RAMERR 31 19 34

RAMT 16 27

RAMTST 17 22

RBI 195 186 900

RBI1C 225 222

RBI1CA 228 226

RBI1D 232 230

RBI IDA 241 237

RBI IE 242 234

RBI1EA 252 247

RBI1G 264 245

152

Label NameDefined

On Referenced OnRBI1GA 271

RBI1GB 284 278

RBI1H 293 266 283

RBI1H1 294 263

RBI 1 HA 303 297

RBI1HB 307 302

RBI2B 313 223

RBI2C 316 314

RBI2CA 319 317

RBI2D 323 321

RBI2DA 332 328

RBI2E->-.-*

->j:> 325

RBI2EA 343 338

RBI2G 355 336

RBI2GA 362

RBI2GB 377 369

RBI2H 386 357 376

RBI2H1 387 354

RBI2HA 396 390

RBI2HB 400 395

RBI3B 406 315

RBI3C 409 407

RBI3CA 412 410

RBI3D 416 414

RBI3DA 425 421

RBI3E 426 418

RBI3EA 436 431

RBI3G 448 429

RBI3GA 455

RBI3GB 470 462

RBI3H 479 450 469

RBI3H1 480 447

RBI3HA 489 483

RBI3HB 493 488

RBI4B 499 408

RBI4C 502 500

RBI4CA 505 503

RBI4D 509 507

RBI4DA 518 514

RBI4E 519 511

RBI4EA 529 524

RBI4G 541 522

RBI4GA 548

RBI4GB 563 555

RBI4H 572 543 562

153

Label NameDefined

On Referenced OnRBI4H1 573 540

RBI4HA 582 576

RBI4HB 586 581

RBIA 198 196

RBIB 210 199

RBIBA 217 213

RBIJ 594 501

RBIJA 600 595

RBIK 610 602

RBIKA 616 634

RBIL 619 614

RBIM 625 636

RBIN 631 612

RBIO 635 632

RBIS 637 311 404 497 590

RBISA 651 647

RBISB 656 652

RBISC 661 657

RBISD 666 662

RBISE 671 667

RBISF 674 643

RBIT 683 599 638

RJBIU 677 645

ROMERR 53 48 50 56

ROMTSA 41 46

ROMTST 38 28

SERVF1 2840 2847

SERVF2 2844 2841

SERVF3 2846 2839

SERVG1 2850 2857

SERVG2 2854 2851

SERVG3 2856 2849

SERVH1 2860 2867

SERVH2 2864 2861

SERVH3 2866 2859

SERVI1 2870 2877

SERVO 2874 2871

SERVI3 2876 2869

SETUP 126

SETUP

1

127 58 188

SETUPS 152 141

SIF 3746 2886

SIF1

SIF2

3750

3752

3784

3779

SIF3 3758 3756

154

Label NameDefined

On Referenced OnSIF3A 3769 3766

SIF4 3770 3768

SIF5 3778 3759

SIF6 3780 3753

SIFA 3783 3747

SIFA1 3855 3853

SIFA 1

A

3836 3786

SIFA IB 3845 3841

SIFA1C 3842 3838

SIFA2 3862 3860

SIFB 3870 3868

SIFB1 3874 3872

SIFB2 3881 3879

SIFC 3889 3887

SIFC1 3893 3891

SIFC2 3900 3898

SIFD 3908 3906

SIFD1 3912 3910

SIFD2 3919 3917

SIFE 3927 3925

SIFE1 3931 3929

SIFE2 3938 3936

SIFF 3946 3944

SIFF1 3950 3948

SIFF2 3957 3955

SIFG 3965 3963

SIFG1 3969 3967

SIFG2 3976 3974

SIFH 3984 3982

SIFH1 3988 3986

SIFH2 3995 3993

SIFI 4003 4001

SIFI1 4007 4005

SIFI2 4014 4012

SIFJ 4041 4039

SIFJ1 4045 4043

SIFJ2 4052 4050

SIFK 4060 4058

SIFK1 4064 4062

SIFK2 4071 4069

SIFL 4079 4077

SIFL1 4083 4081

SIFL2 4090 4088

SIFM 4098 4096

SIFM1 4101

155

Label NameDefined

On Referenced OnSIFM2 4108 4106

SIFN 4115

SIFN1 4118

SIFN2 4125 4123

SIFO 4132

SIFOl 4135

SIF02 4142 4140

SIFP 4150 3833 3873 3892 3911 3930 3949 3968 3987

4006 4025 4044 4063 4082 4100 4117 4134

4162

SIFQ 4160 3829 3869 3888 3907 3926 3945 3964 3983

4002 4021 4040 4059 4078 4097 4114 4131

4148

SIFR 3788 3796

SIFR1 3790

SIFRA 3792 3789

SIFRB 3813 3851

SIFRC 3814 3832

SIFRD 3821 3819

SIFRE 3830 3827

SIFX 4022 4020

SIFX1 4026 4024

SIFX2 4033 4031

SOF 2883 2833

SOF1 2886 2884

SOF2 2888 2907

SOF3 2890 2902

SOF4 2901 2895

SOF5 2903 2891

SOFA 2906 2885

SOFAA 2914 979 2911

SOFB 2925 2923

SOFB1 3048 3045

SOFB2 3053 3050

SOFB3 3057 3054

SOFB4 3062 3059

SOFB5 3066 3063

SOFB6 3070 3068

SOFBA 2931 2928

SOFBB 2936 2933

SOFBC 2940 2937

SOFBD 2945 2942

SOFBE 2949 2946

SOFBF 2954 2951

SOFBG 2958 2955

156

Label NameDefined

On Referenced OnSOFBH 2963 2960

SOFBI 2967 2964

SOFBJ 2972 2969

SOFBK 2976 2973

SOFBL 2981 2978

SOFBM 2985 2982

SOFBN 2990 2987

SOFBO 2994 2991

SOFBP 2999 2996

SOFBQ 3003 3000

SOFBR 3008 3005

SOFBS 3012 3009

SOFBT 3017 3014

SOFBU 3021 3018

SOFBV 3026 3023

SOFBW 3030 3027

SOFBX 3035 3032

SOFBY 3039 3036

SOFBZ 3044 3041

SOFC 3072 3612

SOFCA 3075 3073

SOFCB 3082 3076

SOFCC 3090 3088

SOFCD 3096 3081 3092

SOFD 3101 3099

SOFDA 3105 3103

SOFDB 3112 3106

SOFDC 3120 3118

SOFDD 3126 3111 3122

SOFE 3131 3129

SOFEA 3135 3133

SOFEB 3142 3136

SOFEC 3150 3148

SOFED 3156 3141 3152

SOFF 3161 3159

SOFFA 3165 3163

SOFFB 3172 3166

SOFFC 3180 3178

SOFFD 3186 3171 3182

SOFG 3191 3189

SOFGA 3195 3193

SOFGB 3202 3196

SOFGC 3210 3208

SOFGD 3216 3201 3212

SOFH 3221 3219

157

Label NameDefined

On Referenced OnSOFHA 3225 3223

SOFHB 3232 3226

SOFHC 3240 3238

SOFHD 3246 3231 3242

SOFI 3251 3249

SOFIA 3255 3253

SOFIB 3262 3256

SOFIC 3270 3268

SOFID 3276 3261 3272

SOFJ 3281 3279

SOFJA 3285 3283

SOFJB 3292 3286

SOFJC 3300 3298

SOFJ-

» 3306 3291 3302

SOF 3311 3309

SOFkA 3315 3313

SOFKB 3322 3316

SOFKC 3330 3328

SOFKD *> i ** ^ all jjj>z

SOFL 3341^ ~* "* d

SOFLA 3345 3343

SOFLB 3352 3346

SOFLC 3360 3358

SOFLD 3366 3351 3362

SOFM 3371 3369

SOFMA 3375 3373

SOFMB 3382 3376

SOFMC 3390 3388

SOFMD 3396 3381 3392

SOFN 3401 3399

SOFNA 3405 3403

SOFNB 3412 3406

SOFNC 3420 3418

SOFND 3426 3411 3422

SOFO 3431 3429

SOFOA 3435 3433

SOFOB 3442 3436

SOFOC 3450 3448

SOFOD 3456 3441 3452

SOFP 3461 3459

SOFPA 3465 3463

SOFPB 3472 3466

SOFPC 3480 3478

SOFPD 3486 3471 3482

SOFQ 3491 3489

158

Label NameDefined

On Referenced OnSOFQA 3495 3493

SOFQB 3502 3496

SOFQC 3510 3508

SOFQD 3516 3501 3512

SOFR 3520

SOFRA 3524 3522

SOFRB 3531 3525

SOFRC 3539 3537

SOFRD 3545 3530 3541

SOFS 3550 3074 3104 3134 3164 3194 3224 3254 3284

3314 3344 3374 3404 3434 3464 3494 3523

3600

SOFT 3564 3100 3130 3160 3190 3220 3250 3280 3310

3340 3370 3400 3430 3460 3490 3519 3548

SOFTA 3566 3597 3619 3626 3634 3642 3650 3658 3666

3674 3682 3690 3698 3706 3714 3722 3730

3738

SOFTB 3592 3565

SOFU 3598 3591 3593

SOFY 3601 2924

SOFYA 3613 3603

SOFYA

1

3617 3615

SOFYB 3620

SOFYB1 3624 3621

SOFYC 3627

SOFYC1 3631 3628

SOFYD 3635 j6jj

SOFYD1 3639 3636

SOFYE 3643 3641

SOFYE1 3647 3644

SOFYF 3651 3649

SOFYF1 3655 3652

SOFYG 3659 3657

SOFYG1 3663 3660

SOFYH 3667 3665

SOFYH1 3671 3668

SOFYI 3675 3673

SOFYI1 3679 3676

SOFYJ 3683 3681

SOFYJ1 3687 3684

SOFYK 3691 3689

SOFYK1 3695 3692

SOFYL 3699 3697

SOFYL1 3703 3700

SOFYM 3707 3705

159

Label NameDefined

On Referenced OnSOFYM1 3711 3708

SOFYN 3715 3713

SOFYN1 3719 3716

SOFYO 3723 3721

SOFYOl 3727 3724

SOFYP 3731 3729

SOFYP1 3735 3732

SOFYQ 3739 3737

SOFYXX 3612 3605 3609

STUFA 4301 4304

STUFF 4299 279 370 463 556

TBI 692 197 227 231 251 318 322 342 411

415 435 504 508 528 617 630

TBI1 698 693

TBI1BA 741 738

TBI IE 748 742

TBI1EA 752 747

TBI IF 768 766

TBI2 703 697

TBI2B 773 735

TBI2BA 779 777

TBI2E 786 780

TBI2EA 790 785

TBI2F 806 804

TBI3 705 699

TBI3B 811 774

TBI3BA 817 815

TBI3E 824 818

TBI3EA 828 823

TBI3F 844 842

TBI4 710 706

TBI4B 849 812

TBI4BA 855 853

TBI4E 862 856

TBI4EA 866 861

TB14F 882 880

TBIA 713 711

TBIB 721 714

TBIBA 730 728

TBIG 887 730 850

TBIG1 897 899

TBIGA 901 888

TBIGB 908 910

TBIGC 912 905

TBIH 914 918

160

Label NameDefined

On Referenced OnTBIHA 921 942

TBIHB 925 911

TBIHC 928 926

TBIJ 933 902

TBIK 935 939

TBIN 943 771 809 847 885

TBIO 944

TBIQ 949

TBIQ1 952

TBIR 962 958

TBIRA 964 959 961

TBIRB 977 970

TBIS 979 951 963

TDMA 156 64 172 183 3748 3777 3781 3791 3808

3844 3854 4159

TDMA1 185 159

TDMAA 170 167

TDMAB 171 169

TDMAI 174 161

TIBA 731 725

TSTR ^M 28 24

161

162

APPENDIX F

A. PHOTOS

ft9.

TD-1271B/U Front Panel

TD-1271B/U Card Cage

163

DBP Processor Card

164

INITIAL DISTRIBUTION LIST

1. Defense Technical Information Center 2

8725 John J. Kingman RD., Ste 0944

Fort Belvoir, VA 22060-6218

2. Dudley Knox Library 2

Naval Postgraduate School

411 Dyer Road

Monterey, CA 93943-5150

3. Center for Naval Analysis 1

4401 Ford Ave.

Alexandria, VA 22302-0268

4. Chief of Naval Research 1

800 North Quincy St.

Arlington, VA 22217'c'

5. Dr. Dan Boger, Chairman, Code CS 1

Computer Science Dept.

Naval Postgraduate School

Monterey, CA 93943-5100

6. Dr. Man-Tak Shing, Code CS/SH 1

Computer Science Dept.

Naval Postgraduate School

Monterey, CA 93943-5100

7. Kathleen M. Nelson 1

SPAWAR SYSCEN SAN DIEGOD844

San Diego, CA 92152-5150-t v

8. Laurence Nixon 1

SPAWAR SYSCEN SAN DIEGOD832

San Diego, CA 92152-5150

9. Joe Hirschfelder 1

SPAWAR SYSCEN SANDIEGOD874

San Diego, CA 92152-5150

165

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