- 1 - Embedded systems: processing Embedded System Hardware Embedded system hardware is frequently used in a loop („hardware in a loop“): actuators

- 1 -Embedded systems: processing

Embedded System Hardware

Embedded system hardware is frequently used in a loop(„hardware in a loop“):


actuators


Summary: Information processing

1. ASICs

2. Processors• Energy efficient• Code-size efficient• Run-time efficient

• Special features of DSP processors• Multimedia instructions• Very long instruction word machines

3. Reconfigurable hardware

4. Memory

1. ASICs

2. Processors• Energy efficient• Code-size efficient• Run-time efficient

• Special features of DSP processors• Multimedia instructions• Very long instruction word machines

3. Reconfigurable hardware

4. Memory


Reconfigurable Logic

Full custom chips may be too expensive,

software may be too slow.

Use of configurable hardware;most common form: field programmable gate arrays (FPGAs)

Considered e.g. for configuring mobile phone according to local standards;

Fast “object recognition”.

Example: Xilinx Virtex II FPGAs, Altera Stratix

Full custom chips may be too expensive,

software may be too slow.

Use of configurable hardware;most common form: field programmable gate arrays (FPGAs)

Considered e.g. for configuring mobile phone according to local standards;

Fast “object recognition”.

Example: Xilinx Virtex II FPGAs, Altera Stratix


Floor-plan of VIRTEX II FPGAs


Virtex II Configurable Logic Block (CLB)


Virtex II Pro Devices includeup to 4 PowerPC processor cores

[© and source: Xilinx Inc.: Virtex-II Pro™ Platform FPGAs: Functional Description, Sept. 2002, //www.xilinx.com]


Memory

For the memory, efficiency is again a concern:• fast (latency and throughput); predictable timing• energy efficiency• size• cost• other attributes (volatile vs. persistent, etc)

For the memory, efficiency is again a concern:• fast (latency and throughput); predictable timing• energy efficiency• size• cost• other attributes (volatile vs. persistent, etc)


Access-times will be a problem

Speed gap between processor and main DRAM increasesSpeed gap between processor and main DRAM increases

2

4

8

2 4 5

Speed

years

CPU

(1.5

-2 p

.a.)

DRAM (1.07 p.a.)

31

• early 60ties (Atlas):page fault ~ 2500 instructions

• 2002 (2 GHz µP):access to DRAM ~ 500 instructions

penalty for cache miss soon same as for page fault in Atlas

• early 60ties (Atlas):page fault ~ 2500 instructions

• 2002 (2 GHz µP):access to DRAM ~ 500 instructions

penalty for cache miss soon same as for page fault in Atlas

[P. Machanik: Approaches to Addressing the Memory Wall, TR Nov. 2002, U. Brisbane]

2x every 2 years

10


Access times and energy consumption increases with the size of the memory

Example (CACTI Model): "Currently, the size of some applications is doubling every 10 months" [STMicroelectronics, Medea+ Workshop, Stuttgart, Nov. 2003]


How much of the energy consumption of a system is memory-related?

Mobile PCThermal Design (TDP) System Power

Note: Based on Actual Measurements

600/500 MHz uP37%

LCD 10"19%

HDD9%

Memory+Graphics12%

Power Supply10%

Other13%

Mobile PCAverage System Power

600/500 MHz uP13%

LCD 10"30%

HDD19%

Memory+Graphics15%

Power Supply10%

Other13%

CPU Dominates Thermal Design Power

Multiple Platform Components Comprise

Average Power [Courtesy: N. Dutt; Source: V. Tiwari]


CPU Power Dissipation

Power PC

Clock19%

Control L.16%

Cache23%

Data Flow11%

I/O 7%

PLA5%

ROM2%

TLB17%

Strong ARM

Icache26%

Dcache16%

Clock10%

IMMU9%

EBOX8%

DMMU8%

Others5%

Ibox18%

IEEE Journal of SSC Nov. 96

Proceedings of ISSCC 94Based on slide by and ©: Osman S. Unsal, Israel Koren, C. Mani Krishna, Csaba Andras Moritz, University of Massachusetts, Amherst, 2001

42%/40% again memory-related !


Predictability is a problem

• Embedded system systems are often real-time systems:– Have to guarantee meeting timing constraints.

• Predictability: For satisfying timing constraints in hard real-time systems, predictability is the most important concern;pre run-time scheduling is often the only practical means of providing predictability in a complex system [Xu, Parnas] Time-triggered, statically scheduled operating systems

• What about memory accesses? – Currently available caches don‘t solve the problem:

• Improve the average case behavior• Use “non-deterministic” cache replacement algorithms

Scratch-pad/tightly coupled memory based predictability

• Embedded system systems are often real-time systems:– Have to guarantee meeting timing constraints.

• Predictability: For satisfying timing constraints in hard real-time systems, predictability is the most important concern;pre run-time scheduling is often the only practical means of providing predictability in a complex system [Xu, Parnas] Time-triggered, statically scheduled operating systems

• What about memory accesses? – Currently available caches don‘t solve the problem:

• Improve the average case behavior• Use “non-deterministic” cache replacement algorithms

Scratch-pad/tightly coupled memory based predictability


Hierarchical memoriesusing scratch pad memorys (SPM)

Address spaceAddress space ARM7TDMI cores, well-known for low power consumption

scratch pad memory

0

FFF..

main

SPM

processor

HierarchyHierarchy

ExampleExample

no tag memory


Scratchpad vs. main memory currents

Current32 Bit-Load Instruction (Thumb)

48,2 50,9 44,4 53,1

11677,2 82,2

1,16

0

50

100

150

200

Prog Off-Chip/Data Off-Chip

Prog Off-Chip/Data On-Chip

Prog On-Chip/Data Off-Chip

Prog On-Chip/Data On-Chip

mA

Core+On-Chip-Memory Current (mA) Off-Chip-Memory Current (mA)

Example: Atmel ARM-Evaluation board

Processor

SPM (On-chip)

Main

Memory

(on board)

current reduction:

/ 3.02

current reduction:

/ 3.02


Why not just use a cache ?

[P. Marwedel et al., ASPDAC, 2004]

1. Predictability?Worst case execution time

(WCET) may be large


Why not just use a cache ? (2)

0

1

2

3

4

5

6

7

8

9

256 512 1024 2048 4096 8192 16384

memory size

En

erg

y p

er

ac

ce

ss

[n

J]

.

Scratch pad

Cache, 2way, 4GB space

Cache, 2way, 16 MB space

Cache, 2way, 1 MB space

[R. Banakar, S. Steinke, B.-S. Lee, 2001]

2. Energy for parallel access of sets, in comparators, muxes.





actuators


Digital-to-Analog (D/A) Converters

Various types, can be quite simple, e.g.:


3

0

3

0123

2

842

i

ii

ref

refrefrefref

xR

VR

Vx

R

Vx

R

Vx

R

VxI

0'1 IRV

'II

01 IRV

3

0

131 )(8

2i

refi

iref xnatR

RVx

R

RVV

Due to Kirchhoff‘s laws:

Due to Kirchhoff‘s laws:

Current into Op-Amp=0:

Hence:

Finally:

Output voltage no. represented by x


Possible to reconstruct analog value from digitized value?

According to Nyquist theorem:• Analog input to sample-and-hold can be precisely

reconstructed from its output, provided that sampling proceeds at double of the highest frequency found in the input voltage and provided voltages remain analog.

• Digitizing values in the A/D generates additional uncertainty preventing precise reconstruction of initial values. Can be modeled as additional noise.

According to Nyquist theorem:• Analog input to sample-and-hold can be precisely

reconstructed from its output, provided that sampling proceeds at double of the highest frequency found in the input voltage and provided voltages remain analog.

• Digitizing values in the A/D generates additional uncertainty preventing precise reconstruction of initial values. Can be modeled as additional noise.

S/H A/D-converter D/A-converter

= ?

Inter-polate





actuators


Actuators and output

Huge variety of actuators and output devices, impossible to present all of them.Microsystems motors as examples (© MCNC):

(© MCNC)


Actuators and output (2)

Courtesy and ©:E. Obermeier, MAT,

TU Berlin

Documents

- 1 - Embedded systems: processing Embedded System Hardware Embedded system hardware is frequently used in a loop („hardware in a loop“): actuators