-1-VLSI CAD Laboratory, UC San Diego

Post-Routing BEOL Layout Optimization for Improved Time-Dependent Dielectric Breakdown (TDDB) Reliability

Post-Routing BEOL Layout Optimization for Improved Time-Dependent Dielectric Breakdown (TDDB) Reliability

Tuck-Boon Chan and Andrew B. Kahng

VLSI CAD LABORATORY, UC San Diego

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OutlineOutline

TDDB Reliability Our work: reducing TDDB Margin

–Signal-aware TDDB Analysis–Post-routing Layout Optimization

Experimental Results and Conclusions

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MotivationMotivation Time-dependent dielectric breakdown (TDDB)

– A dielectric forms a conductive path between the interconnects due to electrical stress chip functional error!

Breakdown time, tf α exp (-γEm) [Zhao11]

Electric field (E) across dielectric is increasing [ITRS2011]

E increases linearly tf reduces, TDDB risk

TDDB reliability limits (1) wire density and/or (2) max. voltage

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Via-to-Wire Spacing is CriticalVia-to-Wire Spacing is Critical Dielectric btw. via and wire is most susceptible to TDDB Small spacing is further reduced by mask misalignment

between via and wire Smaller spacing higher electric field shorter lifetime

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Our Work (1)Our Work (1) A chip-level TDDB reliability model

– Enable signal-aware TDDB analysis

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TDDB ModelTDDB Model Dielectric breakdown time is modeled as a Weibull

distribution [Bashir10]

Weibull shape factor

Characteristic lifetime

SpacingSupply voltage

Fij(t) = 1 – ( exp(-t/nij )β )

nij = A exp(-γ(V/Sij)m )

Failure probability

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Chip Level TDDB ReliabilityChip Level TDDB Reliability Apply Poisson area-scaling law to estimate chip failure rate

Sij

Lijviai

wirej

[Bashir10]Fchip(t) = 1 – ( exp(-t H-1 G)β )

G = Σij [ exp(-t γ(V/Sij)m) (Lij)1/β

]Stress factor: probability of interconnects being stressed

αij

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Signal-Aware AnalysisSignal-Aware Analysis Typical TDDB analysis assumes interconnects are under “DC

stress” too pessimistic! Obtain stress factors by running cycle-accurate logic

simulation too slow Proposed method: Use state probability from vector-less

logic simulation much faster

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Our Work (2) Our Work (2) Post-route layout optimization

– Shift wire edges around vias to increase via-to-wire spacing

– Negligible effect on circuit timing Does not require additional design iterations Applicable at post-route or mask writing

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Post-Routing Layout OptimizationPost-Routing Layout Optimization

Original Layout

Design Netlists

State probability

Layout optimization

Modified layout

Signal-aware analysis (optional)

Inputs

TDDB analysis and layout optimization flow

Calculate TDDB

reliabilityOriginal layout

+ Marker layers

Alternative layout implementation

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Defining Segments for PerturbationDefining Segments for Perturbation

via

wire

TDDB critical region

Shift this edge to increase spacing

Shift this edge to preserve wire width

Define movable edges for layout optimization

Overlappedregion

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Shifting Wire EdgesShifting Wire Edges Shift wire edge to increase via-to-wire spacing

Shifting is not applied if it violates via enclosure rule

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Experiment SetupExperiment Setup 4 Benchmark circuits Synopsys 32nm library 160nm metal pitch Analyze TDDB on M2, M3 & M4

Layout Parameters Values TDDB Model Parameters

Values

Min. wire spacing 80nm β 1.0

Min. wire width 80nm ɣ 49 (nm/V)0.5

Min. via-to-wire spacing 80nm m 0.5

Via width 70nm V 1.0V

Via-to-wire spacing variation

5nm H 1.6 х 1019

snm

Max. wire edge shift 4nm (5%)

Wire segment width 95nm

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Layout Optimization ResultsLayout Optimization Results

Layout optimization ~110% lifetime

Signal-aware analysis ~200% lifetime

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Timing Impact of Layout OptimizationTiming Impact of Layout Optimization

Total nets

Opt. nets

Δ Res. (Ω)

Δ Cap. (fF)

Gate-wost Δ Delay (ps)

Wire-worst Δ Delay (ps)

Max. Max. Max. Avg. Max. Avg.

AES 14k 8.0k 0.088 0.046 0.793 0.017 0.969 0.018

JPEG 29k 9.4k 0.143 0.083 0.615 0.007 0.600 0.007

MPEG2 10k 3.4k 0.144 0.056 1.578 0.012 1.580 0.012

SPARC_ECU 15k 7.0k 0.246 0.076 0.649 0.011 1.090 0.011

Average 17k 7k 0.155 0.065 0.909 0.012 1.060 0.012

40% of nets are modified ΔR per net < 0.3 Ω, ΔC per net < 0.1 fF, Average gate-worst Δdelay = 0.012ps,

– Add total ΔC at driver’s output pin Average wire-worst Δdelay = 0.012ps

– Add total ΔC at receivers’ input pin– Add total ΔR at driver’s output pin

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ConclusionsConclusions TDDB is a reliability issue for BEOL

– Limits pitch scaling and/or supply voltage Signal-aware TDDB analysis 2X chip lifetime Post-routing layout optimization +10% chip

lifetime with negligible impact on timing

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Thank you!

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ReferencesReferences [Achanta06] R. S. Achanta, J. L. Plawsky and W. N. Gill, "A Time Dependent Dielectric

Breakdown Model for Field Accelerated Low-k Breakdown Due To Copper Ions”, AIP Applied Physics Letters 91 (23) 2006, pp. 234106-1 - 234106-3.

[Bashir10] M. Bashir and L. Milor, “Towards a Chip Level Reliability Simulator for Copper/Low-k Backend Processes”, IEEE Design Automation and Test in Europe, 2010, pp. 279-282.

[Berman81] A. Berman, “Time-Zero Dielectric Reliability Test By a Ramp Method”, IEEE Intl. Reliability Physics Symposium, 1981, p. 204.

[Chen06] F. Chen, O. Bravo, K. Chanda, P. McLaughlin, T. Sullivam, J. Goill, J. Lloyd, F. Kontra and J. Aitken, “Comprehensive Study of Low-k SiCOH TDDB Phenomena and Its Reliability Lifetime Model Development”, IEEE Intl. Reliability Physics Symposium, 2006, p. 46.

[Lee88] J. Lee, I. C. Chen, and C. Hu, “Modeling and Characterization of Gate Oxide Reliability”, IEEE Intl. Reliability Physics Symposium, 1988, p. 2268-2278.

[Lloyd05] J. R. Lloyd, E. Liniger, and T. M. Shaw, “Simple model for time-dependent dielectric breakdown in inter- and intralevel low-k dielectrics”, AIP Journal of Applied Physics 98, (084109) (2005), 084109-1 – 084109-6.

[Zhao11] L. Zhao, Z. Tőkei, K. Croes, C. J. Wilson, M. Baklanov, G. P. Beyer, and C. Claeys, “Direct Observation of the 1/E Dependence of Time-Dependent Dielectric Breakdown in the Presence of Copper”, AIP Applied Physics Letters 98 (03) (2011), pp. 032107-1 - 032107-3.