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11b MSFFPage 1
ECEn 224 © 2003-2008BYU
MSFF
Master/Slave Flip Flops
11b MSFFPage 2
ECEn 224 © 2003-2008BYU
A Master/Slave Flip Flop (D Type)
Gated D latch (master) Gated D latch (slave)
D Q
Gate
D Q
Gate
D
GATE
QQ1
Either: The master is loading (the master in on)or The slave is loading (the slave is on)
But never both at the same time…
11b MSFFPage 3
ECEn 224 © 2003-2008BYU
DFF Timing
Gate
D
Q1
Q
MasterLoads
MasterLoads
MasterLoads
SlaveLoads
SlaveLoads
SlaveLoads
time
D Q
Gate
D Q
Gate
D
GATE
QQ1
11b MSFFPage 4
ECEn 224 © 2003-2008BYU
Output Changes in Response to Falling Clock
Gate
D
Q1
Q
MasterLoads
MasterLoads
MasterLoads
SlaveLoads
SlaveLoads
SlaveLoads
time
D Q
Gate
D Q
Gate
D
GATE
QQ1
11b MSFFPage 5
ECEn 224 © 2003-2008BYU
DFF Detailed Schematic
D
CLK
Q
Q’
Master latch (D) Slave latch (SR)
Usually call the gate “clock”
11b MSFFPage 6
ECEn 224 © 2003-2008BYU
A Falling Edge Triggered DFF
D
CLK
Q
Q’
CLK
D Q
Edge-triggered
Falling edge triggered
11b MSFFPage 7
ECEn 224 © 2003-2008BYU
Oscillator (Toggle Circuit) Operation
Q
CLK
CLK
time
QD D Q
11b MSFFPage 8
ECEn 224 © 2003-2008BYU
Rising Edge Triggered DFF Schematic
D
CLK
Q
Q’
D Q
CLK
Edge-triggered
Rising edge triggered
11b MSFFPage 9
ECEn 224 © 2003-2008BYU
Oscillator (Toggle Circuit) Operation
Q
CLK
time
CLK
QD D Q
11b MSFFPage 10
ECEn 224 © 2003-2008BYU
D Flip Flop Transition Table
D Q Q+
0 0 00 1 01 0 11 1 1
Q+ = D
No clock shown since it is edge triggered (assumed)
11b MSFFPage 11
ECEn 224 © 2003-2008BYU
Falling vs. Rising Edge Triggered
D Q D QD
CLK
Qfall
CLK
Qrise
CLK
D
Qrise
Qfall
11b MSFFPage 12
ECEn 224 © 2003-2008BYU
Alternative Flip Flops
TJK
11b MSFFPage 13
ECEn 224 © 2003-2008BYU
Toggle Flip Flop
T Q Q+
0 0 00 1 11 0 11 1 0
NoAction
Toggle
T Q
CLK
QT
Q+ = T’•Q + T•Q’ = T
+ Q
Clock edge is assumed in this transition table…
11b MSFFPage 14
ECEn 224 © 2003-2008BYU
Toggle Flip Flop
T Q Q+
0 0 00 1 11 0 11 1 0
NoAction
Toggle
T Q
CLK
QT
Q+ = T’•Q + T•Q’ = T
+ Q
D QT
Q
CLK
An oscillator with an enableinput (T)
11b MSFFPage 15
ECEn 224 © 2003-2008BYU
Toggle Flip Flop
QT
CLK
11b MSFFPage 16
ECEn 224 © 2003-2008BYU
JK Flip Flop
J K Q Q+
0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0
No Change
Reset
Set
Toggle
J QK
CLK
QJK
Q+ = K’•Q + J•Q’Kind of a cross betweena SR FF and a T FF
11b MSFFPage 17
ECEn 224 © 2003-2008BYU
JK Flip Flop
Q
J
CLK
K
11b MSFFPage 18
ECEn 224 © 2003-2008BYU
Why Alternative FF’s?
• With discrete parts (TTL family)– JK or T FF’s could reduce gate count
for the input forming logic – Extensively used
• With VLSI IC’s and FPGA’s– JK or T FF’s must be built from
DFF+gates– Larger, slower than a DFF– Not used
11b MSFFPage 19
ECEn 224 © 2003-2008BYU
Flip Flops With Additional Control Inputs
11b MSFFPage 20
ECEn 224 © 2003-2008BYU
D
CLK
Q
Q’
What is this?
???
11b MSFFPage 21
ECEn 224 © 2003-2008BYU
CLK
What is this?
Enable
A falling edge triggered, D-type FF with enable
Master only loads when CLK = Enable = 1
D
Q
Q’
11b MSFFPage 22
ECEn 224 © 2003-2008BYU
CLK
What is this?
???
D
Q
Q’
11b MSFFPage 23
ECEn 224 © 2003-2008BYU
CLK
What is this?
Set
A falling edge triggered, D-type FF with an asynchronous set
If Set=1 then Q→1, regardless of CLK or D
D
Q
Q’
11b MSFFPage 24
ECEn 224 © 2003-2008BYU
CLK
What is this?
???
D
Q
Q’
11b MSFFPage 25
ECEn 224 © 2003-2008BYU
CLK
What is this?
A falling edge triggered, D-type FF with a synchronous set
If Set=1 then Q→1 on the next falling edge of the clock, regardless of D
Set
D
Q
Q’
11b MSFFPage 26
ECEn 224 © 2003-2008BYU
Flip Flops With Additional Control Inputs
• A variety of FF’s have been made over the years
• They contain combinations of these inputs:– Enable/load– Set– Reset/clear
• The Set and Reset can be either:– Asynchronous (independent of CLK)– Synchronous (work only on CLK edge)
11b MSFFPage 27
ECEn 224 © 2003-2008BYU
Flip Flop Timing Characteristics
11b MSFFPage 28
ECEn 224 © 2003-2008BYU
Clock-to-Q Time (tCLK Q)
CLKtCLK Q = tNOT + tAND + 2 x tNOR
The output does not change instantaneously…
D
Q
Q’
11b MSFFPage 29
ECEn 224 © 2003-2008BYU
tCLK Q
CLK
D
Q
tCLK Q
time
11b MSFFPage 30
ECEn 224 © 2003-2008BYU
Setup Time (tsetup)
D
CLK
Q
Q’
tsetup = tNOT + tAND + 2 x tNOR
The input has to get there early enoughto set the master latch before
the clock turns off…
11b MSFFPage 31
ECEn 224 © 2003-2008BYU
tsetup
CLK
D
Q
tsetup
time
11b MSFFPage 32
ECEn 224 © 2003-2008BYU
Setup Time (tsetup)
D
CLK
Q
Q’
Same setup time as before
11b MSFFPage 33
ECEn 224 © 2003-2008BYU
Setup Time (tsetup)
D
CLK
Q
Q’
Clock is delayed through the NOT gate
11b MSFFPage 34
ECEn 224 © 2003-2008BYU
CLK
Q
Time
CLKinv
D
tsetup-old
tnot
Rising Edge FF Setup Time (tSETUP)
Falling-edge setup time
11b MSFFPage 35
ECEn 224 © 2003-2008BYU
CLK
Q
Time
CLKinv
D
tsetup-old
tnottsetup
Rising Edge FF Setup Time (tSETUP)
11b MSFFPage 36
ECEn 224 © 2003-2008BYU
Falling Edge Hold Time (thold)
D
CLK
Q
Q’
thold = 0ns (AND gates turn off immediately)
You have to keep the old D value there until the ANDgates are shut off… (but no longer)
11b MSFFPage 37
ECEn 224 © 2003-2008BYU
Rising Edge Hold Time (thold)
D
CLK
Q
Q’
thold = tNOT
You have to keep the old D value there until the ANDgates are shut off…
11b MSFFPage 38
ECEn 224 © 2003-2008BYU
Rising Edge Hold Time (thold)
CLK
D
Q
thold = tNOT
time
Clock edge AND gate turns off, D can now change
11b MSFFPage 39
ECEn 224 © 2003-2008BYU
Flip Flop Timing
CLK
D
Q
tsetup
thold
tCLK Q
time
11b MSFFPage 40
ECEn 224 © 2003-2008BYU
Timing of a Synchronous System
CLK
D Q
CLK
D QInputForming
Logic
InputForming
Logic
time
Q D
CLK
Q
D
tCLKQ tIFL tSETUP
tCYCLE >= tCLKQ +
tIFL + tSETUP
11b MSFFPage 41
ECEn 224 © 2003-2008BYU
D QD QD Q
Example of a Synchronous System
D Q+1
Circuit
4
CLK
4 4CNT = 0000
0001001000110100…11110000…One transition per clock edge…