TMS320C54x

7 TMS320C54x7. XCR2:

P.262,7-11977 TMS320C54x5. RCR2 :

6. XCR1: 967 TMS320C54x

1PLL1DMADMAXIO226I/OGPIO37 TMS320C54x7.4 DMADMACPU 7.4.1 DMA DMA440657 TMS320C54x7.5 (McBSP) multichannel buffered serial portsMcBSPC54xDSP7.5.1 McBSP128:877 TMS320C54x C54xI/O(General Purpose I/OGPI/O)

XF

BIO

7.1 I/O(GPIO)TMS320VC5402A67 TMS320C54x 1. XF XFST1D13(XF)XF

7.1.1 XFBIOBIO .7

7 TMS320C54x 7-1 XF SSBX XFLED RSBX XFLED

87 TMS320C54x7-2 BC1500h, TC, NC, BIO;TC=1C=0 BIOPC=1500h

97 TMS320C54x TMS320VC5402AGPIO8(HPI): HD0~HD718(McBSP): BCLKR0/1/2BCLKX0/1/2BDR0/1/2 BDX0/1/2BFSR0/1/2 BFSX0/1/27.1.2 GPIO107 TMS320C54x HPIHPI16(HPI16 = 1)HPI(HPIENA = 0)HPIHD0~HD7GPIO

I/O(GPIOCR)I/O(GPIOSR) 2. (HPI)GPIO137-3 HPIHD03 , HD47, HD03 AR3; HD47 0101b.GPIOCR .set 3Ch ;MMR GPIOCR address is 3ChGPIOSR .set 3Dh ;MMR GPIOSR address is 3Dh.textSTM #0F0h, GPIOCR ; HD0-3 ,HD4-7 . . .LDM GPIOSR, A ; GPIOSR.AND #0Fh, A ; Mask off MSBs.STLM A, AR3 ; Store value of HD0-3 in AR3.STM #050h, GPIOSR ; Set HD4-7 to 0101b.. . .16 C54x1~4 7.2 7.2.1

TCR17synchronized reset7 TMS320C54x

TIM(timer register)

PRD(period register)

PSC(Timer prescaler counter)

TDDR(Timer divide-down ratio) 187 TMS320C54x

TIMPRD0024h0025h

PSCTDDRTCRD9~D6D3~D019 TCR: 15~12 -0 11Soft0 10Free0Free=0Soft=0Free=0Soft=10Free=1Soft=XSoft SoftFreePSCTRBTSSTDDR21 9~6 PSC -PSCCPU clockPSC1PSC0PSCTDDRTIM1 5TRB-TRB=1PRDTIMTDDRPSCTRB0 4TSS-TSS=0TSS=1TSS0 3~0 TDDR0000PSC0TDDRPSC SoftFreePSCTRBTSSTDDR227 TMS320C54x2. SRESET (Synchronized reset)DSPTRB1312PRDTIMTDDRPSC23

DSP(TSS0)TSS05CPU clockPSC

7 TMS320C54x24PSC10TIMTIM12TDDRPSCPSC17 TMS320C54xTSS15CPU clockTIMPSCTIM10 1TINT25

7 TMS320C54x 1TINT 24TOUT 31PRDTIM TIMTIM0=CLKOUT(TDDR+1)(PRD+1) CLKOUTCPU26

7 TMS320C54x7.2.2

277 TMS320C54x 1. =1ms CLKOUT=1/80M=12.5nsTDDRPRD 12.5ns65536=819200ns=0.8192ms =CLKOUT(TDDR+1)(PRD+1) 1ms = 12.5(9+1) (PRD+1) =1106ns PRD=7999(10)=1F3FH28TDDR=97 TMS320C54x2.

1TCRTSS1

2PRD

3TDDRTRB1 TSS0SoftFreePSCTRBTSSTDDR2900000000000100007 TMS320C54xSoftFreePSCTRBTSSTDDRSTM#0010HTCRTSS=1

STM#1F3FHPRDPRD

STM#0E69HTCRTDDR=9TRB=1 TIMPSC TSS=0 15-1211109-6543-00000111001101001307 TMS320C54x3.INTM=1 (ST1D11)1IFRTINT1

2IMRTINT1

3INTM0317 TMS320C54x7.2.2 7-4XF2s50%CLKOUT=1/80M=12.5ns, =CLKOUT(TDDR+1)(PRD+1) 1ms =12.5(9+1)(PRD+1) =1106nsPRD=7999(10)=1F3FH100010001ms=1s3312.5ns6553616=13. 1072ms=1msTDDR=9;7.2.2 1 .file "timer.asm" .mmregs ;54X .global main ; main .def timer_iserv TIM0 .set 0x0024 ; 0PRD0 .set 0x0025 ; 00TCR0 .set 0x0026 ; 0TIM0_VAL .set 0x1F3F ; 01F3Fh ;; ;7999PRD0_VAL .set 0x1F3F ;1F3Fh (7999)TCR0_VAL .set 0x0E69 ; 0E69h0000 1110 0110 1001 ; free.soft=11b, PSC=1001b, TRB=1,TSS=0, TDDR=1001b349 TMS320C54x2) 16SWWSR(MMR)0028hSWWSR9.279.27SWWSR

35

9 TMS320C54x2) 64K32K8000-FFFF0000-7FFFI/O64K SWWSR38MXPA=1 400000-7FFFFF000000-3FFFFF369 TMS320C54x16SWCR(MMR)002BhSWCRSWSM1SWWSR214CLKOUT9.28SWCR

377.2.2 1;SWWSR .set 0x0028 ; software wait-state registerSWWSR_VAL .set 0x36DB ; (0011011011011011b)3SWCR .set 0x002B ; SWCR_VAL .set 0x0001 ; 32TINT0_ENBL .set 0x0008 ;TIMER0;CLKMD .set 0x0058 ;PLLMMRPLLX5 .set 0x43EF ;PLLCLKMD; 0100 0011 1110 111116MHz, 580MHz, PLLCOUNT=125347337348387.2.2 OVLY_1 .set 0x00A0 ;PMST: 0000 0000 1010 0000 IPTR OVLYstack_size .set 100 stack .usect ".stack" , stack_size sys_stack .set stack+stack_size .bss XF_FLAG, 1 .bss LED_DISP, 1 ; .text main: STM #sys_stack, SP ANDM #0fffeh, *(SP) ; (), *(SP)SP STM #OVLY_1, PMST ; OVLY=1, MP/MC=0, DROM=0 STM #SWWSR_VAL, SWWSR ; 407.2.2 * ; PLL339 STM #0CLKMDDIVDIV_Status LDM CLKMDB AND #01hB;PLLSTATUS BC DIV_StatusBNEQ ;B=0, DIV STM PLLX5CLKMD;PLL5PLL_Status LDM CLKMDB AND #01hB;PLLSTATUS BC PLL_StatusBEQ ;B04116MHz, 580MHzCLKOUT=1/80M=12.5ns7.2.2 * ; STM #TINT0_ENBL, IMR ; TINTTINT0_ENBL=0x08 STM #XF_FLAG, AR1 ; AR1XFXF_FLAG ST #0, *AR1 ; XF0 STM #03E8h, AR2 ; 100003E8h STM #PRD0_VAL, PRD ; 1F3Fh STM #TCR0_VAL, TCR ;9 TSS=0 RSBX INTM ;WAIT: BD WAIT NOP NOP NOP427.2.2 * ;timer_iserv: BANZ EXIT_ISERV, *AR2- ;100003E8h STM #03E8h, AR2 ; 100003E8h BITF *AR1, #1h ;XF_FLAGAR1 XF_FLAG BC XF_0, TC ;TC=1XF_FLAG1, XF_0 SSBX XF ;XF1 ST #01h, *AR1 ;XF_FLAG1 B EXIT_ISERV XF_0: RSBX XF ;XF0 ST #00h, *AR1 ;XF_FLAG0EXIT_ISERV: RETE .end 437.2.2 2 VECTORS.ASM .mmregs ;54X .ref main ; main .ref timer_iserv .sect ".vectors"IV_RESET: BD main ; nop nopIV_NMI: rete ;NMI nop nop nop SINT17: rete ;SINT17 nop nop nop447.2.2 SINT26: rete nop nop nopSINT27: rete nop nop nopSINT28: rete nop nop nopSINT29: rete nop nop nop2SINT18: rete nop nop nopSINT19: rete nop nop nop SINT20: rete nop nop nopSINT21: rete nop nop nopSINT22: rete nop nop nopSINT23: rete nop nop nopSINT24: rete nop nop nopSINT25: rete nop nop nop457.2.2 SINT30: rete nop nop nopINT0: rete nop nop nopINT1: rete nop nop nop INT2: rete nop nop nopTINT0: b timer_iserv nop nopBRINT0: rete nop nop nop BXINT0: rete nop nop nopDMAC0: rete nop nop nop467.2.2 TINT1: rete nop nop nop INT3: rete nop nop nopHPINT: rete nop nop nop BRINT1: rete nop nop nopBXINT1: rete nop nop nopDMAC4: rete nop nop nopDMAC5: rete nop nop nopRESERVED .space 8*16 .end 477.2.2 MEMORY { PAGE 0 : PROG: origin = 0x2400, length = 0x1b80 VECT: origin = 0x0080, length = 0x80 PAGE 1 : DARAM: origin = 0x0100, length = 0x1f80 STACK: origin = 0x2000, length = 0x400 }SECTIONS { .text : load = PROG page 0 .data : load = PROG page 0 .bss : load = DARAM page 1 .stack : load = STACK page 1 .vectors : >VECT page 0 }3 ucdos.CMD487 TMS320C54x7.3 HPIC54xHPIHost Port InterfaceDSPHPI816HPI HPI HPI2kRAM HPIDSPRAM(C542,545,548549)C54XXC5402497.3.1 HPI-8 8HPI-8HPICHPIDHPIAHPI

507 TMS320C54x2. HPI HPI

HPIA

HPID

16HPIC 517 TMS320C54x1.20PINHCNTL1HCNTL0 00HPC01HPIDHPIA10HPIA11HPIDHPIAHD0~HD7//HCNTL0HCNTL1 HPIHBIL((HBIL =0))HCS HDS1HDS2527 TMS320C54xHASHR/WHPI/HINT/HRDY/HPIHPIENAHPIHPI16(16HPI), HPI16C5402AHPI8/16HPI16 C5402HPI8HPI161.20PIN537 TMS320C54x1)HPIC88DSPHPIC88

2)DSPHINTHPIC

3)HPIC/DSPHPIC/ 54

HPIC

HPICC54xHPIC

C54xHPICHPI-8HPIC(C542,545,548549)

7 TMS320C54x55If SMOD = 1, shared-access mode (SAM) is enabledHPI memory can be accessed by the C54x DSP

HPIC

HPIC

C54xxHPIC

C54xxHPICC54XXHPI-8HPIC7 TMS320C54x This bit is only available on 54x devices with on-chip RAM mapped in extended addresses. This bit is not available on the 5410. X denotes bits that are unaffected by writes, or bits that can be read as either 1 or 0.56C54x/HPIC 7 TMS320C54x

This bit is only available on 54x devices with on-chip RAM mapped in extended addresses. This bit is not available on the 5410. X denotes bits that are unaffected by writes, or bits that can be read as either 1 or 0.

577 TMS320C54xHPIC BOB 0BOB=0BOB=1 DSPINT 0C54x1C54x HINT 0C54xHINT1HINTHINT0HINTC54x10 XHPIA XXHPIA=016XHPIA=1 HPIENA XHPIHPIENAC54x , 0HPI587.3.2 HPI-8 HPI-8HPI-8

597 TMS320C54x HPI-8HBILHCNTL0/1HR/W

607 TMS320C54x7.3.3 HPI-8HPI-8

HPI-8 HPI-8RAM 617 TMS320C54xHPI-8

HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).62HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).

HPI-8 63

HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).647 TMS320C54x DMA :0054hDMPREC0055hDMSA0056hDMSDI0057hDMSDN00hDMSRC0001hDMDST0066DMPRECDMA channel priority and enable control register7 TMS320C54x02hDMCTR0003hDMSFC0004hDMMCR0005hDMSRC1106hDMDST1107hDMCTR1108hDMSFC1109hDMMCR110AhDMSRC220BhDMDST22677 TMS320C54x0ChDMCTR220DhDMSFC220EhDMMCR220FhDMSRC3310hDMDST3311hDMCTR3312hDMSFC3313hDMMCR3314hDMSRC44687 TMS320C54x15hDMDST4416hDMCTR4417hDMSFC4418hDMMCR4419hDMSRC551AhDMDST551BhDMCTR551ChDMSFC551DhDMMCR551EhDMSRCP697 TMS320C54x1FhDMDSTP20hDMIDX0021hDMIDX1122hDMFRI0023hDMFRI1124hDMGSA25hDMGDA26hDMGCR27hDMGFR707 TMS320C54x1.DMPREC DMSADMSDIDMSDN 40 71

I40 7-6 DMA5DMSA .set 55h ;set register locationsDMSDI .set 56hDMSRC5 .set 19h ; DMDST5 .set 1AhDMCTR5 .set 1BhDMSFC5 .set 1ChDMMCR5 .set 1DhSTM DMSRC5, DMSA ;DMSRC5STM #1000h, DMSDI ;write 1000h to DMSRC5STM #2000h, DMSDI ;write 2000h to DMDST5STM #0010h, DMSDI ;write 10h to DMCTR5STM #0002h, DMSDI ;write 2h to DMSFC5STM #0000h, DMSDI ;write 0h to DMMCR5727 TMS320C54x2. DMPRECDMPREC0054h DMPRECDMA Channel Priority and Enable Control Register DMA(1)(2)(3)DMPREC

732. 15FREE0(1)DMA()13:8DPRC[5:0] DMA[5:0]15:0DE[5:0]DMA[5:0],1DMA7:6INTOSEL[1:0](C5402)

757 TMS320C54x3.

DMA516 DMSRCxDMDSTx16DMCTRx 767 TMS320C54xDMSFCxDMAMcBSP1DSYN[3:0]=0101DSYN[3:0]=01102552560DMADMGFR

DBLW=016bitDBLW=132bit77C54027-77 TMS320C54x

DMMCRxAUTOINIT=1,DMACPU0DINM1IMOD0IMODDMACTMOD=1(0)(1)CTMOD=0(0)(1))CTMOD:01ABUSINDDIND 79SINDDIND(1);(2)1;(3)1;

80DMSDMDI/O

(Table 310. DMA Transfer Mode Control (DMMCRn) Register Bit/Field Descriptions SPRU302.pdf)817 TMS320C54x4. DMA10 DMA DMSRCPDMDSTPDMIDX0-1DMFRI0-1DMGSADMGDADMGCRDMGFR 827 TMS320C54x7.4.2 DMA C54xDMA (multiframe mode)

ABU(autobuffering mode) CTMOD (DMMCRx.12) 837 TMS320C54xDMADMMCRx(DINMIMOD)CPUIMRINTMDMAABU7.4.3 DMA847 TMS320C54x DMA6 :INTOSEL1INTOSEL022DMAC0/58H9XX(10 (DMAC0))23TINT1/DMAC15CH101026BRINT1/DMAC268H1301 1027BXINT1/DMAC36CH1401 1028DMAC470H15XX29DMAC574H16XX867 TMS320C54x(AICs)A/DD/A81216202432A 8887 TMS320C54xMcBSPDMAMcBSP McBSP:897 TMS320C54xMcBSP 16(16)McBSP0McBSP1McBSP2---RBR[1,2]McBSP12---RSR[1,2]McBSP12---XSR[1,2]McBSP12002000400030-DRR2xMcBSP2002100410031-DRR1xMcBSP1002200420032-DXR2xMcBSP2002300430033-DXR1xMcBSP1917 TMS320C54x003800480034-SPSAxMcBSP003900490035-SPSDMcBSP0039004900350SPCR1xMcBSP10039004900351SPCR2xMcBSP20039004900352RCR1xMcBSP10039004900353RCR2xMcBSP20039004900354XCR1xMcBSP10039004900355XCR2xMcBSP2927 TMS320C54x0039004900356SRGR1xMcBSP10039004900357SRGR2xMcBSP20039004900358MCR1xMcBSP10039004900359MCR2xMcBSP2003900490035ARCERAxMcBSPA003900490035BRCERBxMcBSPB003900490035CXCERAxMcBSPA003900490035DXCERBxMcBSPB003900490035EPCRxMcBSP937 TMS320C54x1. McBSP7.5.3 McBSPRSRS=0McBSP, RS=1, GRST = FRST = RRST = XRST = 098SPCR1RRST0, SPCR2XRSTGRST0 7 TMS320C54x7.21 McBSP :P.51McBSPRSMcBSPRRST=0GRST=0XRST=0GRST=0DR--CLKR//CLKR--FSR//FSRP--997 TMS320C54xMcBSPMcBSPRSMcBSPRRST=0GRST=0XRST=0, GRST=0CLKS//--DX--CLKX//--CLKXFSX//--FSXPCLKS--1007 TMS320C54x 2. McBSP1RRST=XRST=FRST=0 27.21McBSP 32SPCR1SPCR21017 TMS320C54x4DXR5XRST=lRRST=16FRST=172exp06 2. McBSP1027 TMS320C54x3.

1037 TMS320C54xMcBSP

FSRFSXCLKRCLKX

1047 TMS320C54xSPCR1PCRRCR[12]XCR[12]012

1057 TMS320C54x4. McBSP/ McBSP RRDY(SPCR1.1)XRDY(SPCR2.1)/DMAREVTXEVTA-bisREVTAXEVTA/CPURINTXINT/ exp061067 TMS320C54x5.A A CCITTG.711

McBSP

1077 TMS320C54xA

DXR1XSR116(A)8 1087 TMS320C54xRBR18ADRR116RJUST

16CPUDMA 109McBSPDRR1DXR1XCOMPANDDXR1RCOMPANDMcBSPXCOMPANDRCOMPANDCPUDMA

1107 TMS320C54x7.5.4 TDMMcBSP/ 1117 TMS320C54xMcBSP128

80~716

A0246B1357 1127 TMS320C54xMcBSPR/XCR1R/XFRLEN1

1283232Al6B161137 TMS320C54xMCR1MCR2McBSP;

A/BRCER(A/B)XCER(A/B)32;1147 TMS320C54x1.MCR1

2. MCR2

1157 TMS320C54x 3.ARCERA

4.BRCERB

1167 TMS320C54x5.AXCERA

6.BXCERB

1177 TMS320C54x7.5.5 McBSP

1187 TMS320C54xMcBSPCLKGFSG

1207 TMS320C54xSRGR[1,2]3 SRGR1

SRGR2

1217 TMS320C54xPCRCLKXMSPCR1DLBPCRCLKRMPCRFSXMSRGR2FSGMDLBPCRFSRMSRGR2GSYNC 1227 TMS320C54x7.5.6 McBSPSPI SPI(Serial Peripheral interface)4 (MISO)Master InSlave Out(MOSI)(SCK): Shift-clock (SS): Slave-enable Signal1237 TMS320C54xSPI

SCKSS 1247 TMS320C54x1. McBSPMcBSPSPI (CLKX)SPI(SCK)(FSX)(SS)(CLKR)(FSR)CLKXFSX1257 TMS320C54x2. McBSPSPI SPCR1CLKSTP1Xb()PCRCLKXP01BCLKXPCRCLKXM01BCLKXRCR1RWDLEN1000~101bXWDLEN1XCR1XWDLEN1000~101bRWDLEN11267 TMS320C54xCLKSTP=10bCLKXP=0CLKSTP=10bCLKXP=1CLKSTPCLKXP4CLKSTP=11bCLKXP=0CLKSTP=11bCLKXP=11277 TMS320C54x3. McBSPSPI

McBSPSPISPI:1287 TMS320C54xMcBSPSPI CLKSTP = 10b /11b()PCRCLKXP = 0 / 1CLKXCLKX(CLKXP = 0)(CLKXP = 1)PCRCLKRP = 0 / 1CLKRCLKR(CLKRP = 0)(CLKRP = 1)PCRCLKXM = 1CLKX1297 TMS320C54xPCRFSXM = 1FSXSRGR2 FSGM=0DXR1XSR1FSXPCR FSXP = 1FSXSRGR2 CLKSM = 1(CLKG)CPUXDATDLY = 01b RDATDLY = 01bFSX1307 TMS320C54x4. McBSPSPIMcBSPSPISPI

1317 TMS320C54xMcBSPSPI CLKSTP = 10b /11b()CLKXP = 0 / 1CLKXCLKX(CLKXP = 0)(CLKXP = 1)CLKRP = 0 / 1CLKRCLKR(CLKRP = 0)(CLKRP = 1)CLKXM = 0CLKXSPI1327 TMS320C54xFSXM = 0FSXSPI()FSGM = 0DXR1XSR1FSXFSXP = 1FSXCLKSM = 1McBSPCPUCLKGDV=1CLKGCPUXDATDLY = 0b RDATDLY = 0bFSX1337.37.6, 7.9, 7.10134