第二章

•CPLD/FPGA 使用方法•AHDL 语言•AHDL 实验设计

可编程逻辑器件的选择• CPLD , FPGA or ASIC?

– 容量• 宏单元数，逻辑单元数• 寄存器数，门数• 存储器大小

– 速度• Tpd

– 可用管脚数• 固定输入管脚，可定义输入 / 输出管脚

• 工作电压– 电源电压– 接口电压

• 功耗• 封装形式• 配置方式

– 一次编程 OTP ( One Time Programmable)– 可再编程 ( Re-Programmable)

• 保持型， ISP• 上电加载型，需要外置 EPROM

Selection of CPLD or FPGA

• If circuit having a lot of combinatorial logic, use CPLD

• If circuit having a lot of Register logic, use FPGA

100% combinatorial logic0% Register

0% combinatorial logic100% Register

CPLD FPGA

cont...• Select CPLD or FPGA depends on

– the circuit application• CPLD for Combinatorial Logic > Register Logic• FPGA for Register Logic > Combinatorial Logic

– Gate count need• CPLD gate count is smaller than FPGA

– Speed Grade• CPLD having less pin to pin I/O delay• CPLD in general run faster than FPGA

– Memory need• FPGA support Memory

– Price• in general FPGA is lower in cost than CPLD

Select Guide

MAX 7000S Family Members

Feature

Usable gates

Macrocells

Max User I/O

tPD (ns)

fcnt (MHz)

7032/S

600

32

36

5

178.6

7064/S

1,250

64

68

6

151.5

7096

1,800

96

76

6

151.5

7128/S

2,500

128

100

7.5

125

7160/S

3,200

160

104

7.5

125

7192/S

3,750

192

124

10

100

7256/S

5,000

256

164

10

100

FLEX 10K Family Members

Feature 10K10 10K20 10K30 10K40 10K50 10K10010K70

Typical gates 10,000 20,000 30,000 40,000 50,000 100,00070,000

Logic elements 576 1,152 1,728 2,304 2,880 4,9923,744

Total RAM bits 6,144 12,288 12,288 16,384 20,480 24,57618,432

Total Registers 720 1,344 1,968 2,576 3,184 5,3924,096

Max User I/O 150 198 248 278 310 406358

Available Now Now Now Now Now NowNow

Multi-volt System Guideline

• Both CPLD and FPGA from Altera support Multi-volt system interface

• Couple suggestion when doing Mulit-volt design– 5V device, use 70000S/10K/6K/8KA/9K

– 3.3V device, use 7000A/10KA/10KV/6KA/9KA

– 2.5V device, use 7000B/10KE

cont...VCCINT

GNDINT

Core

VCCIO

GNDIO

VCCIO

GNDIO

User Option:Allows Interfaceto 5.0-, 3.3- &2.5-V Systems

VCCIO

Based on Process:User Connectsto Power Supply

VCCINT

cont...

Typical Min Input High

Typical Max Input Low

5.0V TTL 2.0V 0.8V

CMOS 3.5V 1.5V

3.3V TTL 2.0V 0.8V

CMOS 2.0V 0.8V

2.5V CMOS 1.6V 0.7V

Interface Logics

5.0-V Devices with MultiVolt Interface

(1) Input of Device Driven by Altera Device Output Must Have 5.0-V Tolerance.(2) Input of Device Driven by Altera Device Output Must Have 3.3-V Tolerance.(3) Use Open-drain outputs with pull-up to 5.0V.

Applicable Devices: FLEX10K, FLEX6000, FLEX8000, MAX7000/S, MAX9000/A

2.5V 3.3V 3.3V 5.0V 5.0V 2.5V 3.3V 3.3V 5.0V 5.0V

CMOS TTL CMOS TTL CMOS CMOS TTL CMOS TTL CMOS

5.0V (1) (1) (1)

3.3V (2) (3)

Input Levels Output Levels

5.0V

VCCINT VCCIO

Note: For some of the smaller packages, there are no VCCIO pins, and therefore does not support Multi-volt interface.

3.3-V Devices with MultiVolt Interface I

(1) Input of Device Driven by Altera Device Output Must Have 3.3-V Tolerance.(2) Use Open-drain outputs with pull-up to 5.0-V.

Applicable Devices: FLEX10KA, FLEX6000A, MAX7000A

2.5V 3.3V 3.3V 5.0V 5.0V 2.5V 3.3V 3.3V 5.0V 5.0V

CMOS TTL CMOS TTL CMOS CMOS TTL CMOS TTL CMOS

3.3V (1) (2)

2.5V

Input Levels Output Levels

3.3V

VCCINT VCCIO

Important: Do not tie the VCCIO of these devices to 5.0-V power source. This will damage our devices.

3.3-V Devices with MultiVolt Interface II

(1) Input of Device Driven by Altera Device Output Must Have 3.3-V Tolerance.(2) Use Open-drain outputs with pull-up to 5.0-V.

Applicable Devices: FLEX10KV, EPF8282AV, EPM7032V

2.5V 3.3V 3.3V 5.0V 5.0V 2.5V 3.3V 3.3V 5.0V 5.0V

CMOS TTL CMOS TTL CMOS CMOS TTL CMOS TTL CMOS

3.3V 3.3V (1) (2)

Input Levels Output Levels

VCCINT VCCIO

Important: Do not tie the VCCIO of these devices to 5.0-V or 2.5-V power source. This will damage our devices.

2.5-V Devices with MultiVolt Interface

(1) Input of Device Driven by Altera Device Output Must Have 3.3-V Tolerance.(2) Use Open-drain outputs with pull-up to 5.0-V.

Applicable Devices: FLEX10KE, FLEX10KB

2.5V 3.3V 3.3V 5.0V 5.0V 2.5V 3.3V 3.3V 5.0V 5.0V

CMOS TTL CMOS TTL CMOS CMOS TTL CMOS TTL CMOS

3.3V (1) (2)

2.5V

Input Levels Output Levels

2.5V

VCCINT VCCIO

Packaging Considerations

• Engineering– Pin Count– Board Space Efficiency– Pin Compatibility with Other Devices– Easy Prototype Development

• Manufacturing– Board Space Efficiency– PCB Trace Width Requirements– Compatibility with Solder Reflow Process– Quality / Yield / Cost

84

100

160

208

240

304

100

144

256

356

600

100

256

484

672

1.4

0.6

1.5

1.5

1.9

2.9

0.4

0.8

1.1

1.9

3.1

0.2

0.4

0.8

1.1

60

160

100

140

120

100

250

200

200

180

190

500

600

600

600

Packaging Metrics

PLCC

PQFP (RQFP)

TQFP

Standard BGA(1.27-mm Pitch)

FineLine BGA(1.0-mm Pitch)

1.27

0.65

0.65

0.50

0.50

0.50

0.50

0.50

1.27

1.27

1.27

1.00

1.00

1.00

1.00

29 x 29

14 x 23

28 x 28

28 x 28

32 x 32

40 x 40

14 x 14

20 x 20

27 x 27

35 x 35

45 x 45

11 x 11

17 x 17

23 x 23

27 x 27

Pin Count

BoardArea (in2)

Pin Density(Pins/in2)

Lead/Ball Pitch (mm)

Body Size(mm)

PackageType

Declining Usage Mainstream Usage Advanced Usage

PQFP

TQFP

TQFP

PQFP

Standard BGA

Standard BGA

TQFP

MicroBGA

TQFP

FineLine BGA

Standard BGA

FineLine BGA

FineLine BGA

PDIP

PLCC

PQFP

PGA

PGA

< 100 Pins

100 to 144

145 to 240

Above 240

Declining Mainstream AdvancedPin Count / Usage

Packaging Technology for PLDs

Higher Gate Count Has Driven Higher Pin Count

Declining Usage Mainstream Usage Advanced Usage

常用封装形式

84-Pin Plastic J-Lead Chip Carrier (PLCC)

100-Pin Plastic Thin Quad Flat Pack(TQFP)

208-Pin Plastic Quad Flat Pack(PQFP)

功耗

•

FPGA/CPLD 不同芯核电压器件流行趋势

资料来源：美国 Altera 公司

0%

20%

40%

60%

80%

100%

1992 1993 1994 1995 1996 1997 1998 1999 2000 2001

5.0 V

3.3 V2.5 V

1.8 V

初始

设计

百分

比

Power Consumption Improvements

0

2

4

6

8

10

PowerConsumption

(W)

EPF10K50 EPF10K100

3.3-V FLEX 10KA

5.0-V FLEX 10K

3.3-V Power Supply Reduces Power Consumption

P = VI

where:P = PowerV = VoltageI = Current

ISP /ICR Increases Flexibility

No Device Handling

No Bent Leads

Allows Generic Inventory

Easy Prototyping

Supports Changes during Manufacturing/ Test Flow

Allows Field Upgrades

Add Enhancements Quickly & Easily

Mount Unprogrammed Program In-System Reprogram in the Field

MAX+plus II ISP Flow

POF

MAX+plus II BitBlaster or other cable

JTAG Chain

Programmer TMSTCK

TDO

TDI

TMSTCK

TDO

TDI

TMSTCK

TDO

TDI

Any JTAGDevice

MAX 9000MAX 7000S

Any JTAGDevice

此接口既可作编程下载口，也可作

JTAG 接口

ALTERA 的 ByteBlaster （ MV ）下载接口

图 3-46 10 芯下载口

引脚 1 2 3 4 5 6 7 8 9 10

PS 模式 DCK GND CONF_DONE VCC nCONFIG - nSTATUS - DATA0 GND

JATG 模式 TCK GND TDO VCC TMS - - - TDI GND

表 3-3 图 3-46 接口各引脚信号名称

CPLD 和 FPGA 的编程与配置

CPLD 编程下载连接图

TCK 、 TDO 、 TMS 、 TDI 为 CPLD 的JTAG 口

对 CPLD 编程

CPLD 的 ISP 方式编程

多 CPLD 芯片 ISP 编程连接方式

CPLD 的 ISP 方式编程

FLEX10K PS 模式配置时序

使用 PC 并行口配置 FPGA

多 FPGA 芯片配置电路

注意：1 、不要忘了将多片配 置 控制信号 nCE 引 脚接地！2 、作为 PS 配置模式， 不要忘了将配置模式 控制信号脚 MSEL1 和 MSEL0 都接地！

FLEX 、 ACEX、 APEX 系列FPGA 配置电路

FPGA Passive Serial Configuration

被动串行配置模式

10 针标准配置 / 下载接口

通过配置电路后与 PC 机的并行

接口相接

对 FPGA 配置

FLEX 、 ACEX 、 APEX 等系列 FPGA 器件配置连线图

Altera 公司的 FPGA 配置方式与器件系列

器 件 功能描述 封装形式

EPC2 1695680× 1 位，3.3/5V 供电 20 脚 PLCC、32 脚 TQFP

EPC1 1046496× 1 位，3.3/5V 供电 8 脚 PDIP、20 脚 PLCC

EPC1441 440 800× 1 位，3.3/5V 供电 8 脚 PDIP、20 脚 PLCC

EPC1213 212 942×位，5V 供电 8 脚 PDIP、20 脚 PLCC、32 脚 TQFP

EPC1064 65 536×位，5V 供电 8 脚 PDIP、20 脚 PLCC、32 脚 TQFP

EPC1064V 65 536×位，5V 供电 8 脚 PDIP、20 脚 PLCC、32 脚 TQFP

FPGA 使用 EPC 配置器件的配置时序

用专用配置器件配置 FPGA

OTP 配置器件：

EPC1441 、 EPC1 、 EPC1213等

FPGA 配置器件

FPGA 的配置电路原理图

选择 Global Project Device… 项

注意，被编译文件的工程名为“ DAC” ，因此，其配置文件名应该为“ DAC . POF ”

编译前选择配置器件

对于低芯核电压 FPGA（如 EP1K30 ），需选择此

项，电路中的配置芯片应该接 3.3V 工作电压。

选择配置芯片的型号为 EPC1PC8

选择 PS 模式

编译前选择配置器件

MCU 用 PPS 模式配置 FPGA 电路

使用单片机配置 FPGA

单片机使用 PPS 模式配置时序

用 89C52 进行配置

可编程逻辑器件的电路设计• 电源滤波• 调试输出管脚• 不用管脚的处理• 上电过程

– VCCINT,VCCIO– Configure Time

• 设计注意事项– 同步时序电路– 复位输入 Global Reset input – 时钟考虑

设计实例• CPLD 设计实例

– CPLD 实验电路原理图• FPGA 设计实例

– FPGA 实验电路原理图

CPLD 实验电路板

CPLD 电路实验板框图

7128SLC84-15

JTAG

4 个按键

4 个发光管

1MHZ 晶振

1 个别数码管

5V Pwr

测试管脚

扩展接口

10 段条形LED

ISP, 电源滤波滤波电容

JTAG for ISP

数码管

a

b

cd

e

fg

共阴

晶振

FPGA 实验电路板

FPGA 电路板框图

FLEX10K10LC84-4

10, 000 门容量

4X4

键盘

6 个扫描显示数码管

1M 晶振FLASH 29F010

SRAM 62256

复位电路 扬声器

电源

JTAG 下载接口

ROM

信号输入

扩展电路

4x4 扫描键盘输入

0

1

1

1

0 1 1 1

1 0 1 1

1 1 0 1

1 1 1 0

扫描显示电路a

b

cde

f g

100000010000001000 …

下载电路和配置电路

JTAG

下载电路

配置ROM

下载模式选择电路

FLASH & SRAM

FLASH

128Kx8

SRAM32kx8

Generic PLD usage

• It apply to both EPLD and FPGA– always having 20% Macro-cell/Logic Cell not used

• have space for future add in logic purpose

– always having 20% of I/O pin not used• have space for future add in logic purpose

– always let Max+Plus II do the pin assign for you at the first time

• if some pin must be locked down, do it first. The rest of the I/O pin, let Max+Plus II assign it automatically

Always check the RPT file

• After Max+Plus II finish the compilation, it will generate a file named as “*.RPT”

• Connect the Vcc, Gnd as suggested by the RPT file

• Check the Pins

MaxPlus II 开发流程

SCH .gdfAHDL .tdfVHDL .vhd

Family DevcicePin AssigmentSysthesis Option

Scf :input Outputburied

EPC1MCUROM

ISP .pofICR .sof

设计输入 编译综合 下载调试 实际运行

Delay MatrixRegister FreqSetup/Hold

时序分析

时序仿真

AHDL

• Altera Hardware Description Language– develop by Altera

– integrate into the Altera software Max+Plus II

– description the hardware in language instead of graphic

• easy to modify

• easy to maintain

– very good for

• complex combinational logic

– BCD to 7 Segment converter

– address decoding

• state machine

• more than you want……..

AHDL 学习内容

• 组合逻辑电路的设计方法• 时序逻辑电路的设计方法• 状态机电路的设计方法• 层次化的设计方法

General AHDL Format

SUBSDESIGN decode( a0, a1, b : input; out1, out2 : output;)Variable c: : node; begin out1 = a0 & !a1; -- out1 c=!out1; out2 = c # b; % out2 %end;

关键字

I/O 端口定义

AHDL format

逻辑定义

中间变量

decode.tdf

AHDL 注释

一样

组合逻辑电路的设计方法• Boolean Expressions & Equations

• Truth Table

• IF-THEN-ELSE

• CASE Statement

• Bus Operation

• Tri-state Buffer

• Open Drain Buffer

Boolean Expressions & Equations

CONSTANT IO_ADDRESS = H“A";

SUBDESIGN decode1(

a[3..0] : input; nior : input; cs0 : output;

test : output; )variable

cs1 : node;begin

cs0 = (a[3..0] == H " A");cs1= !cs0;test=lcell(cs1);

end;

cs0=(a[3..0]==IO_ADDRESS);

cs0=(a[3..0]==B “101x ");

cs0=a3&!a2&a1&!a0;

Define node

常用运算符• Addition : +• Subtraction : -• Numeric Equality : ==• Not equal to : !=• Greater than : >• Greater than or equal to : >=• Less than : <• Less than or equal to : <=• Logical OR : #• Logical AND : &

Truth Tablei[3..0] Segment 7

0 0

1 1

2 2

F F

a

b

cd

e

fg

How easy to make any modification

IF-THEN-ELSESUBDESIGN priority( low, medium, high : input; highest_level[3..0] : output;)beginif ( high == B”1”) thenhighest_level[] = B”1000”;elsif (medium == B”1”) thenhighest_level[] = B”0100”;elsif (low == B”1”) thenhighest_level[] = B”0010”;elsehighest_level[] = B”0001”;end if;end;

CASE StatementSUBDESIGN decoder(low, medium, high : input; highest_level[3..0] : output;)variablecode[2..0] : node;begincode2=high;code1=medium;code0=low;case code[] iswhen 4 => highest_level[] = B”1000”;when 2 => highest_level[] = B”0100”;when 1 => highest_level[] = B”0010”;when others => highest_level[] = B”0001”;end case;end;

What is the usage of this statement

Bus OperationSUBDESIGN decode1( a[3..0], b[3..0] : input; out[3..0] : output;)beginout0 = a0 & b0;out1 = a1 & b1;out2 = a2 & b2;out3 = a3 & b3;end;

SUBDESIGN decode1( a[3..0], b[3..0] : input; out[3..0]: output;)beginout1[] = a[] & b[];end;

Same functionbut easier

More on Bus OperationBus Operationa[9..0], b[9..0]

– a[] = b[]; – a[7..4] = b[9..6];– a[9..8] = VCC;– a[9..8] = 1;– a[9..8] = 2;– a[9..8] = 3;– a[3..0] = GND– a[3..0] = 0;– temp = b0& b1;

a[2..1] = temp

a7=b9, a6=b8, a5=b7, a4=b6 % a[9..8] connect to VCC

a[9..8] = B”01”

a[9..8] = B”10” a[9..8] = B”11”

a[3..0] connect to GND a[3..0] = B”0000”

a2 = temp, a1 = temp

Advance Bus Operation• Bus

– b[3..0]• b3, b2, b1, b0 (having 4 members)

• MSB is b3, LSB is b0

• ARRAY BUS– a[3..0][2..0]

• a3_2, a3_1, a3_0, a2_2, a2_1, a2_0, a1_2, a1_1, a1_0, a0_2, a0_1, a0_0 (having 12 members)

• MSB is a3_2, LSB is a0_0

a[3..2][1..0] = b[];

a3_1 = b3 a3_0 = b2a2_1 = b1 a2_0 = b0

This one change first

Tri-state Buffer

Method 1 Method 2

SUBDESIGN tri_state(a, enable : input; b : output;)beginb = tri(a, enable);end;

SUBDESIGN tri_state( a, enable : input; b : output;)variable temp : tri;begintemp.in = a;temp.oe = enable;b = temp.out;end;

时序电路的设计

• Register– DFFE (D-FF with enable)

– TFF/TFFE

– JKFF/JKFFE

– SRFF/SRFFE

• Counter

• Use “Clock Enable”

Register Logic

Method 1 Method 2

SUBDESIGN flip_flop( d, clk : input; q : output;)beginq = dff(d,clk, ,);end;

SUBDESIGN flip_flop( d, clk : input; q : output;)variable temp : dff;begintemp.d = d;temp.clk = clk;q = temp.q;end;

I want a D-Flipflop

Register Buses

SUBDESIGN bus_reg( clk, d[7..0] : input; q[7..0] : output;)variable ff[7..0] : dff;beginff[].clk = clk;ff[].d = d[];q[] = ff[].q;end;

ff[0].clk = clk;ff[1].clk = clk;ff[2].clk = clk;ff[3].clk = clk;ff[4].clk = clk;ff[5].clk = clk;ff[6].clk = clk;ff[7].clk = clk;

ff[0].d = d[0];ff[1].d = d[1];ff[2].d = d[2];ff[3].d = d[3];ff[4].d = d[4];ff[5].d = d[5];ff[6].d = d[6];ff[7].d = d[7];

q[0] = ff[0].q;q[1] = ff[1].q;q[2] = ff[2].q;q[3] = ff[3].q;q[4] = ff[4].q;q[5] = ff[5].q;q[6] = ff[6].q;q[7] = ff[7].q;

Design 8 bits Counter is Easy

SUBDESIGN 8bits(clk : input; q[7..0] : output;)variable temp[7..0] : dff;begintemp[].clk = clk;temp[].d = temp[].q +1 ;q[] = temp[].q;end;

9-bit up/down counter with load and enable

SUBDESIGN ahdlcnt (  clk,

ld, en, clr, up/down,d[8..0] :INPUT;

  q[8..0] :OUTPUT;) VARIABLE  count[8..0] :DFF; 

BEGIN  count[].clk = clk; count[].clrn = !clr;  IF ld THEN count[] = d[]; ELSIF en THEN IF up/down THEN count[] = count[] + 1; ELSE count[] = count[] - 1; ENDIF; ELSE count[] = count[]; END IF; q[] = count[];END;

Clock Enable• If you wish to load a register on a specific rising edge of the global

Clock, Altera recommends that you use the Clock Enable input of one of the DFFE, TFFE, JKFFE, or SRFFE Enable-type flipflops to control when the register is loaded.

Reg_ctrl[3..0].d =DB[3..0];

Reg_ctrl[3..0].clk = niow;

Reg_ctrl[3..0].ena= cs;

Reg_ctrl[3..0].d =DB[3..0];

Reg_ctrl[3..0].clk = niow&cs;

State MachineSUBDESIGN simple( clk, reset, jump : input; q : output;)variable ss : MACHINE WITH STATES (S0,S1);beginss.clk = clk;ss.reset = reset;case ss is when s0 => q = gnd; if (jump) then ss = s1; end if; when s1 => q = vcc; if (jump) then ss = s0; end if;end case;end;

State Machine Diagram

Note : All State Machine Variable mustbe associated with a CLOCK

S0

S1

jump=1jump=1

q = 0

q = 1

jump=0

jump=0

状态机仿真波形

if (jump) thenss = s1;end if;

if (jump) thenss = s0;end if;

State Machine (2)SUBDESIGN stepper( reset, ccw, cw, clk : input; phase[3..0] : output;)variable ss : MACHINE OF BITS (temp[3..0]) WITH STATES ( s0 = B”0001”, s1 = B”0010”, s2 = B”0100”, s3 = B”1000”);beginss.clk = clk;if (reset) thenss = s2;end if;phase[] = temp[];

TABLE ss, ccw, cw => ss; s0, 1, x => s3; s0, x, 1 => s1; s1, 1, x => s0; s1, x, 1 => s2; s2, 1, x => s1; s2, x, 1 => s3; s3, 1, x => s2; s3, x, 1 => s0;END TABLE;end;

Note : No need to declare what is TEMPIt is automatic declare as DFF

仿真波形

User can control the State Bit

State Machine without Recover StateSUBDESIGN recover( clk, go : input; ok : output;)variable sequence : MACHINE OF BITS (q[2..0]) with STATES ( idle, one, two, three, four, illegal1, illegal2, illegal3);beginsequence.clk = clk;case sequence iswhen idle => if (go) then sequence = one; end if;when one => sequence = two;when two => sequence = three;when three => sequence = four;end case;ok = (sequence == four);end;

State Machine stuck at FOUR

Better have Recover within State Machine

SUBDESIGN recover( clk, go : input; ok : output;)variable sequence : MACHINE OF BITS (q[2..0]) with STATES ( idle, one, two, three, four, illegal1, illegal2, illegal3);beginsequence.clk = clk;case sequence iswhen idle => if (go) then sequence = one; end if;when one => sequence = two;when two => sequence = three;when three => sequence = four;when OTHERS => sequence = idle;end case;ok = (sequence == four);end;

Three bits have Eight State

Only Five State is interesting,but better have this RECOVER options

层次化的设计方法 --- 模块的调用

VARIABLE counter : 4count; decoder : 16dmux;

BEGIN counter.clk = clk; counter.dnup = GND; decoder.(d,c,b,a) = counter.(qd,qc,qb,qa); out[15..0] = decoder.q[15..0];END;

INCLUDE "4count";

INCLUDE "16dmux";

SUBDESIGN macro1

(

clk : INPUT;

out[15..0] : OUTPUT;

)

LPM 模块的调用INCLUDE "lpm_add_sub.inc";

SUBDESIGN lpm_add1

(

a[8..1], b[8..1] : INPUT;

c[8..1] : OUTPUT;

carry_out : OUTPUT;

)

BEGIN

% Megafunction instance with positional port association %

(c[], carry_out, ) = lpm_add_sub(GND, a[], b[], GND,,,)

WITH (LPM_WIDTH=8,

LPM_REPRESENTATION="unsigned");

END;

AHDL with Graphic

• Use the File menu to create Symbol for the AHDL design

• The symbol can be used for graphic entry

生成用户库

Hierarchical Design

• Break design into modules• Enter and debug each module separately• Create Default Symbols or Include Files

for each module• Use these modules in the top-level design

file• Assign each module with individual logic

options, if necessary

AHDL 帮助

AHDL 上机实验• 设计一个秒表，并验证设计

– 设计内容• 用于体育运动计时的秒表

– 系统描述• 输入： 一个按键• 输出： 60 秒数字显示，带分钟，最长可计 9 分 59 秒• 功能：开始计时 / 停止计时 / 回零• 具体请参考实验二讲义

– 验证方案• 用 FPGA 实验电路板验证• 确认输入的实现方式• 输出的表现形式