EDA

3 Verilog HDL3.1 3.2 Verilog HDL3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 Verilog HDL3.13 3

3.1 Verilog HDLVerilog HDLVerilog HDL Verilog HDL

3.1 Verilog HDLVerilog HDLHradware Description Language )Verilog HDLVerilog HDLVerilog HDL

Verilog HDL

3.1 Verilog HDL1983GDAGateWay Design AutomationPhil Moorby1989CadenceGDA1990 CadenceVerilog HDL1995IEEEVerilog HDL1364-19951999Verilog

3.1 Verilog HDLVerilog HDL(system level): case(algorithmic level): RTL(register transfer level): (gate level): (switch level): 3.12

3.1 Verilog HDLCUDPUser Designed Primitive C

3.2 Verilog HDLVerilog HDLVerilog HDLVerilog HDL

3.2 Verilog HDLVerilog HDL[3.2.1] 8module adder8 ( cout,sum,a,b,cin ); output cout; // output [7:0] sum; input [7:0] a,b; // input cin; assign {cout,sum}=a+b+cin;endmodule()Verilog HDLmoduleendmodulemoduleendmodule24//

3.2 Verilog HDL [3.2.2] 8module counter8 ( out,cout,data,load, cin,clk ); output [7:0] out; output cout; input [7:0] data; input load, cin,clk ; reg[7:0] out; always @(posedge clk) begin if(load) out = data; // else out = out + 1 + cin; // 1 end assign cout = &out & cin; //out8hFFcin1cout1endmodule

3.2 Verilog HDL [3.2.3] 2module compare2 ( equal,a,b); output equal; input [1:0] a,b; assign equal = ( a = = b ) ? 1:0; / * abequal 10 * /endmodule/ * * /

3.2 Verilog HDL[3.2.4] module trist2(out,in,enable); output out; input in, enable; bufif1 mybuf(out,in,enable);endmoduleVerilog Inputs | OutputIN ENABLE| OUTX0| Z11| 101| 0bufif1

3.2 Verilog HDL[3.2.5] module trist1(out,in,enable); output out; input in, enable; mytri tri_inst(out,in,enable);endmodule

module mytri(out,in,enable); output out; input in, enable; assign out = enable? in:bz; / * enable1out = in * /endmoduletrist1mytritri_inst

3.2 Verilog HDLVerilog HDLmoduleendmoduleVerilog HDLendmodulebegin_endfork_join/*.....*///...

3.2 Verilog HDLVerilog HDLVerilog (block) Verilog moduleendmodule4module block1(a,b,c,d ) input a,b,c output d wire x assign d = a | x assign x = ( b & ~c )endmoduleI/O1234

3.2 Verilog HDLVerilog 31assign assign x = ( b & ~c )2instantiateand myand3( f,a,b,c)1Verilog HDL234

3.2 Verilog HDL3 always always @(posedge clk) // begin if(load) out = data; // else out = data + 1 + cin; // 1 end1always 2always if-elsecase3 always assign assignalways

3.2 Verilog HDLVerilog HDLmodule (< >) output input //1assign wire assign = //2always always @() begin // //if // case // while,repeat,for // task,function end

3.2 Verilog HDL// 3 < module_name > < instance_name > (); // < instance_name > (); // endmodule

3.2 Verilog HDLVerilog HDLandnotorbuf alwaysassignbegincasecasexelseendforfunctionifinputoutputrepeattabletimewhilewireVerilog HDL P285A

3.2 Verilog HDLVerilog HDLedgeelseendendcaseendfunctionendprimitiveendmoduleendspecifyendtableendtaskeventforforceforeverforkfunction highz0highz1 ififnoneinitialinoutinputintegerjoinlargemacromodulemediummodulenandnegedgenor notnotif0notif1nmosoroutputparameterpmosposedgeprimitivepulldownpulluppull0pull1andalwaysassignbeginbufbufif0bufif1casecasexcasezcmosdeassigndefaultdefparamdisable

3.2 Verilog HDLVerilog HDLtri0tri1 vectoredwaitwandweak0weak1whilewireworxnorxorrcmosrealrealtimeregreleaserepeatrnmosrpmosrtranrtranif0rtranif1scalaredsmallspecifyspecparamstrengthstrong0 strong1supply0supply1tabletasktrantranif0tranif1timetritriandtriortrireg

3.2 Verilog HDL Verilog HDL$$Verilog HDLA_99_ZReset_54MHz_Clock$Module 123a$datamodule7seg.v

3.2 Verilog HDLVerilog HDLVerilog HDL1 2 VerilogHDL

3.2 Verilog HDL1Verilog HDL2$341

3.2 Verilog HDL5678 parameter 1=2= define 1

3.2 Verilog HDL1234always45alwaysalways2 always

3.2 Verilog HDL6always7alwaysalwaysalways8always always @(posedge clk or negedge set or negedge reset)9alwaysalways2 1

3.2 Verilog HDL10alwaysregregreg module rw2( clk, d, out1) input clk, d output out1 reg out1 always @(posedge clk) // out1

3.2 Verilog HDLreg module rw2( clk, d, out1) input clk, d output out1 reg out1 always @(d) // out1

3.2 Verilog HDL11RTL12462N1314integertime3264152 4

3.3

3.3 Verilog HDL194integerparameterregwirelargemedium scalared smalltimetritri0tri1triandtriortriregvectoredwandworxzparameter

3.3

314bBdDhHoO

8b110001018 hc5 32hc532197

3.3 2xzxz8b1001xxxx8 h9x8b1010zzzz8 hazxzxz[]8bzx = 8bzzzz_zzzx []8b1x = 8b0000_001xzcasez[] casez (select) 4b???1: out = a; 4b??1?: out = b; 4b?1??: out = c; 4b1???: out = d; endcase

3.3

3-8d5 //5= 8b111110118 d-5 //_ 16b1010_1011_1100_1111 // 8b_0011_1010 //3210 = 32d10 = 32b1010-1 = -32d1 = 32b11111111 = 32hFFFFFFFF

3.3 4parameterparameterparameter 1 = ,2 = , parameter addrwidth = 16 // parameter addrwidth = datawidth*2 //,

3.3 defparamdefparam .1 = , .2 = , defparamdefparam#

3.3 []module mod ( out, ina, inb); parameter cycle = 8, real_constant = 2.039, file = /user1/jmdong/design/mem_file.dat; endmodule

module test; mod mk(out,ina,inb); // mod defparam mk.cycle = 6, mk.file = ../my_mem.dat; // endmodule

3.3 # []module mod ( out, ina, inb); parameter cycle = 8, real_constant = 2.039, file = /user1/jmdong/design/mem_file.dat; endmodule

module test; mod # (5, 3.20, ../my_mem.dat) mk(out,ina,inb); // mod endmodule # 1,2,

3.3 193nets typeregister type memory type1. nets

netswiretriwortriorwandtriandtri1tri0supply1supply010nets

3.3 wirenetsassign/wireassignwire 1,2, ,n;wire[n-1:0] 1,2, ,m; wire[n:1] 1,2, ,m;nmwire

3.3 ,initialalwaystaskfunction registerreginteger32real64time2. register

3.3 registernets registerregisterassignregister

3.3 regreg 1,2, ,n;reg[n-1:0] 1,2, ,m; reg[n:1] 1,2, ,m;nmreg[] reg[4:1] regc,regd; //regc,regd4regreg

3.3 reg module rw1( a, b, out1, out2 ) input a, b output out1, out2 reg out1 wire out2 assign out2 = a always @(b) out1

3.3 reg module rw2( clk, d, out1, out2 ) input clk, d output out1, out2 reg out1 wire out2 assign out2 = d & ~out1 ; always @(posedge clk) begin out1

3.3

regVerilog HDLregmemoryRAMROMregmemoryregreg[n-1:0] [m-1:0]; reg[n-1:0][m:1];nm3. memoryQuartus IIVerilog HDL

3.3 [] reg[n-1:0] rega//n reg mema [n-1:0] //n1 n [] rega = 0 // mema = 0 // mema[8] = 1 // mema[1023:0] = 0 //memoryreg

3.4

3.4 93 ~

3.4 %% [] -11%3 -2xx MAX + PLUS II/ %Quartus II

*/%

3.4 [] /%

3.4 arithmetic.vwf9/4 = 29%4 =1

3.4 (1b1)(1b0)4bxx00, (1bx) 4bxx111b110x

&&()||()!()

3.4 &&||[] a>b)&&(b>c) a>b && b>c a= =b)||(x= = y) a= =b||x= = y !a)||(a>b) !a||a>b

3.4 0 [] A = 5b11001B = 3b101 A & B = 5b11001&5b00101= 5b00001

~ &|^^~~^

3.4 [] &&&&&1&&& 1b1 1bx 1bx

3.4 110x10xx[] a

3.4 110x(= =)(= = =):,1xzx10xz,10= = == =casecaseMAX + PLUS IIQuartus II

=== =====

3.4

[] if(A = = 1bx) $display(AisX)//A A = = 1bxx if(A = = = 1bx) $display(AisX)//AA = = = 1bx1

3-1 = =3-2 = = =10x10

==0 1 x z01xz1 0 x x0 1 x xx x x xx x x x

===0 1 x z01xz1 0 0 00 1 0 00 0 1 00 0 0 1

3.4 , 1[]reg[3:0] a; b=|a; // b =( (a[0] | a[1]) | a(2)) | a[3]

& ~&|~ |^^~~^

3.4 MAX + PLUS IIA>>n A3 = 4b0001 4b1001>>4 = 4b0000 4b1001

3.4 = 12[] assign out = sel? in1:in012sel=1out=in1 sel=0out=in0

3.4 { }{12n}[1] output [3:0] sum; // output cout; // input[3:0] ina,inb; input cin; assign {cout,sum} = ina + inb +cin//[2] {a,b[3:0],w,3b101} = {a,b[3],b[2],b[1],b[0],w,1b1,1b0,1b1}

3.4 {4{w}} //{w,w,w,w} {b,{3{a,b}}} //{b,{a,b},{a,b},{a,b}}{b,a,b,a,b,a,b}32{1,0} = 64h00000001_00000000 {1,0}2b10

3.4 3-3 []a>b)&&(b>c) a= =b)||(x= = y) !a)||(a>b)

! ~

* / % >< >== = ! = === !==& ~&^ ^~| ~|&&||

3.5

3.5 3-4 Verilog HDL

begin_endfork_joinQuartus IIif_elsecaseforeverMAX+PLUS IIrepeatMAX+PLUS IIwhileMAX+PLUS IIforinitialQuartus IIalwaystaskMAX+PLUS IIfunctiondefineincludeQuartus IItimescaleQuartus II

3.5 Quartus IIQuartus IIrepeattaskMAX+PLUS IIQuartus IIforever whileMAX+PLUS IIQuartus II4fork_joininitial include timescaleQuartus IIModelSim

3.6

3.6 1assignwire [] assign c=a&b; //abcwire

2regnon-blocking)

3.6 1. always @(posedge clk) begin b

3.6 2. always @(posedge clk) begin b = a ; c = b; end cb

3.6

non-blocking) ( b

3.6 begin_endfork_joinbegin_endQuartus II1.

3.6 begin 1 2 nendbegin 1 2 nendregintegerreal

3.6 [1]begin b = a ; c = b; //ca end

[2] begin b = a ; #10 c = b; //10 end# #

3.6 [3] parameter d = 50 reg[7:0] r begin // # d r = h35 # d r = hE2 # d r = h00 # d r = hF7 # d > end_wave //end_wave endd

3.6 2. fork_joindisable

fork

3.6 fork 1 2 njoinfork 1 2 njoinregintegerreal timeevent

3.6 [4] reg[7:0] r fork // # 50 r = h35 # 100 r = hE2 # 150 r = h00 # 200 r = hF7 # 250 > end_wave //end_wave join3fork_join

3.7 if-elsecase

3.7 if-elseif-else30z1begin_endif-elsecasealways

3.7 if(expression) if(expression = = 1) if(expression) if(expression = 1) if 1if1 1else 2if1 1else if22 else ifnn123

3.7 ififelsebegin_endifelseif1 if21 else 2else if33 else 4if1 begin if21 endelse 2ifelsebegin_endifif

3.7 [] 60BCDcounter60.valwaysassignalways

3.7 if (reset) else if (load) else if (cin) 3if if (reset) if (load) if (cin)3resetloadcin133qout

3.7

cinalwaysassigncount60.vwfcin=11

3.7 casecase 11 22 nn default: n+1endcase1. case, case3casecasezcasexcaseif-else

3.7 1~ndefaultcasedefault!1~n1~n

3.7 2. casezcasexcasecase01casezzcasexzxxz

3.7 module mux_z(out,a,b,c,d,select); output out; input a,b,c,d; input[3:0] select; reg out; // always@ (select[3:0] or a or b or c or d) begin casez (select) 4b???1: out = a 4b??1? : out = b 4b? 1?? : out = c 4b 1??? : out = d endcase endendmodule[] casez

3.7 1ifelsecasedefault

3.7 ifal0qal0q0

3.7 ifelsecasedefaultalways@ (sel[1:0] or a or b) case(sel[1:0]) 2b00: q

3.8 forrepeatwhileforever

3.8

4for312332repeatnwhileforeverdisable

3.8 forfor 123for whilebegin while() begin endendforwhile

3.8 []for744module vote7 ( pass,vote ); output pass; input [6:0] vote; reg[2:0] sum; //sumreg integer i; reg pass; always @(vote) begin sum = 0; //sum0 for(i = 0;i=3d4)

3.8 voter7.vwf4,pass=1 for1166

3.8 [] formemorybegin_endbegin:init_mem reg[7:0] tempi; // for(tempi = 0;tempi

3.8 mult_for.vif(b[i]= =1) a(i-1) i-10a,b

3.8 mult_for.vwf!

3.8 repeatnrepeat repeat begin endMAX + PLUS IIQuartus II

3.8 []repeat8for

3.8 mult_repeat.vwfmult_ for.vwf

3.8 whileforever1.whilewhile while begin endMAX + PLUS IIQuartus

3.8 123while@posedge clock

3.8 []while81module count1s_while ( count,rega,clk ); output[3:0] count; input [7:0] rega; input clk; reg[3:0] count; always @(posedge clk) begin:count1 reg[7:0] tempreg; // count = 0; // count0 tempreg = rega; // tempreg rega while(tempreg) // tempreg0 begin if(tempreg[0]) count = count+1; //tempreg1 count1 tempreg = tempreg >>1; //1 end endendmodulefor

3.8 [] for81

3.8 count1s_for_good.vwf

3.8 2.foreverforeverforever forever begin enddisablealways initialinitial begin : Clocking clk = 0; #10 forever #10 clk = !clk; endinitial begin : Stimulus disable Clocking; // end

3.9 alwaysinitialtaskfunction

3.9 initialalwaystaskfunction4always(:

3.9 alwaysregisterregintegerrealtimealwaysalwaysalways 1alwaysbegin_endfork_joinalways @ (posedge clk or negedge clear) begin if(!clear) qout = 0; // else qout = 1; end

3.9

[3.9.1]0 always areg = ~areg;

[3.9.2]2always define half_period 50 module half_clk_top; reg reset, clk; // wire clk_out; // always #half_period clk = ~clk; endmodule

3.9

[3.9.3] alwaysTFF8

3.9 alwaysalways @ () begin // // if // case // whilerepeatfor // taskfunction end! orxzalways

3.9 alwaysposedgenegedgealways@ (posedge clock or posedge reset) begin endalways@ (a or b or c) begin endalways always

3.9 always always1always @ (Inputs) //or begin // end 2always @ (Inputs) //or if (Enable) begin // end

3.9 3always @ (posedge Clock) // Clock only begin // end 4always @ (posedge Clock or negedge Reset)// Clock and Reset only begin if (! Reset) // // else // end //

3.9 1alwaysif - else ififalways @ posedge min_clk or negedge reset) begin if (reset) min

3.9 initialinitial begin 1 2 n endMAX+PLUS Quartus [3.9.4] initial initial begin inputs = b000000; #10 inputs = b011001; #10 inputs = b011011; #10 inputs = b011000; #10 inputs = b001000; end

3.9 [3.9.5] parameter size=16;reg[3:0] addr;reg reg1;reg[7:0] memory[0:15];initial begin reg1 = 0; for(addr=0;addr

3.9 taskfunctiontaskfunction

3.9 1.tasktask endtask1,2, MAX + PLUS IIQuartus

3.9 [3.9.6] task my_task; input a,b; inout c; output d,e; // c = foo1; d = foo2; // e = foo3; endtaskmy_taskv,w,x,y,z); vwxabc cdexyz1module2I/O3

3.9 [3.9.7] 44

3.9 sort4.v $random32 $random % bb>0-b+1~b-1{$random}%150~14

3.9 sort4.vtask_Top.wlf

3.9 2.function function endfunction1reg

3.9 12function[7:0] gefun; // input [7:0] x; // gefun = count; // endfunction

assign number = gefun(rega); //

3.9 #@wait/

3.9 [3.9.8] 80

3.9 count0s_function.vwf

3.9 [3.9.9]

3.9 tryfunct.v

3.9 tryfuncttop.v(Modelsim)nn!= n(n-1)(n-2) 2155!=5x4x3x2x1=120

3.9 3-5

task function)inoutoutputinout

3.10 defineincludetimescale

3.10 definedefine [] define IN ina+inb+inc+indVerilog HDL

3.10 define

3.10 Verilog HDL[] module test; reg a,b,c,d,e,out; define expression a + b + c + d; assign out = expression + e; assign: assign out = a + b + c + d; + e; //

3.10 [] module test; reg a,b,c; wire out; define aa a + b define cc c +aa //aa cc assign out = cc; assign: assign out = c + a + b;

3.10 includeinclude MAX + PLUS IIQuartus file2.vinclude file2.v

3.10 1taskinclude2includeinclude

3.10 [] include16adder

addersizemy_size

3.10 includennincludeincludeinclude aaa.v bbb.v //include parts/count.v //include aaa.v include bbb.v //

3.10 includeinclude aaa.v include bbb.v //

3.10 timescaletimescale / MAX + PLUS IIQuartus

3.10 timescale 1ps / 1ns // timescale 1ns / 1ps // timescale110100smsusnspsfs

3.10 [] timescaletimescale 10ns / 1ns //10ns1nsreg sel; initial begin #10 sel = 0; // 10ns10sel0 #10 sel = 1; // 10ns20sel1 end

3.11

3.11 alwaysalways always [3.11.1] [3.11.2]

3.11 [3.11.1]1module serial1(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin q=~q; // a=~q; endendmodule[3.11.2]2module serial2(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin a=~q; q=~q; endendmoduleqqqqaqaq

3.11 serial1.vwfserial2.vwfaqaqq=~q; a=~q;a=~q; q=~q;

3.11 alwaysassign [3.11.3] [3.11.4]alwaysalways[3.11.2] qaparall1.vwfqq

3.11 [3.11.3]1module parall1(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin q=~q; end always @(posedge clk) begin a=~q; endendmodule[3.11.4]2module parall2(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin a=~q; end always @(posedge clk) begin q=~q; endendmodule

3.12 Verilog HDLVerilog HDLVerilog HDL

3.12 Verilog HDLVerilog HDLVerilog HDLVerilog HDLVerilog HDL(system level): case(algorithmic level): RTL(register transfer level): (gate level): (switch level):

3.12 Verilog HDL Verilog HDL ( ) 269 notandnandornorxorxnorbuf bufif1bufif0notif1notif01 2

3.12 Verilog HDL[3.12.1] 41!

cntrl1 cntrl2out0 0 0 11 01 1in1in2in3in4

3.12 Verilog HDL

3.12 Verilog HDLVerilog HDL,,RTL1. [3.12.2] 41module mux4_1(out,in1,in2,in3,in4,cntrl1,cntrl2); output out; input in1,in2,in3,in4,cntrl1,cntrl2; assign out=(in1 & ~cntrl1 & ~cntrl2) | (in2 & ~cntrl1 & cntrl2) | (in3 & cntrl1 & ~cntrl2) | (in4 & cntrl1 & cntrl2) ;endmodule

3.12 Verilog HDL2. case [3.12.3] case41module mux4_1(out,in1,in2,in3,in4,cntrl1,cntrl2); output out; input in1,in2,in3,in4,cntrl1,cntrl2; reg out; always @(in1 or in2 or in3 or in4 or cntrl1 or cntrl2) case ({cntrl1,cntrl2}) 2b00:out=in1; 2b01:out=in2; 2b10:out=in3; 2b11:out=in4; default :out=1bx; endcaseendmodulecasealways

3.12 Verilog HDL3. case[3.12.4] 41module mux4_1(out,in1,in2,in3,in4,cntrl1,cntrl2); output out; input in1,in2,in3,in4,cntrl1,cntrl2; assign out= cntrl1? (cntrl2? in4 :in3) : (cntrl2? in2 :in1) ;endmodulecntrl1=1cntrl1=0

3.12 Verilog HDLVerilog HDLRTL

3.12 Verilog HDL1RTLRTL2if-elsecasecaseif-else

3.13 12

3.13 1always[3.13.1] Dalwaysif-else

3.13 qqnalwaysalways

3.13 2alwaysif [3.13.2] startenable always@(posedge start or posedge reset) if (reset) enable

3.13 startreset0enablescan_data1startscan_data1startreset1enable=1scan_data1

3.13 else enable

3.13 3I/O [3.13.3] 5run_cntregoutput run_cnt;reg[4:0]run_cnt;

output[4:0] run_cnt; // reg[4:0]run_cnt;

3.13 40 [3.13.4]high[3:0]mid[3:0]low[3:0]000clk_4Hzcount_4clk_4Hz0high[3:0]mid[3:0]low[3:0]0

3.13 module f20MHz_to_6MHz_4Hz(clkin,clr,clk_6M,clk_4); inputclkin,clr; outputclk_6M,clk_4; regclk_6M,clk_4; reg[2:0]count_6M; reg[15:0]count_4; parametercount_6M_width=3; parametercount_4_width=5000000; always@(posedge clkin or posedge clr) beginif(clr) begin count_4=0;clk_4=0; endelse begin if(count_4==count_4_width-1) // begin count_4=0; clk_4=1; end else begin count_4=count_4+1; clk_4=0; end end endendmodule2^23=838860823[22:0] [15:0]clk_400

3.13 5if-else

63

Verilog HDL6Verilog HDLP146~181

Verilog HDL P146Verilog HDLVerilog HDL P178Verilog HDLVerilog HDL P146 andorbufif1(bufif0)nandVerilog HDLVerilog HDLP178 Verilog HDLC

Verilog HDL P147

Verilog HDL P147counter8counter8.vwf1

Verilog HDLP193=1:212

Verilog HDLP19

Verilog HDLP20

Verilog HDLP233 PCM

Verilog HDL P149Verilog HDLP213.2.2Verilog HDL P150 3.10 ModelSimVerilog HDLP33verilog Golden Reference Guide.pdfP83Verilog P97Verilog P66~6718 parameter datawidth=8,addrwidth= datawidth*2; define IN ina+inb+inc+ind

1 RTL 4always 3.9 always814regintegertime Verilog HDL19

11

parameter datawidth =8,addrwidth = datawidth*2 //parameter nets

/wire//wirewire wire[7:0] in,out; assign out=in; //

integerealtime

b