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Slide 2 Even and odd memory banks of 8086 Minimum mode operation Maximum mode operation Intel Pentium features Pentium pro features Pentium MMX features Concept of Hyper threading Core 2 duo processor Slide 3 Even and odd memory banks of 8086 Logically, memory is implemented as a single 1M 8 memory chunk. The byte-wide storage locations are assigned consecutive addresses over the range from 00000 through FFFFF. Physically, memory is implemented as two independent 512Kbyte banks: the low (even) bank and the high (odd) bank. Data bytes associated with an even address (00000, 00002, etc.) reside in the low bank, and those with odd addresses (00001, 00003, etc.) reside in the high bank. Slide 4 Even and odd memory banks of 8086 Address bits A 1 through A 19 select the storage location that is to be accessed. They are applied to both banks in parallel. A 0 and bank high enable (BHE) are used as bank-select signals. Each of the memory banks provides half of the 8086's 16-bit data bus. The lower bank transfers bytes of data over data lines D 0 through D 7, while data transfers for a high bank use D 8 through D 15. Slide 5 Even and odd memory banks of 8086 Slide 6 The 8086 microprocessor accesses memory as follows: To access an even-addressed storage location, A0 is set to logic 0 to enable the low bank of memory and BHE to logic 1 to disable the high bank. Data are transferred to or from the lower bank over data bus lines D 0 through D 7. Even and odd memory banks of 8086 Slide 7 To access an odd addressed storage location such as X + 1. A0 is set to logic 1 and BHE to logic 0. This enables the high bank of memory and disables the low bank. Data are transferred over bus lines D 8 through D 15. D 8 represents the LSB. Even and odd memory banks of 8086 Slide 8 Minimum mode operation Minimum Mode Operation It is obtained by connecting the mode selection pin MN/MX to +5.0V(Giving logic high level) The minimum mode allows the 8085A, 8 bit peripherals to be used with the 8086/8088 without any special considerations Slide 9 Minimum mode operation Minimum mode unique signals Slide 10 8086 Minimum-mode block diagram Slide 11 CLK READYR ESET 8284A CLOCKG ENE- RATOR WAIT STATE GENERATOR MN/MX M/IO INTA RD WR DT/R DEN ALE AD0- AD15 A16-A19 8282 LATCH 8286 TRAN- CEIVER RAM 2142 2716 PROM PERI- PHERAL DATA ADDR/DATA ADDR BASIC 8086 MINIMUM MODE SYSTEM Slide 12 CLK M/IO ALE ADDR/ DATA ADDR/ STATUS RD/INTA READY DT/R DEN T1T2T3TWTW T4 A15-A0 A19-A16 RESERVED FOR DATA VALID D15-D0 MEMORY ACCESS TIME Slide 13 CLK M/IO ALE ADDR/ DATA ADDR/ STATUS READY DT/R DEN T1T2T3TWTW T4 A15-A0 A19-A16 DATA OUT (D15-D0) WR Slide 14 Minimum Mode Interface Address/Data bus: 20 bits vs 8 bits multiplexed Status signals: A16-A19 multiplexed with status signals S3-S6 respectively S3 and S4 together form a 2 bit binary code that identifies which of the internal segment registers was used to generate the physical address that was output on the address bus during the current bus cycle. S5 is the logic level of the internal interrupt enable flag, s6 is always logic 0. Slide 15 S4 S3 Address status 0 0 Alternate(relative to ES segment) 0 1 Stack (relative to SS Segment) 1 0 Code/None (relative to CS segment or a default zero) 1 1 Data (relative to DS segment) Minimum Mode Interface Slide 16 Maximum mode unique signals Slide 17 Maximum-mode interface circuit diagram (8086) Slide 18 Maximum Mode 8086 System Slide 19 Maximum Mode Interface For multiprocessor environment 8288 Bus Controller is used for bus control WR,IO/M,DT/R,DEN,ALE, INTA signals are not available Instead: MRDC (memory read command) MWRT (memory write command) AMWC (advanced memory write command) IORC (I/O read command) IOWC (I/O write command) AIOWC (Advanced I/O write command) INTA (interrupt acknowledge) Slide 20 Status Bits They indicate the function of the current bus cycle. They are normally decoded by the 8288 bus controller Slide 21 DEN, DT/R and ALE signals are the same as minimum-mode systems LOCK: when =0, prevents other processors from using the bus QS 0 and QS 1 (queue status signals) : informs about the status of the queue RQ/GT 0 and RQ/GT 1 are used instead of HOLD and HLDA lines in a multiprocessor environment as request/grant lines. Maximum Mode Signal Description Slide 22 Memory Read timing in Maximum Mode Here MRDC signal is used instead of RD as in case of Maximum Mode S0 to S2 are active and are used to generate control signal. Slide 23 Memory Write timing in Maximum Mode Slide 24 Intel Pentium Features 1)64 bit data bus 2)Instruction cache 3)Data cache 4)Two parallel execution units 5)Floating point unit 6)Branch prediction logic 7)Data integrity and error detection 8)Dual integer processor 9)Functional redundancy check 10) Superscalar architecture Slide 25 Superpipelining: The Pentium Pro dramatically increases the number of execution steps, to 14, from the Pentium's 5. Integrated Level 2 Cache: The Pentium Pro features a dramatically higher-performance secondary cache compared to all earlier processors. Instead of using motherboard-based cache running at the speed of the memory bus, it uses an integrated level 2 cache with its own bus, running at full processor speed, typically three times the speed that the cache runs at on the Pentium. The Pentium Pro's cache is also non-blocking, which allows the processor to continue without waiting on a cache miss. 32-Bit Optimization: The Pentium Pro is optimized for running 32- bit code (which most modern operating systems and applications use) and so gives a greater performance improvement over the Pentium when using the latest software. Intel Pentium Pro features Slide 26 Wider Address Bus: The address bus on the Pentium Pro is widened to 36 bits, giving it a maximum addressability of 64 GB of memory. Greater Multiprocessing: Quad processor configurations are supported with the Pentium Pro compared to only dual with the Pentium. Out of Order Completion: Instructions flowing down the execution pipelines can complete out of order. Superior Branch Prediction Unit: The branch target buffer is double the size of the Pentium's and its accuracy is increased. Register Renaming: This feature improves parallel performance of the pipelines. Speculative Execution: The Pro uses speculative execution to reduce pipeline stall time in its RISC core. Intel Pentium Pro features Slide 27 Doubled Primary Cache: The Pentium with MMX has 16 KB for each of the level 1 data and instruction caches, as opposed to 8 KB each for the regular Pentium. Improved Cache Mapping: The primary cache is now 4-way set associative instead of 2-way. Deepening of Internal Pipelines: Both of the internal integer executions units are increased from 5 to 6 stages. Better Use of Internal Pipelines: More types of instructions can be run in parallel down the two execution pipes than on the older Pentium, so more use is made of the second pipe. Improved Branch Prediction Unit: The branch prediction unit's accuracy is enhanced over the classic Pentium. Improved Instruction Decoder: The instruction decoder is more efficient than the Pentium's. Intel Pentium MMX (MultiMedia eXtension) features Slide 28 Hyper-threading works by duplicating certain sections of the processorthose that store the architectural statebut not duplicating the main execution resources. This allows a hyper-threading processor to appear as two "logical" processors to the host operating system, allowing the operating system to schedule two threads or processes simultaneously. When execution resources would not be used by the current task in a processor without hyper-threading, and especially when the processor is stalled, a hyper-threading equipped processor can use those execution resources to execute another scheduled task. Concept of hyper threading Slide 29 The processor may stall due to a cache miss, branch misprediction, or data dependency. This technology is transparent to operating systems and programs. The minimum that is required to take advantage of hyper-threading is symmetric multiprocessing (SMP) support in the operating system, as the logical processors appear as standard separate processors. It is possible to optimize operating system behavior on multi- processor hyper-threading capable systems. Concept of hyper threading Slide 30 The advantages of hyper-threading are listed as: - improved support for multi-threaded code - allowing multiple threads to run simultaneously - improved reaction and response time. Concept of hyper threading Slide 31 Core 2 duo processor Core 2 is dual core architecture. That means there are two independent CPU cores on the same die. The first Intel dual core CPU was the Pentium D introduced in spring of 2005. Each core on the Core 2 has independent L1 caches. Early dual-core CPUs had independent L2 caches as well. Core 2 has a unified L2 cache of either 2MB or 4MB. That means when data is required on both cores only one set of data need be passed instead of two on two separate L2 caches. Core 2 supports all current instruction sets, including the x86 instruction set, the Multimedia eXtensions introduced with the Pentium MMX CPU Slide 32 Core 2 duo processor architecture