Embed Size (px)
Citation preview
®
Gate ArrayXC5200 Family
A Low-cost Gate Array Alternative
®
www.xilinx.com
XC5200 FPGA Family
Up to 23,000 gates
50-MHz system performance
Robust feature set
Unlimited reprogrammability
Pin-locking flexibility: VersaRingTM routing
5V devices
®
www.xilinx.com
XC5200 Family Features
Gate array replacement success since 1995— World’s fastest 5V FPGA volume ramp
A low cost FPGA/gate array alternative— Low cost, process-optimized architecture — 5V, 0.5 micron process
High performance with robust feature set— Carry logic 3-state buffers— Cascade chain 4 global nets— JTAG logic Slew rate control
®
www.xilinx.com
XC5200 Architecture Overview
Architecture highlights— VersaBlockTM logic
module— VersaRing I/O interface— General Routing Matrix
(GRM)
®
www.xilinx.com
Abundant VersaBlock Routing VersaBlock equals:
— Configurable Logic Block (CLB)– 4 identical Logic Cells – 4 3-state buffers
— Local Interconnect Matrix (LIM)– 100% local connectivity– Up to 23 in, 8 out
— Direct connects Result: abundant local
routing— Minimizes routing
congestion— Granular and symmetrical
®
www.xilinx.com
XC5200 Configurable Logic Block
Configurable Logic Block (CLB)— 4 identical Logic Cells— 20 inputs, 12 outputs— 2 5-input functions
Logic Cell (LC0 - LC3)— Function generator,
register, & control logic— Independently usable F &
FD— Programmable flip-flop or
latch — Fast carry logic or cascade
chain— Independent feed-through
®
www.xilinx.com
carry out
XC5200 Carry Logic: 4-bit Adder
®
www.xilinx.com
XC5200 Cascade Chain:16-bit Decoder
Fast implementation of wide input functions
Adjacent CY_MUX connects to provide cascadable decode logic
Flexible LUT allows general decode, AND and OR cascade chains
®
www.xilinx.com
XC5200 FamilyEfficient 5-Input Functions
Allows any combination of 2 separate 5-input functions in one CLB
LC0 and LC1 and/or LC2 and LC3 combined with F5_MUX
Unified library support:— F5MAP or F5_MUX
Efficient 4:1 muxes
®
www.xilinx.com
Optimizing 5-Input Functions
Both schematics will result in identical implementations
Five input AND using F5_MUX Five input AND using F5MAP- or -
®
www.xilinx.com
Implementing 4:1 MUX Using F5_MUX
Allows 4:1 muxes in 1/2 CLB
®
www.xilinx.com
SingleLengthLines
DoubleLengthLines
DirectConnects
Longlines
LocalInterconnect
Matrix
Abundant Routing Resources
Six Levels of Hierarchy
General Routing Matrix— 10 single-length lines— 4 double-length lines— 8 long lines per channel
VersaBlock— Local Interconnect Matrix— Direct connects to all
neighbors— Logic cell feedthrough
®
www.xilinx.com
XC5200 Global Line Network
4 global clock buffers
Direct access to all CLB clock pins (CK)
Access to non-clock pins via GRM
Buffers can be sourced by IOB or internal routing
®
www.xilinx.com
XC5200 TBUF Connectivity
Four TBUFs/CLB
Any CLB output can drive any TBUF
“Weak-keeper” circuit maintains previous state
No pull-ups; use cascade chain for wired functions
®
www.xilinx.com
VersaRingTM: High Utilization AND Pin Assignment Flexibility
Versatile interface between internal logic and I/O— I/O decoupled from core
logic— Incremental edge routing
VersaRing resources— 8 horizontal/vertical
longlines— 4 direct-connects in/out— 4 double-length lines to
GRM— 10 single-length lines to
GRM— 8 single-length lines to
adjacent VersaRing tile
®
www.xilinx.com
XC5200 Input/Output Block
Selectable input, output or 3-state
Optional pull-up/pull-down
Dedicated boundary scan logic
8-mA output sink & source current
4 global nets
Programmable slew rate control
Programmable input delay line
®
www.xilinx.com
XC5202 XC5204 XC5206 XC5210 XC5215Max Logic Gates 3,000 6,000 10,000 16,000 23,000Typical Gate Range 2-3K 4-6K 6-10K 10-16K 15-23KLogic Cells 256 480 784 1,296 1,936Flip-Flops 256 480 784 1,296 1,936Max I/O 81 124 148 196 197Performance -6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3Packages: VQ64
PC84 PC84 PC84 PC84PQ/VQ100 PQ/VQ100PQ/VQ100
TQ144 TQ144 TQ144PQ160 PQ160 PQ160 PQ160
PQ208 PQ208 HQ208PQ240 HQ240
100% Footprint Compatibility in Common Packages
XC5200 Family
®
www.xilinx.com
XC5200 support to year 2005 and beyond
XC5200 Success Since 1994
RevenueUnits
High Volume Design Wins• Digital camera add-in card• Cable modem• Set-up box• Video game• CD player• Graphics add-in card• 10/100 Mbit Ethernet add-in cards
High Volume Design Wins• Digital camera add-in card• Cable modem• Set-up box• Video game• CD player• Graphics add-in card• 10/100 Mbit Ethernet add-in cards
®
www.xilinx.com
Market Application VolumeConsumer-Video Set Top Box 150,000 unitsConsumer-Audio High-end CD Player 25,000 unitsConsumer-Video Video Game 50,000 unitsData Processing PC Add-in Card 250,000 unitsData Processing Display Monitor 100,000 unitsCommunication PCS Base Station 25,000 unitsCommunication Modem Card 100,000 unitsCommunication Voice Mail 50,000 unitsAutomotive Shock Absorber Control >100,000 units
XC5200 Series Success
®
www.xilinx.com
Xilinx XC5200 vs. Altera Flex 6K
XC5200 Advantages— Segmented interconnect— Lower power— Five XC5200 devices vs. three 6K devices— More features (flip-flop clock enables, cell feed-
through, VersaRing, VersaBlock, etceteras.)
Altera Flex 6K is a poor copy of the innovative XC5200 architecture
®
www.xilinx.com
Feature XC5200 Flex 6K
Clock enable Yes No
Direct feed-through Yes No
Independent logic & flip-flop outputs Yes No
Clocks per flip-flop 1:4 2:10
Logic Cells per block 4 10
Logic Cell Comparison
®
www.xilinx.com
XC5200 Benefit Summary
Process optimized architecture— Small die size— Unlimited reprogrammability— Up to 50-MHz performance
VersaRing I/O interface— Pin assignment flexibility— Logic change flexibility without requiring PCB relayout
100% footprint compatibility— Easy density migration within family
®
www.xilinx.com
XC5200 Robust System Level Features
Fast carry logic — High-speed arithmetic functions
Dedicated JTAG logic— Eases system-level testability
3-state buffers— Efficient on-chip bussing
Cascade chain— Efficient wide-input functions
