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© H. Heck 2008 Section 4.4 1
Module 4: Metrics & MethodologyTopic 4: Recovered Clock Timing
OGI EE564
Howard HeckTsetup Thold
clk
in
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Where Are We?
1. Introduction
2. Transmission Line Basics
3. Analysis Tools
4. Metrics & Methodology1. Synchronous Timing
2. Signal Quality
3. Source Synchronous Timing
4. Recovered Clock Timing
5. Design Methodology
5. Advanced Transmission Lines
6. Multi-Gb/s Signaling
7. Special Topics
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Why Another Clocking Scheme?
2 Problems of interest: What do we do when we’re trying to communicate
between devices that don’t have a “common clock?” e.g. an external device? Both devices will have clocks, but those clocks will not have
a known phase relationship. We have to deal with it. What do we do when we’re sending data at multi-GTs
speeds, while low cost system clocks operate below 1 GHz?
In such cases, we typically do not send an explicit clock signal to the devices at all.
Instead, we “extract” the clock information from the data stream.
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Contents
GoalTiming Relationships & EquationsExample System & OperationSummary
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Goals
Our goal is to establish and maintain a desired phase relationship between DCLK and RCLK in order to ensure that we successfully transmit and receive data.
The phase relationship between the system clock inputs cannot be predetermined or directly controlled, so we must do it locally on each device.
We can also use the local adjustment circuitry to generate high frequency local clocks for controlling the data transfer.
D Q D Q
Data from Core
Din
LatchTx
Latch
RxAB
DCLK RCLK
Dout
System Clock #1
Clock Adjust
System Clock #2
Clock Adjust
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Data-Clock Phase Relationship
The receiver clock recovery circuitry attempts to center the receiver clock in the data eye. i.e. maintain a 90 offset
between B and RCLK.
Accounting for driver and interconnect delay, the desired phase relationship between DCLK and RCLK is:
90°
RCLK
Data @ B
TCO
DCLK
Data @ ATflight
T
90flightCO TTT
Jitter on the driver, receiver, and interconnect, and frequency differences between will degrade the phase relationship (i.e. setup/hold margin) between B and RCLK.
D Q D Q
Data from Core
Din
LatchTx
Latch
RxAB
DCLK RCLK
Dout
System Clock #1
Clock Adjust
System Clock #2
Clock Adjust
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Phase Relationship - Setup Worst case setup case:
TCO & Tflight increase
DCLK pushes out RCLK pulls in
The corresponding DCLK to RCLK relationship is shown below:
RCLKTDCLKT
TT
TTT
pullinpushout
pushoutflightpushoutCO
nomflightnomCOsetup
,,
,,,
90
Tco,max and Tflight,max are taken over M cycles. They include ISI, crosstalk, SSO, etc.
Tpushout(DCLK) is the maximum pushout of the driver clock after M cycles w.r.t. to the edge at the 1st cycle.
Tpullin(RCLK) is the maximum pullin of the receiver clock after M cycles w.r.t. to the edge at the 1st cycle.
RCLK
Data @ B
DCLK
Data @ A
Tpushout(DCLK)
TCO,max = Tco + Tco,pushout
Tflight,max = Tflight + Tflight,pushout
Tpullin(RCLK)
90° - (Tflight,pushout + TCO,pushout)
- Tpullin(RCLK) - T pushout(DCLK)
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Phase Relationship - Hold Worst case setup case:
TCO & Tflight decrease
DCLK pulls in RCLK pushes out
The corresponding DCLK to RCLK relationship is shown below:
RCLKTDCLKT
TT
TTT
pushoutpullin
pullinflightpullinCO
nomflightnomCOhold
,,
,,,
90
Tco,min and Tflight,min are taken over M cycles. They include ISI, crosstalk, SSO, etc.
Tpullin(DCLK) is the maximum pullin of the driver clock after M cycles w.r.t. to the edge at the 1st cycle.
Tpushout(RCLK) is the maximum pushout of the receiver clock after M cycles w.r.t. to the edge at the 1st cycle.
RCLK
Data @ B
DCLK
Data @ A
Tpullin(DCLK)
TCO,min = TCO - TCO,pullin
Tflight,min = Tflight - Tflight,pullin
Tpushout(RCLK,)90° - (Tflight,pullin + TCO,pullin)
- Tpullin(DCLK,) - Tpushout(RCLK)
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Setup & Hold Equations (Skipping the derivation)
Define Tx, Rx, and flight time jitter: Tx jitter (TTX,max) is maximum phase uncertainty of transmitted
data including variation in the local clock. Rx jitter (RX,max) is maximum phase uncertainty of received data
including variation in the local clock. Flight time jitter (lightmax) is maximum phase uncertainty of the
interconnect flight time All quantities are positive for setup, negative for hold
• Keeps with previous conventions
Ideal phase relationship between data edge at the receiver input and RCLK.
Here are the simplified setup & hold equations:
setupcyclesmflightTXRXsetupinm TTTTTT max,max,max,_arg
90 flightco TTT
holdflightRXTXholdinm TTTTTT -cycles 1mmax,cycles mmax,cycles 1mmax,_arg
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Example Extracted Clock System
System clock (SCLK) is multiplied by N to produce higher frequency at C.
The local clock is phase aligned to the output of the loop filter, producing local clock, DCLK.
DCLK is divided by N , and the phase of D is compared to the system clock, SCLK, producing E.
Phase error is averaged over several clock cycles by the loop filter and fed back to the clock adjustment circuit (F).
System Clock
Frequency Multiplier
Clock Adjust
Divide by NPhase
ComparatorLoop Filter
D Q
Clock Adjust
Phase Comparator
Loop Filter
D Q
Clock
Data from Core
Din
Latch
Driver
Latch
ReceiverA
B
DCLK
SCLK
F
D ECG
H
JRCLK
Dout
90°
I
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Example Extracted Clock System (2)
The feedback loop described on the previous slide is designed to lock DCLK to an exact multiple of SCLK, providing a stable high frequency clock for the transmitter.
SCLKDCLK fNf DCLK controls the latching of data to the transmitter (A). The data bit travels down the line to the receiver (B).
System Clock
Frequency Multiplier
Clock Adjust
Divide by NPhase
ComparatorLoop Filter
D Q
Clock Adjust
Phase Comparator
Loop Filter
D Q
Clock
Data from Core
Din
Latch
Driver
Latch
ReceiverA
B
DCLK
SCLK
F
D ECG
H
JRCLK
Dout
90°
I
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Example Extracted Clock System (3)
Data at B is latched by RCLK , which has the same frequency as DCLK. RCLK may or may not have the same system clock source as DCLK.
The delay element shifts RCLK 90 out of phase from B to center the clock in the data bit, with adjustment by the phase comparator/filter/clock adjust loop.
Note that the loop time constant is several cycles, so it does not correct high frequency phase deviations.
System Clock
Frequency Multiplier
Clock Adjust
Divide by NPhase
ComparatorLoop Filter
D Q
Clock Adjust
Phase Comparator
Loop Filter
D Q
Clock
Data from Core
Din
Latch
Driver
Latch
ReceiverA
B
DCLK
SCLK
F
D ECG
H
JRCLK
Dout
90°
I
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Question
What requirement does the periodic clock adjustment place on the operation of a channel that uses an extracted clock?
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References
S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1st edition.
W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.
R. Poon, Computer Circuits Electrical Design, Prentice Hall, 1st edition, 1995.
H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, 1990.
H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, PTR Prentice Hall, 1993.
S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley and Sons, New York, 1998.
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Appendix: Extracted Clock Equation Derivation
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Clock Drift
Assuming DCLK is updated every M cycles, the phase error quantifies how much the Mth DCLK edge deviates from the placement of the Mth RefCLK edge.
Deterministic noise is caused by sources such as power supply switching, temperature variation, bus noise, and spread spectrum clocking.
Gaussian noise is random, which noise, not correlated to any specific source, and will tend to average zero over time.
RefCLK
DCLK(Drift)
N = 1 N = 2 N = M - 1 N = M
= 0 = Tdrift = Tdrift,deterministic + Tdrift,Gaussian
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Clock Drift & Adjustment
Variations in flight time and driver delay degrade the phase relationship, and therefore the setup/hold window.
Both clocks drift with time, and are adjusted periodically, depending on PLL bandwidth, clock extraction circuits, and Tco and Tflight variations.
Interconnect variations tend to be higher frequency, and are not compensated by the clock extraction circuits.
RCLKadjustT
)2( MNT
Cycles(N)
Hold Requirement Hold side marginholdT ,
Setup RequirementSetup side Margin
N=1
N=M
N=2M
N=P
High Frequency Interconnect Noise
Low frequency drift between Dclk and Rclk
setupT ,
idealT ,
DCLKadjustT)1( NerrorT
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Data Path Delay
SCLK
RefCLK
DCLK(Drift)
DCLK(Drift +Correction)
Data@ Driver
Data@ Receiver
MTcycle
Tdrift(DCLK)
Tadj(DCLK)
TCO
Tflight
t
M cycles
MNflight
MNCOadjdriftcycledata TTDCLKTDCLKTMTT [8.3.4]
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Clock Path Delay
RCLKTRCLKTTMTT adjdriftcycleclk [8.3.5]
SCLK
RefCLK
RCLK(Drift)
RCLK(Drift + Correction)
MTcycle + Tdrift(BCLK)
Tadj(BCLK)
t
M cycles
T
errorNflight
Nco TTTT
1190
[8.3.6]
Phase difference, T is:
T is the phase error at calibration (N=1).
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Setup Loop
TRCLKTTMRCLKT
TTTTDCLKTDCLKTTM
driftcycleadj
setupinmMN
flightMN
COadjdriftcycle
0 arg[8.3.7]
SCLK
RefCLK
DCLK(Drift)
DCLK(Drift +Correction)
Data@ Driver
Data@ Receiver
MTcycle
Tdrift(DCLK)
Tadj(DCLK)
TCO
Tflight
t
M cycles
RCLK(Drift)
RCLK(Drift +Correction)
MTcycle + Tdrift(BCLK)
Tadj(BCLK)
T
Tsetup
Tmargin
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Setup Equation
Starting with the loop equation:
TRCLKTTMRCLKT
TTTTDCLKTDCLKTTM
driftcycleadj
setupinmMN
flightMN
COadjdriftcycle
0 arg[8.3.7]
111190 N
flightN
coerrorNflight
Nco TTTTTTT
Define the initial phase offset, T:
errorTT 90
[8.3.8]
[8.3.9]
Simplify the loop equation:
setup
MNflight
MNCOadjdrift
Nflight
NCOdriftadjinm
TTTDCLKTDCLKT
TTTRCLKTRCLKTT
11arg
setup
Nflight
MNflight
NCO
MNCO
driftdriftadjadjinm
TTTTT
RCLKTDCLKTRCLKTDCLKTTT
11
arg
[8.3.10]
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Setup Equation #2
Define worst case transmitter and flight times for the setup case:
Simplify the loop equation:
setup
Nflight
MNflight
NCO
MNCO
driftdriftadjadjinm
TTTTT
RCLKTDCLKTRCLKTDCLKTTT
11
arg
[8.3.11]
flightT T
Mn
n
flight
2
max, max
1min,
NCOco TT
1min,
Nflightflight TT
coT TMn
n
co
2
max, max
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Setup Equation #3 Define worst case transmitter, receiver, and flight
time variation:
Rewrite the loop equation:
setupcyclesmerconnectrtransmittereceiverinm TTTTTT max,intmax,max,arg [8.3.16]
cyclesMflightflighterconnect TTT min,max,max,int
cyclesMcocoadjdriftrtransmitte TTDCLKTDCLKTT min,max,max,max,max,
cyclesMadjdriftreceiver RCLKTRCLKTT min,min,min,
[8.3.14]
[8.3.13]
[8.3.12]
Maximum data signal pushout w.r.t. refCLK over M cycles.
Minimum pull-in of RCLK w.r.t. refCLK over M cycles.
Maximum flight time variation over M cycles.
errorTT 90min, [8.3.15]
Minimum phase relationship between data edge at the receiver input and RCLK..
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Hold Loop
TRCLKTTMRCLKTTT
TTDCLKTDCLKTTM
driftcycleadjinmhold
MNflight
MNCOadjdriftcycle
arg
11
10[8.3.17]
SCLK
RefCLK
DCLK(Drift)
DCLK(Drift +Correction)
Data@ Driver
Data@ Receiver
(M + 1) Tcycle
Tdrift(DCLK)
Tadj(DCLK)
TCO
Tflight
t
M cycles
RCLK(Drift)
RCLK(Drift +Correction)
M Tcycle + Tdrift(RCLK)
Tadj(RCLK)
T
Thold
Tmargin
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Hold Equation
Starting with the loop equation:
[8.3.17]
1801 cyclecyclecycle TTMTM
Use the phase relationship:
[8.3.19]
[8.3.9]
TRCLKTTMRCLKTTT
TTDCLKTDCLKTTM
driftcycleadjinmhold
MNflight
MNCOadjdriftcycle
arg
11
10
111190 N
flightN
coerrorNflight
Nco TTTTTTT
hold
MNflight
MNCOadjdrift
cycledriftcycleadjinm
TTTDCLKTDCLKT
TMTRCLKTTMRCLKTT
-
111
arg
[8.3.18]
Recall:
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Hold Equation #2
Work with the loop equation:
[8.3.18]
holdMN
flightMN
COadjdrift
cycledriftcycleadjinm
TTTDCLKTDCLKT
TMTRCLKTTMRCLKTT
-
111
arg
holdMN
flightMN
COadjdrift
errorcycle
Nflight
Ncodriftadjinm
TTTDCLKTDCLKT
TTMM
TTRCLKTRCLKTT
-
190 11
11arg
holdMN
flightMN
COadjdrift
error
Nflight
Ncodriftadjinm
TTTDCLKTDCLKT
T
TTRCLKTRCLKTT
-
90 11
11arg
hold
MNCO
Ncoadjdrift
MNflight
Nflightdriftadjinm
TT
TTDCLKTDCLKT
TTRCLKTRCLKTT
-
max
1max,
1min,
1max,
1max,arg
[8.3.20]
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Hold Equation #3
[8.3.20]
Define:
[8.3.24]
holderror
MNCO
Ncoadjdrift
MNflight
Nflightdriftadjinm
TT
TTDCLKTDCLKT
TTRCLKTRCLKTT
-90
1max,
1min,
1max,
1max,arg
cyclesMflightflighterconnect TTT max,min,min,int
cyclesMcocoadjmubdriftrtransmitte TTDCLKTDCLKTT min,max,min,,min,
cyclesMadjdriftreceiver RCLKTRCLKTT max,max,max,
[8.3.23]
[8.3.22]
[8.3.21]
Minimum data signal pullin w.r.t. refCLK over M+1 cycles.
Maximum pushout of RCLK w.r.t. refCLK over M cycles.
Minimum flight time variation over M+1 cycles.
errorTT 90max,
Maximum phase relationship between data edge at the receiver input and RCLK..
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Hold Equation #4
[8.3.25]
Finally:
holderconnectreceiverrtransmitteinm TTTTTT -cycles 1mmin,intcycles mmax,cycles 1mmin,maxarg